llvm-project/llvm/test/CodeGen/ARM/ispositive.ll

; RUN: llc < %s -march=arm | FileCheck %s

define i32 @test1(i32 %X) {
; CHECK: lsr{{.*}}#31
entry:
        icmp slt i32 %X, 0              ; <i1>:0 [#uses=1]
        zext i1 %0 to i32               ; <i32>:1 [#uses=1]
        ret i32 %1
}
Fix the rest of the ARM failures by converting them to FileCheck. llvm-svn: 85208 2009-10-27 14:16:45 +08:00			`; RUN: llc < %s -march=arm \| FileCheck %s`
new testcase llvm-svn: 35882 2007-04-11 13:32:13 +08:00
change test name. llvm-svn: 35904 2007-04-11 23:24:04 +08:00			`define i32 @test1(i32 %X) {`
Update tests to handle MC-inst instruction printing of shift operations. The legacy asm printer uses instructions of the form, "mov r0, r0, lsl #3", while the MC-instruction printer uses the form "lsl r0, r0, #3". The latter mnemonic is correct and preferred according the ARM documentation (A8.6.98). The former are pseudo-instructions for the latter. llvm-svn: 114221 2010-09-18 05:58:46 +08:00			`; CHECK: lsr{{.*}}#31`
new testcase llvm-svn: 35882 2007-04-11 13:32:13 +08:00			`entry:`
			`icmp slt i32 %X, 0 ; <i1>:0 [#uses=1]`
			`zext i1 %0 to i32 ; <i32>:1 [#uses=1]`
			`ret i32 %1`
			`}`