2018-11-27 05:47:28 +08:00
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//===- AArch64SchedPredicates.td - AArch64 Sched Preds -----*- tablegen -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defines scheduling predicate definitions that are used by the
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// AArch64 subtargets.
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//
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//===----------------------------------------------------------------------===//
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// Function mappers.
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2018-12-11 00:24:30 +08:00
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// Check the extension type in arithmetic instructions.
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let FunctionMapper = "AArch64_AM::getArithExtendType" in {
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def CheckExtUXTB : CheckImmOperand_s<3, "AArch64_AM::UXTB">;
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def CheckExtUXTH : CheckImmOperand_s<3, "AArch64_AM::UXTH">;
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def CheckExtUXTW : CheckImmOperand_s<3, "AArch64_AM::UXTW">;
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def CheckExtUXTX : CheckImmOperand_s<3, "AArch64_AM::UXTX">;
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def CheckExtSXTB : CheckImmOperand_s<3, "AArch64_AM::SXTB">;
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def CheckExtSXTH : CheckImmOperand_s<3, "AArch64_AM::SXTH">;
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def CheckExtSXTW : CheckImmOperand_s<3, "AArch64_AM::SXTW">;
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def CheckExtSXTX : CheckImmOperand_s<3, "AArch64_AM::SXTX">;
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}
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// Check for shifting in extended arithmetic instructions.
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foreach I = {0-3} in {
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let FunctionMapper = "AArch64_AM::getArithShiftValue" in
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def CheckExtBy#I : CheckImmOperand<3, I>;
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}
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2018-11-27 05:47:28 +08:00
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// Check the extension type in the register offset addressing mode.
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let FunctionMapper = "AArch64_AM::getMemExtendType" in {
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2018-12-11 00:24:30 +08:00
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def CheckMemExtUXTW : CheckImmOperand_s<3, "AArch64_AM::UXTW">;
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def CheckMemExtLSL : CheckImmOperand_s<3, "AArch64_AM::UXTX">;
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def CheckMemExtSXTW : CheckImmOperand_s<3, "AArch64_AM::SXTW">;
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def CheckMemExtSXTX : CheckImmOperand_s<3, "AArch64_AM::SXTX">;
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2018-11-27 05:47:28 +08:00
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}
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// Check for scaling in the register offset addressing mode.
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let FunctionMapper = "AArch64_AM::getMemDoShift" in
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2018-12-11 00:24:30 +08:00
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def CheckMemScaled : CheckImmOperandSimple<3>;
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// Check the shifting type in arithmetic and logic instructions.
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let FunctionMapper = "AArch64_AM::getShiftType" in {
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def CheckShiftLSL : CheckImmOperand_s<3, "AArch64_AM::LSL">;
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def CheckShiftLSR : CheckImmOperand_s<3, "AArch64_AM::LSR">;
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def CheckShiftASR : CheckImmOperand_s<3, "AArch64_AM::ASR">;
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def CheckShiftROR : CheckImmOperand_s<3, "AArch64_AM::ROR">;
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def CheckShiftMSL : CheckImmOperand_s<3, "AArch64_AM::MSL">;
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}
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// Check for shifting in arithmetic and logic instructions.
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foreach I = {0-3, 8} in {
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let FunctionMapper = "AArch64_AM::getShiftValue" in
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def CheckShiftBy#I : CheckImmOperand<3, I>;
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}
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2018-11-27 05:47:28 +08:00
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// Generic predicates.
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2018-12-11 00:24:30 +08:00
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// Identify whether an instruction is the 64-bit NEON form based on its result.
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def CheckDForm : CheckAll<[CheckIsRegOperand<0>,
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CheckAny<[CheckRegOperand<0, D0>,
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CheckRegOperand<0, D1>,
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CheckRegOperand<0, D2>,
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CheckRegOperand<0, D3>,
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CheckRegOperand<0, D4>,
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CheckRegOperand<0, D5>,
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CheckRegOperand<0, D6>,
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CheckRegOperand<0, D7>,
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CheckRegOperand<0, D8>,
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CheckRegOperand<0, D9>,
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CheckRegOperand<0, D10>,
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CheckRegOperand<0, D11>,
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CheckRegOperand<0, D12>,
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CheckRegOperand<0, D13>,
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CheckRegOperand<0, D14>,
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CheckRegOperand<0, D15>,
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CheckRegOperand<0, D16>,
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CheckRegOperand<0, D17>,
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CheckRegOperand<0, D18>,
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CheckRegOperand<0, D19>,
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CheckRegOperand<0, D20>,
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CheckRegOperand<0, D21>,
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CheckRegOperand<0, D22>,
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CheckRegOperand<0, D23>,
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CheckRegOperand<0, D24>,
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CheckRegOperand<0, D25>,
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CheckRegOperand<0, D26>,
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CheckRegOperand<0, D27>,
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CheckRegOperand<0, D28>,
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CheckRegOperand<0, D29>,
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CheckRegOperand<0, D30>,
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CheckRegOperand<0, D31>]>]>;
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// Identify whether an instruction is the 128-bit NEON form based on its result.
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def CheckQForm : CheckAll<[CheckIsRegOperand<0>,
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CheckAny<[CheckRegOperand<0, Q0>,
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CheckRegOperand<0, Q1>,
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CheckRegOperand<0, Q2>,
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CheckRegOperand<0, Q3>,
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CheckRegOperand<0, Q4>,
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CheckRegOperand<0, Q5>,
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CheckRegOperand<0, Q6>,
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CheckRegOperand<0, Q7>,
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CheckRegOperand<0, Q8>,
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CheckRegOperand<0, Q9>,
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CheckRegOperand<0, Q10>,
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CheckRegOperand<0, Q11>,
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CheckRegOperand<0, Q12>,
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CheckRegOperand<0, Q13>,
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CheckRegOperand<0, Q14>,
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CheckRegOperand<0, Q15>,
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CheckRegOperand<0, Q16>,
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CheckRegOperand<0, Q17>,
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CheckRegOperand<0, Q18>,
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CheckRegOperand<0, Q19>,
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CheckRegOperand<0, Q20>,
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CheckRegOperand<0, Q21>,
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CheckRegOperand<0, Q22>,
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CheckRegOperand<0, Q23>,
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CheckRegOperand<0, Q24>,
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CheckRegOperand<0, Q25>,
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CheckRegOperand<0, Q26>,
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CheckRegOperand<0, Q27>,
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CheckRegOperand<0, Q28>,
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CheckRegOperand<0, Q29>,
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CheckRegOperand<0, Q30>,
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CheckRegOperand<0, Q31>]>]>;
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2018-11-27 05:47:46 +08:00
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// Identify arithmetic instructions with extend.
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2018-12-11 00:24:30 +08:00
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def IsArithExt32Op : CheckOpcode<[ADDWrx, ADDXrx, ADDSWrx, ADDSXrx,
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SUBWrx, SUBXrx, SUBSWrx, SUBSXrx]>;
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def IsArithExt64Op : CheckOpcode<[ADDXrx64, ADDSXrx64,
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SUBXrx64, SUBSXrx64]>;
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def IsArithExtOp : CheckOpcode<!listconcat(IsArithExt32Op.ValidOpcodes,
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IsArithExt64Op.ValidOpcodes)>;
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// Identify arithmetic immediate instructions.
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def IsArithImmOp : CheckOpcode<[ADDWri, ADDXri, ADDSWri, ADDSXri,
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SUBWri, SUBXri, SUBSWri, SUBSXri]>;
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2018-11-27 05:47:46 +08:00
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2018-11-27 05:47:41 +08:00
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// Identify arithmetic instructions with shift.
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2018-12-11 00:24:30 +08:00
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def IsArithShiftOp : CheckOpcode<[ADDWrs, ADDXrs, ADDSWrs, ADDSXrs,
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SUBWrs, SUBXrs, SUBSWrs, SUBSXrs]>;
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// Identify arithmetic instructions without shift.
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def IsArithUnshiftOp : CheckOpcode<[ADDWrr, ADDXrr, ADDSWrr, ADDSXrr,
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SUBWrr, SUBXrr, SUBSWrr, SUBSXrr]>;
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// Identify logic immediate instructions.
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def IsLogicImmOp : CheckOpcode<[ANDWri, ANDXri,
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EORWri, EORXri,
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ORRWri, ORRXri]>;
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2018-11-27 05:47:41 +08:00
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// Identify logic instructions with shift.
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2018-12-11 00:24:30 +08:00
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def IsLogicShiftOp : CheckOpcode<[ANDWrs, ANDXrs, ANDSWrs, ANDSXrs,
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BICWrs, BICXrs, BICSWrs, BICSXrs,
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EONWrs, EONXrs,
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EORWrs, EORXrs,
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ORNWrs, ORNXrs,
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ORRWrs, ORRXrs]>;
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// Identify logic instructions without shift.
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def IsLogicUnshiftOp : CheckOpcode<[ANDWrr, ANDXrr, ANDSWrr, ANDSXrr,
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BICWrr, BICXrr, BICSWrr, BICSXrr,
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EONWrr, EONXrr,
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EORWrr, EORXrr,
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ORNWrr, ORNXrr,
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ORRWrr, ORRXrr]>;
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// Identify arithmetic and logic immediate instructions.
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def IsArithLogicImmOp : CheckOpcode<!listconcat(IsArithImmOp.ValidOpcodes,
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IsLogicImmOp.ValidOpcodes)>;
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2018-11-27 05:47:41 +08:00
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// Identify arithmetic and logic instructions with shift.
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2018-12-11 00:24:30 +08:00
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def IsArithLogicShiftOp : CheckOpcode<!listconcat(IsArithShiftOp.ValidOpcodes,
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IsLogicShiftOp.ValidOpcodes)>;
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// Identify arithmetic and logic instructions without shift.
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def IsArithLogicUnshiftOp : CheckOpcode<!listconcat(IsArithUnshiftOp.ValidOpcodes,
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IsLogicUnshiftOp.ValidOpcodes)>;
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// Identify whether an instruction whose result is a long vector
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// operates on the upper half of the input registers.
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def IsLongVectorUpperOp : CheckOpcode<[FCVTLv8i16, FCVTLv4i32,
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FCVTNv8i16, FCVTNv4i32,
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FCVTXNv4f32,
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PMULLv16i8, PMULLv2i64,
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RADDHNv8i16_v16i8, RADDHNv4i32_v8i16, RADDHNv2i64_v4i32,
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RSHRNv16i8_shift, RSHRNv8i16_shift, RSHRNv4i32_shift,
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RSUBHNv8i16_v16i8, RSUBHNv4i32_v8i16, RSUBHNv2i64_v4i32,
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SABALv16i8_v8i16, SABALv8i16_v4i32, SABALv4i32_v2i64,
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SABDLv16i8_v8i16, SABDLv8i16_v4i32, SABDLv4i32_v2i64,
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SADDLv16i8_v8i16, SADDLv8i16_v4i32, SADDLv4i32_v2i64,
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SADDWv16i8_v8i16, SADDWv8i16_v4i32, SADDWv4i32_v2i64,
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SHLLv16i8, SHLLv8i16, SHLLv4i32,
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SHRNv16i8_shift, SHRNv8i16_shift, SHRNv4i32_shift,
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SMLALv16i8_v8i16, SMLALv8i16_v4i32, SMLALv4i32_v2i64,
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SMLALv8i16_indexed, SMLALv4i32_indexed,
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SMLSLv16i8_v8i16, SMLSLv8i16_v4i32, SMLSLv4i32_v2i64,
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SMLSLv8i16_indexed, SMLSLv4i32_indexed,
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SMULLv16i8_v8i16, SMULLv8i16_v4i32, SMULLv4i32_v2i64,
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SMULLv8i16_indexed, SMULLv4i32_indexed,
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SQDMLALv8i16_v4i32, SQDMLALv4i32_v2i64,
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SQDMLALv8i16_indexed, SQDMLALv4i32_indexed,
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SQDMLSLv8i16_v4i32, SQDMLSLv4i32_v2i64,
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SQDMLSLv8i16_indexed, SQDMLSLv4i32_indexed,
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SQDMULLv8i16_v4i32, SQDMULLv4i32_v2i64,
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SQDMULLv8i16_indexed, SQDMULLv4i32_indexed,
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SQRSHRNv16i8_shift, SQRSHRNv8i16_shift, SQRSHRNv4i32_shift,
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SQRSHRUNv16i8_shift, SQRSHRUNv8i16_shift, SQRSHRUNv4i32_shift,
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SQSHRNv16i8_shift, SQSHRNv8i16_shift, SQSHRNv4i32_shift,
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SQSHRUNv16i8_shift, SQSHRUNv8i16_shift, SQSHRUNv4i32_shift,
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SQXTNv16i8, SQXTNv8i16, SQXTNv4i32,
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SQXTUNv16i8, SQXTUNv8i16, SQXTUNv4i32,
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SSHLLv16i8_shift, SSHLLv8i16_shift, SSHLLv4i32_shift,
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SSUBLv16i8_v8i16, SSUBLv8i16_v4i32, SSUBLv4i32_v2i64,
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SSUBWv16i8_v8i16, SSUBWv8i16_v4i32, SSUBWv4i32_v2i64,
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UABALv16i8_v8i16, UABALv8i16_v4i32, UABALv4i32_v2i64,
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UABDLv16i8_v8i16, UABDLv8i16_v4i32, UABDLv4i32_v2i64,
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UADDLv16i8_v8i16, UADDLv8i16_v4i32, UADDLv4i32_v2i64,
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UADDWv16i8_v8i16, UADDWv8i16_v4i32, UADDWv4i32_v2i64,
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UMLALv16i8_v8i16, UMLALv8i16_v4i32, UMLALv4i32_v2i64,
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UMLALv8i16_indexed, UMLALv4i32_indexed,
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UMLSLv16i8_v8i16, UMLSLv8i16_v4i32, UMLSLv4i32_v2i64,
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UMLSLv8i16_indexed, UMLSLv4i32_indexed,
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UMULLv16i8_v8i16, UMULLv8i16_v4i32, UMULLv4i32_v2i64,
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UMULLv8i16_indexed, UMULLv4i32_indexed,
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UQSHRNv16i8_shift, UQSHRNv8i16_shift, UQSHRNv4i32_shift,
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UQXTNv16i8, UQXTNv8i16, UQXTNv4i32,
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USHLLv16i8_shift, USHLLv8i16_shift, USHLLv4i32_shift,
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USUBLv16i8_v8i16, USUBLv8i16_v4i32, USUBLv4i32_v2i64,
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USUBWv16i8_v8i16, USUBWv8i16_v4i32, USUBWv4i32_v2i64,
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XTNv16i8, XTNv8i16, XTNv4i32]>;
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2018-11-27 05:47:41 +08:00
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2018-11-27 05:47:28 +08:00
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// Identify whether an instruction is a load
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// using the register offset addressing mode.
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2018-12-11 00:24:30 +08:00
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def IsLoadRegOffsetOp : CheckOpcode<[PRFMroW, PRFMroX,
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LDRBBroW, LDRBBroX,
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LDRSBWroW, LDRSBWroX, LDRSBXroW, LDRSBXroX,
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LDRHHroW, LDRHHroX,
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LDRSHWroW, LDRSHWroX, LDRSHXroW, LDRSHXroX,
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LDRWroW, LDRWroX,
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LDRSWroW, LDRSWroX,
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LDRXroW, LDRXroX,
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LDRBroW, LDRBroX,
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LDRHroW, LDRHroX,
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LDRSroW, LDRSroX,
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LDRDroW, LDRDroX]>;
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2018-11-27 05:47:28 +08:00
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// Identify whether an instruction is a load
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// using the register offset addressing mode.
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2018-12-11 00:24:30 +08:00
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def IsStoreRegOffsetOp : CheckOpcode<[STRBBroW, STRBBroX,
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STRHHroW, STRHHroX,
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STRWroW, STRWroX,
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STRXroW, STRXroX,
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STRBroW, STRBroX,
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STRHroW, STRHroX,
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STRSroW, STRSroX,
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STRDroW, STRDroX]>;
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// Identify whether an instruction is a load or
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// store using the register offset addressing mode.
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def IsLoadStoreRegOffsetOp : CheckOpcode<!listconcat(IsLoadRegOffsetOp.ValidOpcodes,
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IsStoreRegOffsetOp.ValidOpcodes)>;
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2018-11-27 05:47:28 +08:00
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// Target predicates.
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2018-12-11 00:24:30 +08:00
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// Identify an instruction that effectively transfers a register to another.
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def IsCopyIdiomFn : TIIPredicate<"isCopyIdiom",
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MCOpcodeSwitchStatement<
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[// MOV {Rd, SP}, {SP, Rn} =>
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// ADD {Rd, SP}, {SP, Rn}, #0
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MCOpcodeSwitchCase<
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[ADDWri, ADDXri],
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MCReturnStatement<
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CheckAll<
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[CheckIsRegOperand<0>,
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CheckIsRegOperand<1>,
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CheckAny<
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[CheckRegOperand<0, WSP>,
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CheckRegOperand<0, SP>,
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CheckRegOperand<1, WSP>,
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CheckRegOperand<1, SP>]>,
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CheckZeroOperand<2>]>>>,
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// MOV Rd, Rm =>
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// ORR Rd, ZR, Rm, LSL #0
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MCOpcodeSwitchCase<
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[ORRWrs, ORRXrs],
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MCReturnStatement<
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CheckAll<
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[CheckIsRegOperand<1>,
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CheckIsRegOperand<2>,
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CheckAny<
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[CheckRegOperand<1, WZR>,
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CheckRegOperand<1, XZR>,
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CheckRegOperand<2, WZR>,
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CheckRegOperand<2, XZR>]>,
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CheckShiftBy0]>>>],
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MCReturnStatement<FalsePred>>>;
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|
def IsCopyIdiomPred : MCSchedPredicate<IsCopyIdiomFn>;
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|
2018-11-27 05:47:46 +08:00
|
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|
// Identify arithmetic instructions with an extended register.
|
2018-12-11 00:24:30 +08:00
|
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|
def RegExtendedFn : TIIPredicate<"hasExtendedReg",
|
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|
|
MCOpcodeSwitchStatement<
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|
[MCOpcodeSwitchCase<
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|
|
IsArithExtOp.ValidOpcodes,
|
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|
MCReturnStatement<
|
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|
CheckNot<CheckZeroOperand<3>>>>],
|
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|
MCReturnStatement<FalsePred>>>;
|
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|
|
def RegExtendedPred : MCSchedPredicate<RegExtendedFn>;
|
2018-11-27 05:47:46 +08:00
|
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|
// Identify arithmetic and logic instructions with a shifted register.
|
2018-12-11 00:24:30 +08:00
|
|
|
def RegShiftedFn : TIIPredicate<"hasShiftedReg",
|
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|
|
|
MCOpcodeSwitchStatement<
|
|
|
|
|
[MCOpcodeSwitchCase<
|
|
|
|
|
IsArithLogicShiftOp.ValidOpcodes,
|
|
|
|
|
MCReturnStatement<
|
|
|
|
|
CheckNot<CheckZeroOperand<3>>>>],
|
|
|
|
|
MCReturnStatement<FalsePred>>>;
|
|
|
|
|
def RegShiftedPred : MCSchedPredicate<RegShiftedFn>;
|
2018-11-27 05:47:41 +08:00
|
|
|
|
2018-11-27 05:47:28 +08:00
|
|
|
// Identify a load or store using the register offset addressing mode
|
|
|
|
|
// with an extended or scaled register.
|
2018-12-11 00:24:30 +08:00
|
|
|
def ScaledIdxFn : TIIPredicate<"isScaledAddr",
|
|
|
|
|
MCOpcodeSwitchStatement<
|
|
|
|
|
[MCOpcodeSwitchCase<
|
|
|
|
|
IsLoadStoreRegOffsetOp.ValidOpcodes,
|
|
|
|
|
MCReturnStatement<
|
|
|
|
|
CheckAny<[CheckNot<CheckMemExtLSL>,
|
|
|
|
|
CheckMemScaled]>>>],
|
|
|
|
|
MCReturnStatement<FalsePred>>>;
|
|
|
|
|
def ScaledIdxPred : MCSchedPredicate<ScaledIdxFn>;
|
|
|
|
|
|
|
|
|
|
// Identify an instruction that effectively resets a FP register to zero.
|
|
|
|
|
def IsZeroFPIdiomFn : TIIPredicate<"isZeroFPIdiom",
|
|
|
|
|
MCOpcodeSwitchStatement<
|
|
|
|
|
[// MOVI Vd, #0
|
|
|
|
|
MCOpcodeSwitchCase<
|
|
|
|
|
[MOVIv8b_ns, MOVIv16b_ns,
|
|
|
|
|
MOVID, MOVIv2d_ns],
|
|
|
|
|
MCReturnStatement<CheckZeroOperand<1>>>,
|
|
|
|
|
// MOVI Vd, #0, LSL #0
|
|
|
|
|
MCOpcodeSwitchCase<
|
|
|
|
|
[MOVIv4i16, MOVIv8i16,
|
|
|
|
|
MOVIv2i32, MOVIv4i32],
|
|
|
|
|
MCReturnStatement<
|
|
|
|
|
CheckAll<
|
|
|
|
|
[CheckZeroOperand<1>,
|
|
|
|
|
CheckZeroOperand<2>]>>>],
|
|
|
|
|
MCReturnStatement<FalsePred>>>;
|
|
|
|
|
def IsZeroFPIdiomPred : MCSchedPredicate<IsZeroFPIdiomFn>;
|
|
|
|
|
|
|
|
|
|
// Identify an instruction that effectively resets a GP register to zero.
|
|
|
|
|
def IsZeroIdiomFn : TIIPredicate<"isZeroIdiom",
|
|
|
|
|
MCOpcodeSwitchStatement<
|
|
|
|
|
[// ORR Rd, ZR, #0
|
|
|
|
|
MCOpcodeSwitchCase<
|
|
|
|
|
[ORRWri, ORRXri],
|
|
|
|
|
MCReturnStatement<
|
|
|
|
|
CheckAll<
|
|
|
|
|
[CheckIsRegOperand<1>,
|
|
|
|
|
CheckAny<
|
|
|
|
|
[CheckRegOperand<1, WZR>,
|
|
|
|
|
CheckRegOperand<1, XZR>]>,
|
|
|
|
|
CheckZeroOperand<2>]>>>],
|
|
|
|
|
MCReturnStatement<FalsePred>>>;
|
|
|
|
|
def IsZeroIdiomPred : MCSchedPredicate<IsZeroIdiomFn>;
|
