forked from OSchip/llvm-project
53 lines
2.2 KiB
LLVM
53 lines
2.2 KiB
LLVM
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; RUN: llc -march=hexagon -enable-pipeliner < %s
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; REQUIRES: asserts
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; Test that causes an assert when the phi reuse code does not set
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; PhiOp2 correctly for use in the next stage. This occurs when the
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; number of stages is two or more.
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; Function Attrs: nounwind
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define void @f0(i16* noalias nocapture %a0) #0 {
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b0:
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br i1 undef, label %b1, label %b3
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b1: ; preds = %b0
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%v0 = bitcast i16* %a0 to <16 x i32>*
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br label %b2
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b2: ; preds = %b2, %b1
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%v1 = phi i32 [ 0, %b1 ], [ %v15, %b2 ]
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%v2 = phi <16 x i32>* [ %v0, %b1 ], [ %v14, %b2 ]
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%v3 = phi <16 x i32>* [ undef, %b1 ], [ %v6, %b2 ]
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%v4 = phi <16 x i32> [ undef, %b1 ], [ %v10, %b2 ]
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%v5 = phi <16 x i32> [ undef, %b1 ], [ %v4, %b2 ]
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%v6 = getelementptr inbounds <16 x i32>, <16 x i32>* %v3, i32 1
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%v7 = load <16 x i32>, <16 x i32>* %v3, align 64
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%v8 = tail call <16 x i32> @llvm.hexagon.V6.vaddh(<16 x i32> undef, <16 x i32> %v7)
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%v9 = tail call <16 x i32> @llvm.hexagon.V6.valignb(<16 x i32> %v4, <16 x i32> %v5, i32 62)
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%v10 = tail call <16 x i32> @llvm.hexagon.V6.vaddh(<16 x i32> %v8, <16 x i32> undef)
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%v11 = tail call <16 x i32> @llvm.hexagon.V6.valignb(<16 x i32> %v10, <16 x i32> %v4, i32 2)
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%v12 = tail call <16 x i32> @llvm.hexagon.V6.vabsdiffh(<16 x i32> %v9, <16 x i32> %v11)
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%v13 = getelementptr inbounds <16 x i32>, <16 x i32>* %v2, i32 1
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store <16 x i32> %v12, <16 x i32>* %v2, align 64
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%v14 = getelementptr inbounds <16 x i32>, <16 x i32>* %v2, i32 2
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store <16 x i32> zeroinitializer, <16 x i32>* %v13, align 64
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%v15 = add nsw i32 %v1, 1
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%v16 = icmp slt i32 %v15, undef
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br i1 %v16, label %b2, label %b3
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b3: ; preds = %b2, %b0
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ret void
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}
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; Function Attrs: nounwind readnone
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declare <16 x i32> @llvm.hexagon.V6.vaddh(<16 x i32>, <16 x i32>) #1
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; Function Attrs: nounwind readnone
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declare <16 x i32> @llvm.hexagon.V6.valignb(<16 x i32>, <16 x i32>, i32) #1
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; Function Attrs: nounwind readnone
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declare <16 x i32> @llvm.hexagon.V6.vabsdiffh(<16 x i32>, <16 x i32>) #1
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attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvxv60,+hvx-length64b" }
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attributes #1 = { nounwind readnone }
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