[ModuloSchedule] Peel out prologs and epilogs, generate actual code
Summary:
This extends the PeelingModuloScheduleExpander to generate prolog and epilog code,
and correctly stitch uses through the prolog, kernel, epilog DAG.
The key concept in this patch is to ensure that all transforms are *local*; only a
function of a block and its immediate predecessor and successor. By defining the problem in this way
we can inductively rewrite the entire DAG using only local knowledge that is easy to
reason about.
For example, we assume that all prologs and epilogs are near-perfect clones of the
steady-state kernel. This means that if a block has an instruction that is predicated out,
we can redirect all users of that instruction to that equivalent instruction in our
immediate predecessor. As all blocks are clones, every instruction must have an equivalent in
every other block.
Similarly we can make the assumption by construction that if a value defined in a block is used
outside that block, the only possible user is its immediate successors. We maintain this
even for values that are used outside the loop by creating a limited form of LCSSA.
This code isn't small, but it isn't complex.
Enabled a bunch of testing from Hexagon. There are a couple of tests not enabled yet;
I'm about 80% sure there isn't buggy codegen but the tests are checking for patterns
that we don't produce. Those still need a bit more investigation. In the meantime we
(Google) are happy with the code produced by this on our downstream SMS implementation,
and believe it generates correct code.
Subscribers: mgorny, hiraditya, jsji, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D68205
llvm-svn: 373462
2019-10-02 20:46:44 +08:00
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; RUN: llc -march=hexagon < %s -pipeliner-experimental-cg=true | FileCheck %s
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2017-10-11 23:51:44 +08:00
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; Test that the instruction ordering code in the pipeliner fixes up dependences
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; between post-increment register definitions and uses so that the register
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; allocator does not allocate an additional register. The following test case
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; should generate a single packet.
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; CHECK: loop0(.LBB0_[[LOOP:.]],
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; CHECK: .LBB0_[[LOOP]]:
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; CHECK: {
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; CHECK-NOT: {
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; CHECK: :endloop0
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define void @test(i64* nocapture %v1, i64 %v2, i32 %len) local_unnamed_addr #0 {
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entry:
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%cmp7 = icmp sgt i32 %len, 0
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br i1 %cmp7, label %for.body, label %for.end
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for.body:
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%arrayidx.phi = phi i64* [ %arrayidx.inc, %for.body ], [ %v1, %entry ]
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%i.08 = phi i32 [ %inc, %for.body ], [ 0, %entry ]
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%0 = load i64, i64* %arrayidx.phi, align 8
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%1 = tail call i64 @llvm.hexagon.M2.mmpyul.rs1(i64 %0, i64 %v2)
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store i64 %1, i64* %arrayidx.phi, align 8
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%inc = add nuw nsw i32 %i.08, 1
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%exitcond = icmp eq i32 %inc, %len
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%arrayidx.inc = getelementptr i64, i64* %arrayidx.phi, i32 1
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br i1 %exitcond, label %for.end, label %for.body
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for.end:
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ret void
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}
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declare i64 @llvm.hexagon.M2.mmpyul.rs1(i64, i64) #1
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attributes #0 = { nounwind "target-cpu"="hexagonv60" }
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attributes #1 = { nounwind readnone }
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