llvm-project/llvm/test/Transforms/InstCombine/2007-03-21-SignedRangeTest.ll

; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
; RUN: opt < %s -instcombine -S | FileCheck %s

; For PR1248

define i1 @test(i32 %tmp6) {
; CHECK-LABEL: @test(
; CHECK-NEXT:    [[TMP6_OFF:%.*]] = add i32 %tmp6, 83
; CHECK-NEXT:    [[TMP1:%.*]] = icmp ugt i32 [[TMP6_OFF]], 11
; CHECK-NEXT:    ret i1 [[TMP1]]
;
  %tmp7 = sdiv i32 %tmp6, 12
  icmp ne i32 %tmp7, -6
  ret i1 %1
}

define <2 x i1> @test_vec(<2 x i32> %tmp6) {
; CHECK-LABEL: @test_vec(
; CHECK-NEXT:    [[TMP6_OFF:%.*]] = add <2 x i32> %tmp6, <i32 83, i32 83>
; CHECK-NEXT:    [[TMP1:%.*]] = icmp ugt <2 x i32> [[TMP6_OFF]], <i32 11, i32 11>
; CHECK-NEXT:    ret <2 x i1> [[TMP1]]
;
  %tmp7 = sdiv <2 x i32> %tmp6, <i32 12, i32 12>
  icmp ne <2 x i32> %tmp7, <i32 -6, i32 -6>
  ret <2 x i1> %1
}