2018-05-25 23:55:37 +08:00
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//===--------------------- PredicateExpander.cpp --------------------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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/// \file
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/// Functionalities used by the Tablegen backends to expand machine predicates.
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//
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//===----------------------------------------------------------------------===//
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#include "PredicateExpander.h"
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[TableGen][SubtargetEmitter] Add the ability for processor models to describe dependency breaking instructions.
This patch adds the ability for processor models to describe dependency breaking
instructions.
Different processors may specify a different set of dependency-breaking
instructions.
That means, we cannot assume that all processors of the same target would use
the same rules to classify dependency breaking instructions.
The main goal of this patch is to provide the means to describe dependency
breaking instructions directly via tablegen, and have the following
TargetSubtargetInfo hooks redefined in overrides by tabegen'd
XXXGenSubtargetInfo classes (here, XXX is a Target name).
```
virtual bool isZeroIdiom(const MachineInstr *MI, APInt &Mask) const {
return false;
}
virtual bool isDependencyBreaking(const MachineInstr *MI, APInt &Mask) const {
return isZeroIdiom(MI);
}
```
An instruction MI is a dependency-breaking instruction if a call to method
isDependencyBreaking(MI) on the STI (TargetSubtargetInfo object) evaluates to
true. Similarly, an instruction MI is a special case of zero-idiom dependency
breaking instruction if a call to STI.isZeroIdiom(MI) returns true.
The extra APInt is used for those targets that may want to select which machine
operands have their dependency broken (see comments in code).
Note that by default, subtargets don't know about the existence of
dependency-breaking. In the absence of external information, those method calls
would always return false.
A new tablegen class named STIPredicate has been added by this patch to let
processor models classify instructions that have properties in common. The idea
is that, a MCInstrPredicate definition can be used to "generate" an instruction
equivalence class, with the idea that instructions of a same class all have a
property in common.
STIPredicate definitions are essentially a collection of instruction equivalence
classes.
Also, different processor models can specify a different variant of the same
STIPredicate with different rules (i.e. predicates) to classify instructions.
Tablegen backends (in this particular case, the SubtargetEmitter) will be able
to process STIPredicate definitions, and automatically generate functions in
XXXGenSubtargetInfo.
This patch introduces two special kind of STIPredicate classes named
IsZeroIdiomFunction and IsDepBreakingFunction in tablegen. It also adds a
definition for those in the BtVer2 scheduling model only.
This patch supersedes the one committed at r338372 (phabricator review: D49310).
The main advantages are:
- We can describe subtarget predicates via tablegen using STIPredicates.
- We can describe zero-idioms / dep-breaking instructions directly via
tablegen in the scheduling models.
In future, the STIPredicates framework can be used for solving other problems.
Examples of future developments are:
- Teach how to identify optimizable register-register moves
- Teach how to identify slow LEA instructions (each subtarget defining its own
concept of "slow" LEA).
- Teach how to identify instructions that have undocumented false dependencies
on the output registers on some processors only.
It is also (in my opinion) an elegant way to expose knowledge to both external
tools like llvm-mca, and codegen passes.
For example, machine schedulers in LLVM could reuse that information when
internally constructing the data dependency graph for a code region.
This new design feature is also an "opt-in" feature. Processor models don't have
to use the new STIPredicates. It has all been designed to be as unintrusive as
possible.
Differential Revision: https://reviews.llvm.org/D52174
llvm-svn: 342555
2018-09-19 23:57:45 +08:00
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#include "CodeGenSchedule.h" // Definition of STIPredicateFunction.
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2018-05-25 23:55:37 +08:00
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namespace llvm {
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2018-08-13 23:13:35 +08:00
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void PredicateExpander::expandTrue(raw_ostream &OS) { OS << "true"; }
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void PredicateExpander::expandFalse(raw_ostream &OS) { OS << "false"; }
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2018-05-25 23:55:37 +08:00
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2018-08-13 23:13:35 +08:00
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void PredicateExpander::expandCheckImmOperand(raw_ostream &OS, int OpIndex,
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int ImmVal) {
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2018-07-18 00:11:37 +08:00
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OS << "MI" << (isByRef() ? "." : "->") << "getOperand(" << OpIndex
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<< ").getImm() " << (shouldNegate() ? "!= " : "== ") << ImmVal;
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2018-05-25 23:55:37 +08:00
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}
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2018-08-13 23:13:35 +08:00
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void PredicateExpander::expandCheckImmOperand(raw_ostream &OS, int OpIndex,
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StringRef ImmVal) {
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2018-07-18 00:11:37 +08:00
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OS << "MI" << (isByRef() ? "." : "->") << "getOperand(" << OpIndex
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<< ").getImm() " << (shouldNegate() ? "!= " : "== ") << ImmVal;
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2018-05-25 23:55:37 +08:00
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}
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2018-08-13 23:13:35 +08:00
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void PredicateExpander::expandCheckRegOperand(raw_ostream &OS, int OpIndex,
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const Record *Reg) {
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2018-05-25 23:55:37 +08:00
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assert(Reg->isSubClassOf("Register") && "Expected a register Record!");
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OS << "MI" << (isByRef() ? "." : "->") << "getOperand(" << OpIndex
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<< ").getReg() " << (shouldNegate() ? "!= " : "== ");
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const StringRef Str = Reg->getValueAsString("Namespace");
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if (!Str.empty())
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OS << Str << "::";
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OS << Reg->getName();
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}
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2018-08-13 23:13:35 +08:00
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void PredicateExpander::expandCheckInvalidRegOperand(raw_ostream &OS,
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2018-07-18 19:03:22 +08:00
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int OpIndex) {
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OS << "MI" << (isByRef() ? "." : "->") << "getOperand(" << OpIndex
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<< ").getReg() " << (shouldNegate() ? "!= " : "== ") << "0";
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}
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2018-08-13 23:13:35 +08:00
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void PredicateExpander::expandCheckSameRegOperand(raw_ostream &OS, int First,
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int Second) {
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2018-05-25 23:55:37 +08:00
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OS << "MI" << (isByRef() ? "." : "->") << "getOperand(" << First
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<< ").getReg() " << (shouldNegate() ? "!=" : "==") << " MI"
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<< (isByRef() ? "." : "->") << "getOperand(" << Second << ").getReg()";
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}
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2018-08-13 23:13:35 +08:00
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void PredicateExpander::expandCheckNumOperands(raw_ostream &OS, int NumOps) {
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2018-05-25 23:55:37 +08:00
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OS << "MI" << (isByRef() ? "." : "->") << "getNumOperands() "
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<< (shouldNegate() ? "!= " : "== ") << NumOps;
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}
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2018-08-13 23:13:35 +08:00
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void PredicateExpander::expandCheckOpcode(raw_ostream &OS, const Record *Inst) {
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2018-05-25 23:55:37 +08:00
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OS << "MI" << (isByRef() ? "." : "->") << "getOpcode() "
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<< (shouldNegate() ? "!= " : "== ") << Inst->getValueAsString("Namespace")
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<< "::" << Inst->getName();
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}
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2018-08-13 23:13:35 +08:00
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void PredicateExpander::expandCheckOpcode(raw_ostream &OS,
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2018-05-25 23:55:37 +08:00
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const RecVec &Opcodes) {
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assert(!Opcodes.empty() && "Expected at least one opcode to check!");
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bool First = true;
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if (Opcodes.size() == 1) {
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OS << "( ";
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expandCheckOpcode(OS, Opcodes[0]);
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OS << " )";
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return;
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}
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OS << '(';
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increaseIndentLevel();
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for (const Record *Rec : Opcodes) {
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OS << '\n';
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2018-08-13 23:13:35 +08:00
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OS.indent(getIndentLevel() * 2);
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2018-05-25 23:55:37 +08:00
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if (!First)
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OS << (shouldNegate() ? "&& " : "|| ");
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expandCheckOpcode(OS, Rec);
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First = false;
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}
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OS << '\n';
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decreaseIndentLevel();
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2018-08-13 23:13:35 +08:00
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OS.indent(getIndentLevel() * 2);
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2018-05-25 23:55:37 +08:00
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OS << ')';
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}
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2018-08-13 23:13:35 +08:00
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void PredicateExpander::expandCheckPseudo(raw_ostream &OS,
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2018-05-25 23:55:37 +08:00
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const RecVec &Opcodes) {
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if (shouldExpandForMC())
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expandFalse(OS);
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else
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expandCheckOpcode(OS, Opcodes);
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}
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2018-08-13 23:13:35 +08:00
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void PredicateExpander::expandPredicateSequence(raw_ostream &OS,
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2018-05-25 23:55:37 +08:00
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const RecVec &Sequence,
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bool IsCheckAll) {
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assert(!Sequence.empty() && "Found an invalid empty predicate set!");
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if (Sequence.size() == 1)
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return expandPredicate(OS, Sequence[0]);
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// Okay, there is more than one predicate in the set.
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bool First = true;
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OS << (shouldNegate() ? "!(" : "(");
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increaseIndentLevel();
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bool OldValue = shouldNegate();
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setNegatePredicate(false);
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for (const Record *Rec : Sequence) {
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OS << '\n';
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2018-08-13 23:13:35 +08:00
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OS.indent(getIndentLevel() * 2);
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2018-05-25 23:55:37 +08:00
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if (!First)
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OS << (IsCheckAll ? "&& " : "|| ");
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expandPredicate(OS, Rec);
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First = false;
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}
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OS << '\n';
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decreaseIndentLevel();
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2018-08-13 23:13:35 +08:00
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OS.indent(getIndentLevel() * 2);
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2018-05-25 23:55:37 +08:00
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OS << ')';
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setNegatePredicate(OldValue);
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}
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2018-08-13 23:13:35 +08:00
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void PredicateExpander::expandTIIFunctionCall(raw_ostream &OS,
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2018-05-25 23:55:37 +08:00
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StringRef MethodName) {
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OS << (shouldNegate() ? "!" : "");
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2018-08-15 02:36:54 +08:00
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OS << TargetName << (shouldExpandForMC() ? "_MC::" : "GenInstrInfo::");
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2018-05-25 23:55:37 +08:00
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OS << MethodName << (isByRef() ? "(MI)" : "(*MI)");
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}
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2018-08-13 23:13:35 +08:00
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void PredicateExpander::expandCheckIsRegOperand(raw_ostream &OS, int OpIndex) {
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2018-05-25 23:55:37 +08:00
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OS << (shouldNegate() ? "!" : "") << "MI" << (isByRef() ? "." : "->")
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<< "getOperand(" << OpIndex << ").isReg() ";
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}
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2018-08-13 23:13:35 +08:00
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void PredicateExpander::expandCheckIsImmOperand(raw_ostream &OS, int OpIndex) {
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2018-05-25 23:55:37 +08:00
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OS << (shouldNegate() ? "!" : "") << "MI" << (isByRef() ? "." : "->")
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<< "getOperand(" << OpIndex << ").isImm() ";
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}
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2018-08-13 23:13:35 +08:00
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void PredicateExpander::expandCheckFunctionPredicate(raw_ostream &OS,
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2018-05-25 23:55:37 +08:00
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StringRef MCInstFn,
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StringRef MachineInstrFn) {
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OS << (shouldExpandForMC() ? MCInstFn : MachineInstrFn)
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<< (isByRef() ? "(MI)" : "(*MI)");
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}
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2018-08-13 23:13:35 +08:00
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void PredicateExpander::expandCheckNonPortable(raw_ostream &OS,
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2018-05-25 23:55:37 +08:00
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StringRef Code) {
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if (shouldExpandForMC())
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return expandFalse(OS);
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OS << '(' << Code << ')';
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}
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2018-08-13 23:13:35 +08:00
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void PredicateExpander::expandReturnStatement(raw_ostream &OS,
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2018-08-09 23:32:48 +08:00
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const Record *Rec) {
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2018-08-13 23:13:35 +08:00
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std::string Buffer;
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raw_string_ostream SS(Buffer);
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SS << "return ";
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expandPredicate(SS, Rec);
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SS << ";";
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SS.flush();
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OS << Buffer;
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2018-08-09 23:32:48 +08:00
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}
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2018-08-13 23:13:35 +08:00
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void PredicateExpander::expandOpcodeSwitchCase(raw_ostream &OS,
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2018-08-09 23:32:48 +08:00
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const Record *Rec) {
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const RecVec &Opcodes = Rec->getValueAsListOfDefs("Opcodes");
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for (const Record *Opcode : Opcodes) {
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2018-08-13 23:13:35 +08:00
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OS.indent(getIndentLevel() * 2);
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2018-08-09 23:32:48 +08:00
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OS << "case " << Opcode->getValueAsString("Namespace")
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<< "::" << Opcode->getName() << " :\n";
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}
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increaseIndentLevel();
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2018-08-13 23:13:35 +08:00
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OS.indent(getIndentLevel() * 2);
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2018-08-09 23:32:48 +08:00
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expandStatement(OS, Rec->getValueAsDef("CaseStmt"));
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decreaseIndentLevel();
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}
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2018-08-13 23:13:35 +08:00
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void PredicateExpander::expandOpcodeSwitchStatement(raw_ostream &OS,
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2018-08-09 23:32:48 +08:00
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const RecVec &Cases,
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const Record *Default) {
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2018-08-13 23:13:35 +08:00
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std::string Buffer;
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raw_string_ostream SS(Buffer);
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2018-08-09 23:32:48 +08:00
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2018-08-13 23:13:35 +08:00
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SS << "switch(MI" << (isByRef() ? "." : "->") << "getOpcode()) {\n";
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2018-08-09 23:32:48 +08:00
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for (const Record *Rec : Cases) {
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2018-08-13 23:13:35 +08:00
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expandOpcodeSwitchCase(SS, Rec);
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SS << '\n';
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2018-08-09 23:32:48 +08:00
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}
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// Expand the default case.
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2018-08-13 23:13:35 +08:00
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SS.indent(getIndentLevel() * 2);
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SS << "default :\n";
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2018-08-09 23:32:48 +08:00
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increaseIndentLevel();
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2018-08-13 23:13:35 +08:00
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SS.indent(getIndentLevel() * 2);
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expandStatement(SS, Default);
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2018-08-09 23:32:48 +08:00
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decreaseIndentLevel();
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2018-08-13 23:13:35 +08:00
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SS << '\n';
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2018-08-09 23:32:48 +08:00
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2018-08-13 23:13:35 +08:00
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SS.indent(getIndentLevel() * 2);
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SS << "} // end of switch-stmt";
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SS.flush();
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OS << Buffer;
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2018-08-09 23:32:48 +08:00
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}
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2018-08-13 23:13:35 +08:00
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void PredicateExpander::expandStatement(raw_ostream &OS, const Record *Rec) {
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// Assume that padding has been added by the caller.
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2018-08-09 23:32:48 +08:00
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if (Rec->isSubClassOf("MCOpcodeSwitchStatement")) {
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expandOpcodeSwitchStatement(OS, Rec->getValueAsListOfDefs("Cases"),
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Rec->getValueAsDef("DefaultCase"));
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return;
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}
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if (Rec->isSubClassOf("MCReturnStatement")) {
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expandReturnStatement(OS, Rec->getValueAsDef("Pred"));
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return;
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}
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llvm_unreachable("No known rules to expand this MCStatement");
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}
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2018-08-13 23:13:35 +08:00
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void PredicateExpander::expandPredicate(raw_ostream &OS, const Record *Rec) {
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// Assume that padding has been added by the caller.
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2018-05-25 23:55:37 +08:00
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if (Rec->isSubClassOf("MCTrue")) {
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if (shouldNegate())
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return expandFalse(OS);
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return expandTrue(OS);
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}
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if (Rec->isSubClassOf("MCFalse")) {
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if (shouldNegate())
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return expandTrue(OS);
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return expandFalse(OS);
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}
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if (Rec->isSubClassOf("CheckNot")) {
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flipNegatePredicate();
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expandPredicate(OS, Rec->getValueAsDef("Pred"));
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flipNegatePredicate();
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return;
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}
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if (Rec->isSubClassOf("CheckIsRegOperand"))
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return expandCheckIsRegOperand(OS, Rec->getValueAsInt("OpIndex"));
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if (Rec->isSubClassOf("CheckIsImmOperand"))
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return expandCheckIsImmOperand(OS, Rec->getValueAsInt("OpIndex"));
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if (Rec->isSubClassOf("CheckRegOperand"))
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return expandCheckRegOperand(OS, Rec->getValueAsInt("OpIndex"),
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Rec->getValueAsDef("Reg"));
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2018-07-18 19:03:22 +08:00
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if (Rec->isSubClassOf("CheckInvalidRegOperand"))
|
|
|
|
return expandCheckInvalidRegOperand(OS, Rec->getValueAsInt("OpIndex"));
|
|
|
|
|
2018-05-25 23:55:37 +08:00
|
|
|
if (Rec->isSubClassOf("CheckImmOperand"))
|
|
|
|
return expandCheckImmOperand(OS, Rec->getValueAsInt("OpIndex"),
|
|
|
|
Rec->getValueAsInt("ImmVal"));
|
|
|
|
|
|
|
|
if (Rec->isSubClassOf("CheckImmOperand_s"))
|
|
|
|
return expandCheckImmOperand(OS, Rec->getValueAsInt("OpIndex"),
|
|
|
|
Rec->getValueAsString("ImmVal"));
|
|
|
|
|
|
|
|
if (Rec->isSubClassOf("CheckSameRegOperand"))
|
|
|
|
return expandCheckSameRegOperand(OS, Rec->getValueAsInt("FirstIndex"),
|
|
|
|
Rec->getValueAsInt("SecondIndex"));
|
|
|
|
|
|
|
|
if (Rec->isSubClassOf("CheckNumOperands"))
|
|
|
|
return expandCheckNumOperands(OS, Rec->getValueAsInt("NumOps"));
|
|
|
|
|
|
|
|
if (Rec->isSubClassOf("CheckPseudo"))
|
|
|
|
return expandCheckPseudo(OS, Rec->getValueAsListOfDefs("ValidOpcodes"));
|
|
|
|
|
|
|
|
if (Rec->isSubClassOf("CheckOpcode"))
|
|
|
|
return expandCheckOpcode(OS, Rec->getValueAsListOfDefs("ValidOpcodes"));
|
|
|
|
|
|
|
|
if (Rec->isSubClassOf("CheckAll"))
|
|
|
|
return expandPredicateSequence(OS, Rec->getValueAsListOfDefs("Predicates"),
|
|
|
|
/* AllOf */ true);
|
|
|
|
|
|
|
|
if (Rec->isSubClassOf("CheckAny"))
|
|
|
|
return expandPredicateSequence(OS, Rec->getValueAsListOfDefs("Predicates"),
|
|
|
|
/* AllOf */ false);
|
|
|
|
|
|
|
|
if (Rec->isSubClassOf("CheckFunctionPredicate"))
|
|
|
|
return expandCheckFunctionPredicate(
|
|
|
|
OS, Rec->getValueAsString("MCInstFnName"),
|
|
|
|
Rec->getValueAsString("MachineInstrFnName"));
|
|
|
|
|
|
|
|
if (Rec->isSubClassOf("CheckNonPortable"))
|
|
|
|
return expandCheckNonPortable(OS, Rec->getValueAsString("CodeBlock"));
|
|
|
|
|
|
|
|
if (Rec->isSubClassOf("TIIPredicate"))
|
2018-08-15 02:36:54 +08:00
|
|
|
return expandTIIFunctionCall(OS, Rec->getValueAsString("FunctionName"));
|
2018-05-25 23:55:37 +08:00
|
|
|
|
|
|
|
llvm_unreachable("No known rules to expand this MCInstPredicate");
|
|
|
|
}
|
|
|
|
|
[TableGen][SubtargetEmitter] Add the ability for processor models to describe dependency breaking instructions.
This patch adds the ability for processor models to describe dependency breaking
instructions.
Different processors may specify a different set of dependency-breaking
instructions.
That means, we cannot assume that all processors of the same target would use
the same rules to classify dependency breaking instructions.
The main goal of this patch is to provide the means to describe dependency
breaking instructions directly via tablegen, and have the following
TargetSubtargetInfo hooks redefined in overrides by tabegen'd
XXXGenSubtargetInfo classes (here, XXX is a Target name).
```
virtual bool isZeroIdiom(const MachineInstr *MI, APInt &Mask) const {
return false;
}
virtual bool isDependencyBreaking(const MachineInstr *MI, APInt &Mask) const {
return isZeroIdiom(MI);
}
```
An instruction MI is a dependency-breaking instruction if a call to method
isDependencyBreaking(MI) on the STI (TargetSubtargetInfo object) evaluates to
true. Similarly, an instruction MI is a special case of zero-idiom dependency
breaking instruction if a call to STI.isZeroIdiom(MI) returns true.
The extra APInt is used for those targets that may want to select which machine
operands have their dependency broken (see comments in code).
Note that by default, subtargets don't know about the existence of
dependency-breaking. In the absence of external information, those method calls
would always return false.
A new tablegen class named STIPredicate has been added by this patch to let
processor models classify instructions that have properties in common. The idea
is that, a MCInstrPredicate definition can be used to "generate" an instruction
equivalence class, with the idea that instructions of a same class all have a
property in common.
STIPredicate definitions are essentially a collection of instruction equivalence
classes.
Also, different processor models can specify a different variant of the same
STIPredicate with different rules (i.e. predicates) to classify instructions.
Tablegen backends (in this particular case, the SubtargetEmitter) will be able
to process STIPredicate definitions, and automatically generate functions in
XXXGenSubtargetInfo.
This patch introduces two special kind of STIPredicate classes named
IsZeroIdiomFunction and IsDepBreakingFunction in tablegen. It also adds a
definition for those in the BtVer2 scheduling model only.
This patch supersedes the one committed at r338372 (phabricator review: D49310).
The main advantages are:
- We can describe subtarget predicates via tablegen using STIPredicates.
- We can describe zero-idioms / dep-breaking instructions directly via
tablegen in the scheduling models.
In future, the STIPredicates framework can be used for solving other problems.
Examples of future developments are:
- Teach how to identify optimizable register-register moves
- Teach how to identify slow LEA instructions (each subtarget defining its own
concept of "slow" LEA).
- Teach how to identify instructions that have undocumented false dependencies
on the output registers on some processors only.
It is also (in my opinion) an elegant way to expose knowledge to both external
tools like llvm-mca, and codegen passes.
For example, machine schedulers in LLVM could reuse that information when
internally constructing the data dependency graph for a code region.
This new design feature is also an "opt-in" feature. Processor models don't have
to use the new STIPredicates. It has all been designed to be as unintrusive as
possible.
Differential Revision: https://reviews.llvm.org/D52174
llvm-svn: 342555
2018-09-19 23:57:45 +08:00
|
|
|
void STIPredicateExpander::expandHeader(raw_ostream &OS,
|
|
|
|
const STIPredicateFunction &Fn) {
|
|
|
|
const Record *Rec = Fn.getDeclaration();
|
|
|
|
StringRef FunctionName = Rec->getValueAsString("Name");
|
|
|
|
|
|
|
|
OS.indent(getIndentLevel() * 2);
|
|
|
|
OS << "bool ";
|
|
|
|
if (shouldExpandDefinition())
|
|
|
|
OS << getClassPrefix() << "::";
|
|
|
|
OS << FunctionName << "(";
|
|
|
|
if (shouldExpandForMC())
|
|
|
|
OS << "const MCInst " << (isByRef() ? "&" : "*") << "MI";
|
|
|
|
else
|
|
|
|
OS << "const MachineInstr " << (isByRef() ? "&" : "*") << "MI";
|
|
|
|
if (Rec->getValueAsBit("UpdatesOpcodeMask"))
|
|
|
|
OS << ", APInt &Mask";
|
|
|
|
OS << (shouldExpandForMC() ? ", unsigned ProcessorID) const " : ") const ");
|
|
|
|
if (shouldExpandDefinition()) {
|
|
|
|
OS << "{\n";
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (Rec->getValueAsBit("OverridesBaseClassMember"))
|
|
|
|
OS << "override";
|
|
|
|
OS << ";\n";
|
|
|
|
}
|
|
|
|
|
|
|
|
void STIPredicateExpander::expandPrologue(raw_ostream &OS,
|
|
|
|
const STIPredicateFunction &Fn) {
|
|
|
|
RecVec Delegates = Fn.getDeclaration()->getValueAsListOfDefs("Delegates");
|
|
|
|
bool UpdatesOpcodeMask =
|
|
|
|
Fn.getDeclaration()->getValueAsBit("UpdatesOpcodeMask");
|
|
|
|
|
|
|
|
increaseIndentLevel();
|
|
|
|
unsigned IndentLevel = getIndentLevel();
|
|
|
|
for (const Record *Delegate : Delegates) {
|
|
|
|
OS.indent(IndentLevel * 2);
|
|
|
|
OS << "if (" << Delegate->getValueAsString("Name") << "(MI";
|
|
|
|
if (UpdatesOpcodeMask)
|
|
|
|
OS << ", Mask";
|
|
|
|
if (shouldExpandForMC())
|
|
|
|
OS << ", ProcessorID";
|
|
|
|
OS << "))\n";
|
|
|
|
OS.indent((1 + IndentLevel) * 2);
|
|
|
|
OS << "return true;\n\n";
|
|
|
|
}
|
|
|
|
|
|
|
|
if (shouldExpandForMC())
|
|
|
|
return;
|
|
|
|
|
|
|
|
OS.indent(IndentLevel * 2);
|
|
|
|
OS << "unsigned ProcessorID = getSchedModel().getProcessorID();\n";
|
|
|
|
}
|
|
|
|
|
|
|
|
void STIPredicateExpander::expandOpcodeGroup(raw_ostream &OS, const OpcodeGroup &Group,
|
|
|
|
bool ShouldUpdateOpcodeMask) {
|
|
|
|
const OpcodeInfo &OI = Group.getOpcodeInfo();
|
|
|
|
for (const PredicateInfo &PI : OI.getPredicates()) {
|
|
|
|
const APInt &ProcModelMask = PI.ProcModelMask;
|
|
|
|
bool FirstProcID = true;
|
|
|
|
for (unsigned I = 0, E = ProcModelMask.getActiveBits(); I < E; ++I) {
|
|
|
|
if (!ProcModelMask[I])
|
|
|
|
continue;
|
|
|
|
|
|
|
|
if (FirstProcID) {
|
|
|
|
OS.indent(getIndentLevel() * 2);
|
|
|
|
OS << "if (ProcessorID == " << I;
|
|
|
|
} else {
|
|
|
|
OS << " || ProcessorID == " << I;
|
|
|
|
}
|
|
|
|
FirstProcID = false;
|
|
|
|
}
|
|
|
|
|
|
|
|
OS << ") {\n";
|
|
|
|
|
|
|
|
increaseIndentLevel();
|
|
|
|
OS.indent(getIndentLevel() * 2);
|
|
|
|
if (ShouldUpdateOpcodeMask) {
|
|
|
|
if (PI.OperandMask.isNullValue())
|
|
|
|
OS << "Mask.clearAllBits();\n";
|
|
|
|
else
|
|
|
|
OS << "Mask = " << PI.OperandMask << ";\n";
|
|
|
|
OS.indent(getIndentLevel() * 2);
|
|
|
|
}
|
|
|
|
OS << "return ";
|
|
|
|
expandPredicate(OS, PI.Predicate);
|
|
|
|
OS << ";\n";
|
|
|
|
decreaseIndentLevel();
|
|
|
|
OS.indent(getIndentLevel() * 2);
|
|
|
|
OS << "}\n";
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
void STIPredicateExpander::expandBody(raw_ostream &OS,
|
|
|
|
const STIPredicateFunction &Fn) {
|
|
|
|
bool UpdatesOpcodeMask =
|
|
|
|
Fn.getDeclaration()->getValueAsBit("UpdatesOpcodeMask");
|
|
|
|
|
|
|
|
unsigned IndentLevel = getIndentLevel();
|
|
|
|
OS.indent(IndentLevel * 2);
|
|
|
|
OS << "switch(MI" << (isByRef() ? "." : "->") << "getOpcode()) {\n";
|
|
|
|
OS.indent(IndentLevel * 2);
|
|
|
|
OS << "default:\n";
|
|
|
|
OS.indent(IndentLevel * 2);
|
|
|
|
OS << " break;";
|
|
|
|
|
|
|
|
for (const OpcodeGroup &Group : Fn.getGroups()) {
|
|
|
|
for (const Record *Opcode : Group.getOpcodes()) {
|
|
|
|
OS << '\n';
|
|
|
|
OS.indent(IndentLevel * 2);
|
|
|
|
OS << "case " << getTargetName() << "::" << Opcode->getName() << ":";
|
|
|
|
}
|
|
|
|
|
|
|
|
OS << '\n';
|
|
|
|
increaseIndentLevel();
|
|
|
|
expandOpcodeGroup(OS, Group, UpdatesOpcodeMask);
|
|
|
|
|
|
|
|
OS.indent(getIndentLevel() * 2);
|
|
|
|
OS << "break;\n";
|
|
|
|
decreaseIndentLevel();
|
|
|
|
}
|
|
|
|
|
|
|
|
OS.indent(IndentLevel * 2);
|
|
|
|
OS << "}\n";
|
|
|
|
}
|
|
|
|
|
|
|
|
void STIPredicateExpander::expandEpilogue(raw_ostream &OS,
|
|
|
|
const STIPredicateFunction &Fn) {
|
|
|
|
OS << '\n';
|
|
|
|
OS.indent(getIndentLevel() * 2);
|
|
|
|
OS << "return ";
|
|
|
|
expandPredicate(OS, Fn.getDefaultReturnPredicate());
|
|
|
|
OS << ";\n";
|
|
|
|
|
|
|
|
decreaseIndentLevel();
|
|
|
|
OS.indent(getIndentLevel() * 2);
|
|
|
|
StringRef FunctionName = Fn.getDeclaration()->getValueAsString("Name");
|
|
|
|
OS << "} // " << ClassPrefix << "::" << FunctionName << "\n\n";
|
|
|
|
}
|
|
|
|
|
|
|
|
void STIPredicateExpander::expandSTIPredicate(raw_ostream &OS,
|
|
|
|
const STIPredicateFunction &Fn) {
|
|
|
|
const Record *Rec = Fn.getDeclaration();
|
|
|
|
if (shouldExpandForMC() && !Rec->getValueAsBit("ExpandForMC"))
|
|
|
|
return;
|
|
|
|
|
|
|
|
expandHeader(OS, Fn);
|
|
|
|
if (shouldExpandDefinition()) {
|
|
|
|
expandPrologue(OS, Fn);
|
|
|
|
expandBody(OS, Fn);
|
|
|
|
expandEpilogue(OS, Fn);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2018-05-25 23:55:37 +08:00
|
|
|
} // namespace llvm
|