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llvm-project/llvm/test/CodeGen/SPARC/64cond.ll

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Sparc: Perform leaf procedure optimization by default llvm-svn: 183083
2013-06-02 10:24:27 +08:00
; RUN: llc < %s -mtriple=sparc64-pc-openbsd -disable-sparc-leaf-proc | FileCheck %s
Recognize sparc64 as an alias for sparcv9 triples. Patch by Brad Smith! llvm-svn: 181808
2013-05-15 01:47:27 +08:00
; Testing 64-bit conditionals. The sparc64 triple is an alias for sparcv9.
Add 64-bit compare + branch for SPARC v9. The same compare instruction is used for 32-bit and 64-bit compares. It sets two different sets of flags: icc and xcc. This patch adds a conditional branch instruction using the xcc flags for 64-bit compares. llvm-svn: 178621
2013-04-03 12:41:44 +08:00
; CHECK: cmpri
[Sparc]: Use cmp instruction instead of subcc to compare integers. llvm-svn: 183463
2013-06-07 08:03:36 +08:00
; CHECK: cmp %i1, 1
Fix a typo in asm string of BP* family of instructions. With this fix I am able to compile/assemble/link/run /bin/echo from FreeBSD. llvm-svn: 183537
2013-06-08 01:46:57 +08:00
; CHECK: be %xcc,
Add 64-bit compare + branch for SPARC v9. The same compare instruction is used for 32-bit and 64-bit compares. It sets two different sets of flags: icc and xcc. This patch adds a conditional branch instruction using the xcc flags for 64-bit compares. llvm-svn: 178621
2013-04-03 12:41:44 +08:00
define void @cmpri(i64* %p, i64 %x) {
entry:
%tobool = icmp eq i64 %x, 1
br i1 %tobool, label %if.end, label %if.then
if.then:
store i64 %x, i64* %p, align 8
br label %if.end
if.end:
ret void
}
; CHECK: cmprr
[Sparc]: Use cmp instruction instead of subcc to compare integers. llvm-svn: 183463
2013-06-07 08:03:36 +08:00
; CHECK: cmp %i1, %i2
Fix a typo in asm string of BP* family of instructions. With this fix I am able to compile/assemble/link/run /bin/echo from FreeBSD. llvm-svn: 183537
2013-06-08 01:46:57 +08:00
; CHECK: bgu %xcc,
Add 64-bit compare + branch for SPARC v9. The same compare instruction is used for 32-bit and 64-bit compares. It sets two different sets of flags: icc and xcc. This patch adds a conditional branch instruction using the xcc flags for 64-bit compares. llvm-svn: 178621
2013-04-03 12:41:44 +08:00
define void @cmprr(i64* %p, i64 %x, i64 %y) {
entry:
%tobool = icmp ugt i64 %x, %y
br i1 %tobool, label %if.end, label %if.then
if.then:
store i64 %x, i64* %p, align 8
br label %if.end
if.end:
ret void
}
Add SPARC v9 support for select on 64-bit compares. This requires v9 cmov instructions using the %xcc flags instead of the %icc flags. Still missing: - Select floats on %xcc flags. - Select i64 on %fcc flags. llvm-svn: 178737
2013-04-04 11:08:00 +08:00
; CHECK: selecti32_xcc
[Sparc]: Use cmp instruction instead of subcc to compare integers. llvm-svn: 183463
2013-06-07 08:03:36 +08:00
; CHECK: cmp %i0, %i1
Add SPARC v9 support for select on 64-bit compares. This requires v9 cmov instructions using the %xcc flags instead of the %icc flags. Still missing: - Select floats on %xcc flags. - Select i64 on %fcc flags. llvm-svn: 178737
2013-04-04 11:08:00 +08:00
; CHECK: movg %xcc, %i2, %i3
Sparc: Combine add/or/sethi instruction with restore if possible. llvm-svn: 183088
2013-06-03 05:48:17 +08:00
; CHECK: restore %g0, %i3, %o0
Add SPARC v9 support for select on 64-bit compares. This requires v9 cmov instructions using the %xcc flags instead of the %icc flags. Still missing: - Select floats on %xcc flags. - Select i64 on %fcc flags. llvm-svn: 178737
2013-04-04 11:08:00 +08:00
define i32 @selecti32_xcc(i64 %x, i64 %y, i32 %a, i32 %b) {
entry:
%tobool = icmp sgt i64 %x, %y
%rv = select i1 %tobool, i32 %a, i32 %b
ret i32 %rv
}
; CHECK: selecti64_xcc
[Sparc]: Use cmp instruction instead of subcc to compare integers. llvm-svn: 183463
2013-06-07 08:03:36 +08:00
; CHECK: cmp %i0, %i1
Add SPARC v9 support for select on 64-bit compares. This requires v9 cmov instructions using the %xcc flags instead of the %icc flags. Still missing: - Select floats on %xcc flags. - Select i64 on %fcc flags. llvm-svn: 178737
2013-04-04 11:08:00 +08:00
; CHECK: movg %xcc, %i2, %i3
Sparc: Combine add/or/sethi instruction with restore if possible. llvm-svn: 183088
2013-06-03 05:48:17 +08:00
; CHECK: restore %g0, %i3, %o0
Add SPARC v9 support for select on 64-bit compares. This requires v9 cmov instructions using the %xcc flags instead of the %icc flags. Still missing: - Select floats on %xcc flags. - Select i64 on %fcc flags. llvm-svn: 178737
2013-04-04 11:08:00 +08:00
define i64 @selecti64_xcc(i64 %x, i64 %y, i64 %a, i64 %b) {
entry:
%tobool = icmp sgt i64 %x, %y
%rv = select i1 %tobool, i64 %a, i64 %b
ret i64 %rv
}
Implement SPselectfcc for i64 operands. Also clean up the arguments to all the MOVCC instructions so the operands always are (true-val, false-val, cond-code). llvm-svn: 182221
2013-05-20 04:20:54 +08:00
Select i64 values with %icc conditions. llvm-svn: 182224
2013-05-20 04:38:21 +08:00
; CHECK: selecti64_icc
[Sparc]: Use cmp instruction instead of subcc to compare integers. llvm-svn: 183463
2013-06-07 08:03:36 +08:00
; CHECK: cmp %i0, %i1
Select i64 values with %icc conditions. llvm-svn: 182224
2013-05-20 04:38:21 +08:00
; CHECK: movg %icc, %i2, %i3
Sparc: Combine add/or/sethi instruction with restore if possible. llvm-svn: 183088
2013-06-03 05:48:17 +08:00
; CHECK: restore %g0, %i3, %o0
Select i64 values with %icc conditions. llvm-svn: 182224
2013-05-20 04:38:21 +08:00
define i64 @selecti64_icc(i32 %x, i32 %y, i64 %a, i64 %b) {
entry:
%tobool = icmp sgt i32 %x, %y
%rv = select i1 %tobool, i64 %a, i64 %b
ret i64 %rv
}
Implement SPselectfcc for i64 operands. Also clean up the arguments to all the MOVCC instructions so the operands always are (true-val, false-val, cond-code). llvm-svn: 182221
2013-05-20 04:20:54 +08:00
; CHECK: selecti64_fcc
[Sparc] Return true in enableMultipleCopyHints(). Enable multiple COPY hints to eliminate more COPYs during register allocation. Note that this is something all targets should do, see https://reviews.llvm.org/D38128. Review: James Y Knight llvm-svn: 326028
2018-02-24 16:24:31 +08:00
; CHECK: mov %i3, %i0
Implement SPselectfcc for i64 operands. Also clean up the arguments to all the MOVCC instructions so the operands always are (true-val, false-val, cond-code). llvm-svn: 182221
2013-05-20 04:20:54 +08:00
; CHECK: fcmps %f1, %f3
[Sparc] Return true in enableMultipleCopyHints(). Enable multiple COPY hints to eliminate more COPYs during register allocation. Note that this is something all targets should do, see https://reviews.llvm.org/D38128. Review: James Y Knight llvm-svn: 326028
2018-02-24 16:24:31 +08:00
; CHECK: movul %fcc0, %i2, %i0
; CHECK: restore
Implement SPselectfcc for i64 operands. Also clean up the arguments to all the MOVCC instructions so the operands always are (true-val, false-val, cond-code). llvm-svn: 182221
2013-05-20 04:20:54 +08:00
define i64 @selecti64_fcc(float %x, float %y, i64 %a, i64 %b) {
entry:
%tobool = fcmp ult float %x, %y
%rv = select i1 %tobool, i64 %a, i64 %b
ret i64 %rv
}
Add floating point selects on %xcc predicates. llvm-svn: 182222
2013-05-20 04:33:11 +08:00
; CHECK: selectf32_xcc
The SPARCv9 ABI returns a float in %f0. This is different from the argument passing convention which puts the first float argument in %f1. With this patch, all returned floats are treated as if the 'inreg' flag were set. This means multiple float return values get packed in %f0, %f1, %f2, ... Note that when returning a struct in registers, clang will set the 'inreg' flag on the return value, so that behavior is unchanged. This also happens when returning a float _Complex. llvm-svn: 199028
2014-01-12 12:13:17 +08:00
; CHECK: fmovs %f7, %f0
[Sparc] Return true in enableMultipleCopyHints(). Enable multiple COPY hints to eliminate more COPYs during register allocation. Note that this is something all targets should do, see https://reviews.llvm.org/D38128. Review: James Y Knight llvm-svn: 326028
2018-02-24 16:24:31 +08:00
; CHECK: cmp %i0, %i1
; CHECK: fmovsg %xcc, %f5, %f0
Add floating point selects on %xcc predicates. llvm-svn: 182222
2013-05-20 04:33:11 +08:00
define float @selectf32_xcc(i64 %x, i64 %y, float %a, float %b) {
entry:
%tobool = icmp sgt i64 %x, %y
%rv = select i1 %tobool, float %a, float %b
ret float %rv
}
; CHECK: selectf64_xcc
; CHECK: fmovd %f6, %f0
[Sparc] Return true in enableMultipleCopyHints(). Enable multiple COPY hints to eliminate more COPYs during register allocation. Note that this is something all targets should do, see https://reviews.llvm.org/D38128. Review: James Y Knight llvm-svn: 326028
2018-02-24 16:24:31 +08:00
; CHECK: cmp %i0, %i1
; CHECK: fmovdg %xcc, %f4, %f0
Add floating point selects on %xcc predicates. llvm-svn: 182222
2013-05-20 04:33:11 +08:00
define double @selectf64_xcc(i64 %x, i64 %y, double %a, double %b) {
entry:
%tobool = icmp sgt i64 %x, %y
%rv = select i1 %tobool, double %a, double %b
ret double %rv
}
Don't use %g0 to materialize 0 directly. The wired physreg doesn't work on tied operands like on MOVXCC. Add a README note to fix this later. llvm-svn: 182225
2013-05-20 05:47:13 +08:00
; The MOVXCC instruction can't use %g0 for its tied operand.
; CHECK: select_consti64_xcc
[Sparc]: Use cmp instruction instead of subcc to compare integers. llvm-svn: 183463
2013-06-07 08:03:36 +08:00
; CHECK: cmp
Allocate local registers in order for optimal coloring. Also avoid locals evicting locals just because they want a cheaper register. Problem: MI Sched knows exactly how many registers we have and assumes they can be colored. In cases where we have large blocks, usually from unrolled loops, greedy coloring fails. This is a source of "regressions" from the MI Scheduler on x86. I noticed this issue on x86 where we have long chains of two-address defs in the same live range. It's easy to see this in matrix multiplication benchmarks like IRSmk and even the unit test misched-matmul.ll. A fundamental difference between the LLVM register allocator and conventional graph coloring is that in our model a live range can't discover its neighbors, it can only verify its neighbors. That's why we initially went for greedy coloring and added eviction to deal with the hard cases. However, for singly defined and two-address live ranges, we can optimally color without visiting neighbors simply by processing the live ranges in instruction order. Other beneficial side effects: It is much easier to understand and debug regalloc for large blocks when the live ranges are allocated in order. Yes, global allocation is still very confusing, but it's nice to be able to comprehend what happened locally. Heuristics could be added to bias register assignment based on instruction locality (think late register pairing, banks...). Intuituvely this will make some test cases that are on the threshold of register pressure more stable. llvm-svn: 187139
2013-07-26 02:35:14 +08:00
; CHECK: movg %xcc, 123, %i{{[0-2]}}
Don't use %g0 to materialize 0 directly. The wired physreg doesn't work on tied operands like on MOVXCC. Add a README note to fix this later. llvm-svn: 182225
2013-05-20 05:47:13 +08:00
define i64 @select_consti64_xcc(i64 %x, i64 %y) {
entry:
%tobool = icmp sgt i64 %x, %y
%rv = select i1 %tobool, i64 123, i64 0
ret i64 %rv
}
[Sparc]: Implement getSetCCResultType() in SparcTargetLowering so that umulo/smulo can be lowered on sparcv9 without an assertion error. llvm-svn: 196751
2013-12-09 12:02:15 +08:00
; CHECK-LABEL: setcc_resultty
[SparcV9]: Custom lower UMULO/SMULO so that the arguments are send to __multi3() in correct order. llvm-svn: 198281
2014-01-02 04:22:45 +08:00
; CHECK-DAG: srax %i0, 63, %o0
TableGen: fix operand counting for aliases TableGen has a fairly dubious heuristic to decide whether an alias should be printed: does the alias have lest operands than the real instruction. This is bad enough (particularly with no way to override it), but it should at least be calculated consistently for both strings. This patch implements that logic: first get the *correct* string for the variant, in the same way as the Matcher, without guessing; then count the number of whitespace chars. There are basically 4 changes this brings about after the previous commits; all of these appear to be good, so I have changed the tests: + ARM64: we print "neg X, Y" instead of "sub X, xzr, Y". + ARM64: we skip implicit "uxtx" and "uxtw" modifiers. + Sparc: we print "mov A, B" instead of "or %g0, A, B". + Sparc: we print "fcmpX A, B" instead of "fcmpX %fcc0, A, B" llvm-svn: 208969
2014-05-16 17:42:04 +08:00
; CHECK-DAG: mov %i0, %o1
; CHECK-DAG: mov 0, %o2
; CHECK-DAG: mov 32, %o3
[SparcV9]: Custom lower UMULO/SMULO so that the arguments are send to __multi3() in correct order. llvm-svn: 198281
2014-01-02 04:22:45 +08:00
; CHECK-DAG: call __multi3
[Sparc]: Implement getSetCCResultType() in SparcTargetLowering so that umulo/smulo can be lowered on sparcv9 without an assertion error. llvm-svn: 196751
2013-12-09 12:02:15 +08:00
; CHECK: cmp
; CHECK: movne %xcc, 1, [[R:%[gilo][0-7]]]
; CHECK: or [[R]], %i1, %i0
define i1 @setcc_resultty(i64 %a, i1 %b) {
%a0 = tail call { i64, i1 } @llvm.umul.with.overflow.i64(i64 %a, i64 32)
%a1 = extractvalue { i64, i1 } %a0, 1
%a4 = or i1 %a1, %b
ret i1 %a4
}
declare { i64, i1 } @llvm.umul.with.overflow.i64(i64, i64)