forked from OSchip/llvm-project
56 lines
1.9 KiB
LLVM
56 lines
1.9 KiB
LLVM
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; RUN: opt %s -analyze -divergence -use-gpu-divergence-analysis | FileCheck %s
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target datalayout = "e-i64:64-v16:16-v32:32-n16:32:64"
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target triple = "nvptx64-nvidia-cuda"
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; This test contains an unstructured loop.
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; +-------------- entry ----------------+
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; | |
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; V V
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; i1 = phi(0, i3) i2 = phi(0, i3)
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; j1 = i1 + 1 ---> i3 = phi(j1, j2) <--- j2 = i2 + 2
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; ^ | ^
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; | V |
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; +-------- switch (tid / i3) ----------+
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; |
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; V
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; if (i3 == 5) // divergent
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; because sync dependent on (tid / i3).
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define i32 @unstructured_loop(i1 %entry_cond) {
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; CHECK-LABEL: Printing analysis 'Legacy Divergence Analysis' for function 'unstructured_loop'
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entry:
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%tid = call i32 @llvm.nvvm.read.ptx.sreg.tid.x()
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br i1 %entry_cond, label %loop_entry_1, label %loop_entry_2
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loop_entry_1:
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%i1 = phi i32 [ 0, %entry ], [ %i3, %loop_latch ]
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%j1 = add i32 %i1, 1
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br label %loop_body
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loop_entry_2:
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%i2 = phi i32 [ 0, %entry ], [ %i3, %loop_latch ]
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%j2 = add i32 %i2, 2
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br label %loop_body
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loop_body:
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%i3 = phi i32 [ %j1, %loop_entry_1 ], [ %j2, %loop_entry_2 ]
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br label %loop_latch
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loop_latch:
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%div = sdiv i32 %tid, %i3
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switch i32 %div, label %branch [ i32 1, label %loop_entry_1
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i32 2, label %loop_entry_2 ]
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branch:
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%cmp = icmp eq i32 %i3, 5
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br i1 %cmp, label %then, label %else
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; CHECK: DIVERGENT: br i1 %cmp,
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then:
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ret i32 0
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else:
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ret i32 1
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}
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declare i32 @llvm.nvvm.read.ptx.sreg.tid.x()
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declare i32 @llvm.nvvm.read.ptx.sreg.tid.y()
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declare i32 @llvm.nvvm.read.ptx.sreg.tid.z()
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declare i32 @llvm.nvvm.read.ptx.sreg.laneid()
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!nvvm.annotations = !{!0}
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!0 = !{i32 (i1)* @unstructured_loop, !"kernel", i32 1}
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