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llvm-project/llvm/lib/Target/ARM/CMakeLists.txt

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CMake: Builds all targets. llvm-svn: 56641
2008-09-26 12:40:32 +08:00
set(LLVM_TARGET_DEFINITIONS ARM.td)
tablegen(ARMGenRegisterInfo.h.inc -gen-register-desc-header)
tablegen(ARMGenRegisterNames.inc -gen-register-enums)
tablegen(ARMGenRegisterInfo.inc -gen-register-desc)
tablegen(ARMGenInstrNames.inc -gen-instr-enums)
tablegen(ARMGenInstrInfo.inc -gen-instr-desc)
tablegen(ARMGenCodeEmitter.inc -gen-emitter)
Teach ARM Target to use the tblgen support for generating an MC'ized CodeEmitter. llvm-svn: 118209
2010-11-04 07:52:49 +08:00
tablegen(ARMGenMCCodeEmitter.inc -gen-emitter -mc-emitter)
CMake: Builds all targets. llvm-svn: 56641
2008-09-26 12:40:32 +08:00
tablegen(ARMGenAsmWriter.inc -gen-asm-writer)
MC/ARM: Enable generation of the ARM asm matcher, not that it can do much. llvm-svn: 110782
2010-08-11 13:09:20 +08:00
tablegen(ARMGenAsmMatcher.inc -gen-asm-matcher)
CMake: Builds all targets. llvm-svn: 56641
2008-09-26 12:40:32 +08:00
tablegen(ARMGenDAGISel.inc -gen-dag-isel)
MC/ARM: Enable generation of the ARM asm matcher, not that it can do much. llvm-svn: 110782
2010-08-11 13:09:20 +08:00
tablegen(ARMGenFastISel.inc -gen-fast-isel)
Use CallConvLower.h and TableGen descriptions of the calling conventions for ARM. Patch by Sandeep Patel. llvm-svn: 69371
2009-04-18 03:07:39 +08:00
tablegen(ARMGenCallingConv.inc -gen-callingconv)
CMake: Builds all targets. llvm-svn: 56641
2008-09-26 12:40:32 +08:00
tablegen(ARMGenSubtarget.inc -gen-subtarget)
Unbreak CMake build by improving the EnhancedDisassembly makefile a bit (we're not trying to build a shared library yet) and generating the X86GenEDInfo.inc and ARMGenEDInfo.inc files as necessary. llvm-svn: 101188
2010-04-14 06:47:43 +08:00
tablegen(ARMGenEDInfo.inc -gen-enhanced-disassembly-info)
Add ARM Disassembler to the CMake build. llvm-svn: 114949
2010-09-28 19:48:19 +08:00
tablegen(ARMGenDecoderTables.inc -gen-arm-decoder)
CMake: Builds all targets. llvm-svn: 56641
2008-09-26 12:40:32 +08:00
CMake: Turned some libraries into partially linked objects. Corrected names of LLVMCore and ARMCodeGen. llvm-svn: 57943
2008-10-22 10:51:53 +08:00
add_llvm_target(ARMCodeGen
I added a new file ARMAsmBackend which stubs out in similar ways to the eqv X86 class. For now, I split the ELFARMAsmBackend from the DarwinARMAsmBackend (also mimicking X86) Tested against -r115126 llvm-svn: 115129
2010-09-30 10:17:26 +08:00
ARMAsmBackend.cpp
Update CMake files. llvm-svn: 108787
2010-07-20 08:08:13 +08:00
ARMAsmPrinter.cpp
Checkpoint Thumb2 Instr info work. Generalized base code so that it can be shared between ARM and Thumb2. Not yet activated because register information must be generalized first. llvm-svn: 75010
2009-07-09 00:09:28 +08:00
ARMBaseInstrInfo.cpp
Fix cmake build. Added ARMBaseRegisterInfo.cpp to lib/Target/ARM/CMakeLists.txt llvm-svn: 75035
2009-07-09 04:13:41 +08:00
ARMBaseRegisterInfo.cpp
CMake: Builds all targets. llvm-svn: 56641
2008-09-26 12:40:32 +08:00
ARMCodeEmitter.cpp
ARMConstantIslandPass.cpp
ARMConstantPoolValue.cpp
Odd additional stub framework for the ARM MC ELF emission. llc now recognizes the "intent" to support MC/obj emission for ARM, but given that they are all stubs, it asserts on --filetype=obj --march=arm Patch by Jason Kim. llvm-svn: 114856
2010-09-28 02:31:37 +08:00
ARMELFWriterInfo.cpp
Update CMake file. llvm-svn: 86325
2009-11-07 11:26:59 +08:00
ARMExpandPseudoInsts.cpp
Update CMake files. llvm-svn: 109081
2010-07-22 14:00:01 +08:00
ARMFastISel.cpp
Update CMake stuff llvm-svn: 123171
2011-01-10 20:39:23 +08:00
ARMFrameLowering.cpp
Unbreak CMake build llvm-svn: 109372
2010-07-26 01:10:14 +08:00
ARMGlobalMerge.cpp
Making use of VFP / NEON floating point multiply-accumulate / subtraction is difficult on current ARM implementations for a few reasons. 1. Even though a single vmla has latency that is one cycle shorter than a pair of vmul + vadd, a RAW hazard during the first (4? on Cortex-a8) can cause additional pipeline stall. So it's frequently better to single codegen vmul + vadd. 2. A vmla folowed by a vmul, vmadd, or vsub causes the second fp instruction to stall for 4 cycles. We need to schedule them apart. 3. A vmla followed vmla is a special case. Obvious issuing back to back RAW vmla + vmla is very bad. But this isn't ideal either: vmul vadd vmla Instead, we want to expand the second vmla: vmla vmul vadd Even with the 4 cycle vmul stall, the second sequence is still 2 cycles faster. Up to now, isel simply avoid codegen'ing fp vmla / vmls. This works well enough but it isn't the optimial solution. This patch attempts to make it possible to use vmla / vmls in cases where it is profitable. A. Add missing isel predicates which cause vmla to be codegen'ed. B. Make sure the fmul in (fadd (fmul)) has a single use. We don't want to compute a fmul and a fmla. C. Add additional isel checks for vmla, avoid cases where vmla is feeding into fp instructions (except for the #3 exceptional case). D. Add ARM hazard recognizer to model the vmla / vmls hazards. E. Add a special pre-regalloc case to expand vmla / vmls when it's likely the vmla / vmls will trigger one of the special hazards. Work in progress, only A+B are enabled. llvm-svn: 120960
2010-12-06 06:04:16 +08:00
ARMHazardRecognizer.cpp
CMake: Builds all targets. llvm-svn: 56641
2008-09-26 12:40:32 +08:00
ARMISelDAGToDAG.cpp
ARMISelLowering.cpp
Update CMake file. llvm-svn: 85861
2009-11-03 12:14:12 +08:00
ARMInstrInfo.cpp
CMake: Builds all targets. llvm-svn: 56641
2008-09-26 12:40:32 +08:00
ARMJITInfo.cpp
Add skeleton infrastructure for the ARMMCCodeEmitter class. Patch by Jason Kim! llvm-svn: 114195
2010-09-18 02:46:17 +08:00
ARMMCCodeEmitter.cpp
Model :upper16: and :lower16: as ARM specific MCTargetExpr. This is a step in the right direction. It eliminated some hacks and will unblock codegen work. But it's far from being done. It doesn't reject illegal expressions, e.g. (FOO - :lower16:BAR). It also doesn't work in Thumb2 mode at all. llvm-svn: 123369
2011-01-13 15:58:56 +08:00
ARMMCExpr.cpp
CMake: Builds all targets. llvm-svn: 56641
2008-09-26 12:40:32 +08:00
ARMLoadStoreOptimizer.cpp
Normalize makefile comments and sort cmake file lists. llvm-svn: 80584
2009-08-31 21:05:24 +08:00
ARMMCAsmInfo.cpp
Update CMake files. llvm-svn: 108787
2010-07-20 08:08:13 +08:00
ARMMCInstLower.cpp
CMake: Builds all targets. llvm-svn: 56641
2008-09-26 12:40:32 +08:00
ARMRegisterInfo.cpp
Update CMake files. llvm-svn: 108787
2010-07-20 08:08:13 +08:00
ARMSelectionDAGInfo.cpp
CMake: Builds all targets. llvm-svn: 56641
2008-09-26 12:40:32 +08:00
ARMSubtarget.cpp
ARMTargetMachine.cpp
The ARM EH experiment worked! Place the LSDA into the TEXT section for ARM platforms. This involves making the encoding indirect, pcrel, and sdata4 instead of an absolute pointer. The references to the type infos are then non-lazy pointers. Revision 98019 changed the encoding of non-lazy pointers to add the symbol to the non-lazy pointer definition if it's a local symbol (otherwise, it's external and set to '0' so that the loader can adjust it to the real value). This paved the way for this change to work on ARM. llvm-svn: 98068
2010-03-10 02:31:07 +08:00
ARMTargetObjectFile.cpp
ARM/CMakeLists.txt: Add missing MLxExpansionPass.cpp since r120960. llvm-svn: 120966
2010-12-06 07:08:57 +08:00
MLxExpansionPass.cpp
Update CMake file. llvm-svn: 85861
2009-11-03 12:14:12 +08:00
NEONMoveFix.cpp
Checkpoint refactoring of ThumbInstrInfo and ThumbRegisterInfo into Thumb1InstrInfo, Thumb2InstrInfo, Thumb1RegisterInfo and Thumb2RegisterInfo. Move methods from ARMInstrInfo to ARMBaseInstrInfo to prepare for sharing with Thumb2. llvm-svn: 74731
2009-07-03 06:18:33 +08:00
Thumb1InstrInfo.cpp
Update CMake stuff llvm-svn: 123171
2011-01-10 20:39:23 +08:00
Thumb1FrameLowering.cpp
Checkpoint refactoring of ThumbInstrInfo and ThumbRegisterInfo into Thumb1InstrInfo, Thumb2InstrInfo, Thumb1RegisterInfo and Thumb2RegisterInfo. Move methods from ARMInstrInfo to ARMBaseInstrInfo to prepare for sharing with Thumb2. llvm-svn: 74731
2009-07-03 06:18:33 +08:00
Thumb1RegisterInfo.cpp
Add Thumb2ITBlockPass.cpp to CMakeLists.txt, fixing the cmake build. llvm-svn: 75246
2009-07-10 16:31:50 +08:00
Thumb2ITBlockPass.cpp
Checkpoint refactoring of ThumbInstrInfo and ThumbRegisterInfo into Thumb1InstrInfo, Thumb2InstrInfo, Thumb1RegisterInfo and Thumb2RegisterInfo. Move methods from ARMInstrInfo to ARMBaseInstrInfo to prepare for sharing with Thumb2. llvm-svn: 74731
2009-07-03 06:18:33 +08:00
Thumb2InstrInfo.cpp
Thumb2RegisterInfo.cpp
Update CMake llvm-svn: 78475
2009-08-09 01:03:13 +08:00
Thumb2SizeReduction.cpp
CMake: Builds all targets. llvm-svn: 56641
2008-09-26 12:40:32 +08:00
)
CMake: Add disabling optimization on MSVC8 and MSVC10 as workaround for some files in Target/ARM and Target/X86. llvm-svn: 122623
2010-12-29 11:59:27 +08:00
# workaround for hanging compilation on MSVC10
if( MSVC_VERSION EQUAL 1600 )
set_property(
SOURCE ARMISelLowering.cpp
PROPERTY COMPILE_FLAGS "/Od"
)
endif()