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llvm-project/llvm/test/CodeGen/X86/shift-pair.ll

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Change this DAGCombine to build AND of SHR instead of SHR of AND; this matches the ordering we prefer in instcombine. Part of rdar://9562809. The potential DAGCombine which enforces this more generally messes up some other very fragile patterns, so I'm leaving that alone, at least for now. llvm-svn: 132809
2011-06-10 06:14:44 +08:00
; RUN: llc < %s -march=x86-64 | FileCheck %s
define i64 @test(i64 %A) {
; CHECK: @test
; CHECK: shrq $54
[X86] Don't use GR64 register 'and with immediate' instructions if the immediate is zero in the upper 33-bits or upper 57-bits. Use GR32 instructions instead. Previously the patterns didn't have high enough priority and we would only use the GR32 form if the only the upper 32 or 56 bits were zero. Fixes PR23100. llvm-svn: 234075
2015-04-04 10:08:20 +08:00
; CHECK: andl $1020
Change this DAGCombine to build AND of SHR instead of SHR of AND; this matches the ordering we prefer in instcombine. Part of rdar://9562809. The potential DAGCombine which enforces this more generally messes up some other very fragile patterns, so I'm leaving that alone, at least for now. llvm-svn: 132809
2011-06-10 06:14:44 +08:00
; CHECK: ret
%B = lshr i64 %A, 56
%C = shl i64 %B, 2
ret i64 %C
}