2017-09-23 07:46:57 +08:00
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//===- InterferenceCache.cpp - Caching per-block interference -------------===//
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2011-04-02 14:03:35 +08:00
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//
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2019-01-19 16:50:56 +08:00
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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2011-04-02 14:03:35 +08:00
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//
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//===----------------------------------------------------------------------===//
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//
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// InterferenceCache remembers per-block interference in LiveIntervalUnions.
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//
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//===----------------------------------------------------------------------===//
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#include "InterferenceCache.h"
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2017-09-23 07:46:57 +08:00
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#include "llvm/ADT/ArrayRef.h"
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2017-12-13 10:51:04 +08:00
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#include "llvm/CodeGen/LiveIntervals.h"
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2017-09-23 07:46:57 +08:00
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#include "llvm/CodeGen/MachineBasicBlock.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineOperand.h"
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2017-11-17 09:07:10 +08:00
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#include "llvm/CodeGen/TargetRegisterInfo.h"
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2017-09-23 07:46:57 +08:00
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#include "llvm/MC/MCRegisterInfo.h"
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2012-12-04 00:50:05 +08:00
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#include "llvm/Support/ErrorHandling.h"
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2017-09-23 07:46:57 +08:00
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#include <cassert>
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#include <cstdint>
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#include <tuple>
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2011-04-02 14:03:35 +08:00
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using namespace llvm;
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2014-04-22 10:02:50 +08:00
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#define DEBUG_TYPE "regalloc"
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2011-07-23 11:10:17 +08:00
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// Static member used for null interference cursors.
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2015-03-09 00:07:39 +08:00
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const InterferenceCache::BlockInterference
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InterferenceCache::Cursor::NoInterference;
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2011-07-23 11:10:17 +08:00
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2014-02-06 17:23:24 +08:00
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// Initializes PhysRegEntries (instead of a SmallVector, PhysRegEntries is a
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// buffer of size NumPhysRegs to speed up alloc/clear for targets with large
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// reg files). Calloced memory is used for good form, and quites tools like
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// Valgrind too, but zero initialized memory is not required by the algorithm:
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// this is because PhysRegEntries works like a SparseSet and its entries are
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// only valid when there is a corresponding CacheEntries assignment. There is
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// also support for when pass managers are reused for targets with different
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// numbers of PhysRegs: in this case PhysRegEntries is freed and reinitialized.
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void InterferenceCache::reinitPhysRegEntries() {
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if (PhysRegEntriesCount == TRI->getNumRegs()) return;
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free(PhysRegEntries);
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PhysRegEntriesCount = TRI->getNumRegs();
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Report fatal error in the case of out of memory
This is the second part of recommit of r325224. The previous part was
committed in r325426, which deals with C++ memory allocation. Solution
for C memory allocation involved functions `llvm::malloc` and similar.
This was a fragile solution because it caused ambiguity errors in some
cases. In this commit the new functions have names like `llvm::safe_malloc`.
The relevant part of original comment is below, updated for new function
names.
Analysis of fails in the case of out of memory errors can be tricky on
Windows. Such error emerges at the point where memory allocation function
fails, but manifests itself when null pointer is used. These two points
may be distant from each other. Besides, next runs may not exhibit
allocation error.
In some cases memory is allocated by a call to some of C allocation
functions, malloc, calloc and realloc. They are used for interoperability
with C code, when allocated object has variable size and when it is
necessary to avoid call of constructors. In many calls the result is not
checked for null pointer. To simplify checks, new functions are defined
in the namespace 'llvm': `safe_malloc`, `safe_calloc` and `safe_realloc`.
They behave as corresponding standard functions but produce fatal error if
allocation fails. This change replaces the standard functions like 'malloc'
in the cases when the result of the allocation function is not checked
for null pointer.
Finally, there are plain C code, that uses malloc and similar functions. If
the result is not checked, assert statement is added.
Differential Revision: https://reviews.llvm.org/D43010
llvm-svn: 325551
2018-02-20 13:41:26 +08:00
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PhysRegEntries = static_cast<unsigned char*>(
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safe_calloc(PhysRegEntriesCount, sizeof(unsigned char)));
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2014-02-06 17:23:24 +08:00
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}
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2011-04-02 14:03:35 +08:00
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void InterferenceCache::init(MachineFunction *mf,
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LiveIntervalUnion *liuarray,
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SlotIndexes *indexes,
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2012-02-11 02:58:34 +08:00
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LiveIntervals *lis,
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2011-07-23 11:10:17 +08:00
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const TargetRegisterInfo *tri) {
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2011-04-02 14:03:35 +08:00
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MF = mf;
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LIUArray = liuarray;
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TRI = tri;
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2014-02-06 17:23:24 +08:00
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reinitPhysRegEntries();
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2011-04-02 14:03:35 +08:00
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for (unsigned i = 0; i != CacheEntries; ++i)
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2012-02-11 02:58:34 +08:00
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Entries[i].clear(mf, indexes, lis);
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2011-04-02 14:03:35 +08:00
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}
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2020-10-07 05:38:41 +08:00
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InterferenceCache::Entry *InterferenceCache::get(MCRegister PhysReg) {
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unsigned char E = PhysRegEntries[PhysReg.id()];
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2011-04-02 14:03:35 +08:00
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if (E < CacheEntries && Entries[E].getPhysReg() == PhysReg) {
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if (!Entries[E].valid(LIUArray, TRI))
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2012-06-21 06:52:26 +08:00
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Entries[E].revalidate(LIUArray, TRI);
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2011-04-02 14:03:35 +08:00
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return &Entries[E];
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}
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// No valid entry exists, pick the next round-robin entry.
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E = RoundRobin;
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if (++RoundRobin == CacheEntries)
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RoundRobin = 0;
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2011-07-14 13:35:11 +08:00
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for (unsigned i = 0; i != CacheEntries; ++i) {
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// Skip entries that are in use.
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if (Entries[E].hasRefs()) {
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if (++E == CacheEntries)
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E = 0;
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continue;
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}
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Entries[E].reset(PhysReg, LIUArray, TRI, MF);
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PhysRegEntries[PhysReg] = E;
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return &Entries[E];
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}
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llvm_unreachable("Ran out of interference cache entries.");
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2011-04-02 14:03:35 +08:00
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}
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/// revalidate - LIU contents have changed, update tags.
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2012-06-21 06:52:26 +08:00
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void InterferenceCache::Entry::revalidate(LiveIntervalUnion *LIUArray,
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const TargetRegisterInfo *TRI) {
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2011-04-02 14:03:35 +08:00
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// Invalidate all block entries.
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++Tag;
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// Invalidate all iterators.
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PrevPos = SlotIndex();
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2012-06-21 06:52:26 +08:00
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unsigned i = 0;
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for (MCRegUnitIterator Units(PhysReg, TRI); Units.isValid(); ++Units, ++i)
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RegUnits[i].VirtTag = LIUArray[*Units].getTag();
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2011-04-02 14:03:35 +08:00
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}
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2020-10-07 05:38:41 +08:00
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void InterferenceCache::Entry::reset(MCRegister physReg,
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2011-04-02 14:03:35 +08:00
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LiveIntervalUnion *LIUArray,
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const TargetRegisterInfo *TRI,
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const MachineFunction *MF) {
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2011-07-14 13:35:11 +08:00
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assert(!hasRefs() && "Cannot reset cache entry with references");
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2011-04-02 14:03:35 +08:00
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// LIU's changed, invalidate cache.
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++Tag;
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PhysReg = physReg;
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Blocks.resize(MF->getNumBlockIDs());
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// Reset iterators.
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PrevPos = SlotIndex();
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2012-06-21 06:52:26 +08:00
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RegUnits.clear();
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for (MCRegUnitIterator Units(PhysReg, TRI); Units.isValid(); ++Units) {
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RegUnits.push_back(LIUArray[*Units]);
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RegUnits.back().Fixed = &LIS->getRegUnit(*Units);
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}
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2011-04-02 14:03:35 +08:00
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}
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bool InterferenceCache::Entry::valid(LiveIntervalUnion *LIUArray,
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const TargetRegisterInfo *TRI) {
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2012-06-21 06:52:26 +08:00
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unsigned i = 0, e = RegUnits.size();
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for (MCRegUnitIterator Units(PhysReg, TRI); Units.isValid(); ++Units, ++i) {
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if (i == e)
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2011-04-02 14:03:35 +08:00
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return false;
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2012-06-21 06:52:26 +08:00
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if (LIUArray[*Units].changedSince(RegUnits[i].VirtTag))
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2011-04-02 14:03:35 +08:00
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return false;
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}
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return i == e;
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}
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void InterferenceCache::Entry::update(unsigned MBBNum) {
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SlotIndex Start, Stop;
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2014-03-02 21:30:33 +08:00
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std::tie(Start, Stop) = Indexes->getMBBRange(MBBNum);
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2011-04-02 14:03:35 +08:00
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// Use advanceTo only when possible.
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2011-04-08 01:27:50 +08:00
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if (PrevPos != Start) {
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2012-06-21 06:52:26 +08:00
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if (!PrevPos.isValid() || Start < PrevPos) {
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for (unsigned i = 0, e = RegUnits.size(); i != e; ++i) {
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RegUnitInfo &RUI = RegUnits[i];
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RUI.VirtI.find(Start);
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RUI.FixedI = RUI.Fixed->find(Start);
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}
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} else {
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for (unsigned i = 0, e = RegUnits.size(); i != e; ++i) {
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RegUnitInfo &RUI = RegUnits[i];
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RUI.VirtI.advanceTo(Start);
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if (RUI.FixedI != RUI.Fixed->end())
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RUI.FixedI = RUI.Fixed->advanceTo(RUI.FixedI, Start);
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}
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}
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2011-04-08 01:27:50 +08:00
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PrevPos = Start;
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}
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2011-04-02 14:03:35 +08:00
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2015-10-10 03:13:58 +08:00
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MachineFunction::const_iterator MFI =
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MF->getBlockNumbered(MBBNum)->getIterator();
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2011-04-09 10:59:05 +08:00
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BlockInterference *BI = &Blocks[MBBNum];
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2012-02-11 02:58:34 +08:00
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ArrayRef<SlotIndex> RegMaskSlots;
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ArrayRef<const uint32_t*> RegMaskBits;
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2017-09-23 07:46:57 +08:00
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while (true) {
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2011-04-09 10:59:05 +08:00
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BI->Tag = Tag;
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BI->First = BI->Last = SlotIndex();
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2012-06-21 06:52:26 +08:00
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// Check for first interference from virtregs.
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for (unsigned i = 0, e = RegUnits.size(); i != e; ++i) {
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LiveIntervalUnion::SegmentIter &I = RegUnits[i].VirtI;
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2011-04-09 10:59:05 +08:00
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if (!I.valid())
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continue;
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SlotIndex StartI = I.start();
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if (StartI >= Stop)
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continue;
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if (!BI->First.isValid() || StartI < BI->First)
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BI->First = StartI;
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}
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2011-04-02 14:03:35 +08:00
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2012-06-21 06:52:26 +08:00
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// Same thing for fixed interference.
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for (unsigned i = 0, e = RegUnits.size(); i != e; ++i) {
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LiveInterval::const_iterator I = RegUnits[i].FixedI;
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LiveInterval::const_iterator E = RegUnits[i].Fixed->end();
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if (I == E)
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continue;
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SlotIndex StartI = I->start;
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if (StartI >= Stop)
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continue;
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if (!BI->First.isValid() || StartI < BI->First)
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BI->First = StartI;
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}
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2012-02-11 02:58:34 +08:00
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// Also check for register mask interference.
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RegMaskSlots = LIS->getRegMaskSlotsInBlock(MBBNum);
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RegMaskBits = LIS->getRegMaskBitsInBlock(MBBNum);
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SlotIndex Limit = BI->First.isValid() ? BI->First : Stop;
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for (unsigned i = 0, e = RegMaskSlots.size();
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i != e && RegMaskSlots[i] < Limit; ++i)
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2012-02-11 03:23:53 +08:00
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if (MachineOperand::clobbersPhysReg(RegMaskBits[i], PhysReg)) {
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2012-02-11 02:58:34 +08:00
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// Register mask i clobbers PhysReg before the LIU interference.
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BI->First = RegMaskSlots[i];
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break;
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}
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2011-04-09 10:59:05 +08:00
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PrevPos = Stop;
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if (BI->First.isValid())
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break;
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// No interference in this block? Go ahead and precompute the next block.
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if (++MFI == MF->end())
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return;
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MBBNum = MFI->getNumber();
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BI = &Blocks[MBBNum];
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if (BI->Tag == Tag)
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return;
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2014-03-02 21:30:33 +08:00
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std::tie(Start, Stop) = Indexes->getMBBRange(MBBNum);
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2011-04-09 10:59:05 +08:00
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}
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2011-04-02 14:03:35 +08:00
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2011-04-09 10:59:05 +08:00
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// Check for last interference in block.
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2012-06-21 06:52:26 +08:00
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for (unsigned i = 0, e = RegUnits.size(); i != e; ++i) {
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LiveIntervalUnion::SegmentIter &I = RegUnits[i].VirtI;
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2011-04-02 14:03:35 +08:00
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if (!I.valid() || I.start() >= Stop)
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continue;
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I.advanceTo(Stop);
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2011-04-08 01:27:50 +08:00
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bool Backup = !I.valid() || I.start() >= Stop;
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if (Backup)
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2011-04-02 14:03:35 +08:00
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--I;
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SlotIndex StopI = I.stop();
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if (!BI->Last.isValid() || StopI > BI->Last)
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BI->Last = StopI;
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2011-04-08 01:27:50 +08:00
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if (Backup)
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++I;
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2011-04-02 14:03:35 +08:00
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}
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2012-02-11 02:58:34 +08:00
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2012-06-21 06:52:26 +08:00
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// Fixed interference.
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for (unsigned i = 0, e = RegUnits.size(); i != e; ++i) {
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LiveInterval::iterator &I = RegUnits[i].FixedI;
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2013-10-11 05:29:02 +08:00
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LiveRange *LR = RegUnits[i].Fixed;
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if (I == LR->end() || I->start >= Stop)
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2012-06-21 06:52:26 +08:00
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continue;
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2013-10-11 05:29:02 +08:00
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I = LR->advanceTo(I, Stop);
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bool Backup = I == LR->end() || I->start >= Stop;
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2012-06-21 06:52:26 +08:00
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if (Backup)
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--I;
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SlotIndex StopI = I->end;
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if (!BI->Last.isValid() || StopI > BI->Last)
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BI->Last = StopI;
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if (Backup)
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++I;
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}
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2012-02-11 02:58:34 +08:00
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// Also check for register mask interference.
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SlotIndex Limit = BI->Last.isValid() ? BI->Last : Start;
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2012-02-15 07:53:23 +08:00
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for (unsigned i = RegMaskSlots.size();
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i && RegMaskSlots[i-1].getDeadSlot() > Limit; --i)
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2012-02-11 03:23:53 +08:00
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if (MachineOperand::clobbersPhysReg(RegMaskBits[i-1], PhysReg)) {
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2012-02-11 02:58:34 +08:00
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// Register mask i-1 clobbers PhysReg after the LIU interference.
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// Model the regmask clobber as a dead def.
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BI->Last = RegMaskSlots[i-1].getDeadSlot();
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break;
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}
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2011-04-02 14:03:35 +08:00
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}
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