2012-02-18 20:03:15 +08:00
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//===-- X86InstrMMX.td - Describe the MMX Instruction Set --*- tablegen -*-===//
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2009-08-11 06:37:37 +08:00
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//
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2019-01-19 16:50:56 +08:00
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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2009-08-11 06:37:37 +08:00
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//
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2006-02-22 03:13:53 +08:00
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//===----------------------------------------------------------------------===//
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//
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// This file describes the X86 MMX instruction set, defining the instructions,
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// and properties of the instructions which are needed for code generation,
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// machine code emission, and analysis.
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//
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2010-09-09 09:02:39 +08:00
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// All instructions that use MMX should be in this file, even if they also use
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// SSE.
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//
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2006-02-22 03:13:53 +08:00
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//===----------------------------------------------------------------------===//
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2007-03-09 06:09:11 +08:00
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//===----------------------------------------------------------------------===//
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// MMX Multiclasses
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//===----------------------------------------------------------------------===//
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2018-01-16 06:32:40 +08:00
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// Alias instruction that maps zero vector to pxor mmx.
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// This is expanded by ExpandPostRAPseudos to an pxor.
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// We set canFoldAsLoad because this can be converted to a constant-pool
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// load of an all-zeros value if folding it would be beneficial.
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let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
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isPseudo = 1, SchedRW = [WriteZero] in {
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def MMX_SET0 : I<0, Pseudo, (outs VR64:$dst), (ins), "", []>;
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}
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2009-08-11 06:37:37 +08:00
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let Constraints = "$src1 = $dst" in {
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2010-10-01 07:57:10 +08:00
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// MMXI_binop_rm_int - Simple MMX binary operator based on intrinsic.
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2010-09-09 04:54:00 +08:00
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multiclass MMXI_binop_rm_int<bits<8> opc, string OpcodeStr, Intrinsic IntId,
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2018-04-12 18:49:57 +08:00
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X86FoldableSchedWrite sched, bit Commutable = 0,
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2017-12-29 16:31:01 +08:00
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X86MemOperand OType = i64mem> {
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2010-09-08 02:10:56 +08:00
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def irr : MMXI<opc, MRMSrcReg, (outs VR64:$dst),
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(ins VR64:$src1, VR64:$src2),
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!strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
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2018-04-12 18:49:57 +08:00
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[(set VR64:$dst, (IntId VR64:$src1, VR64:$src2))]>,
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Sched<[sched]> {
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2010-09-08 02:10:56 +08:00
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let isCommutable = Commutable;
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}
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def irm : MMXI<opc, MRMSrcMem, (outs VR64:$dst),
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2017-12-29 16:31:01 +08:00
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(ins VR64:$src1, OType:$src2),
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2010-09-08 02:10:56 +08:00
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!strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
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[(set VR64:$dst, (IntId VR64:$src1,
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2018-04-12 18:49:57 +08:00
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(bitconvert (load_mmx addr:$src2))))]>,
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2018-10-06 01:57:29 +08:00
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Sched<[sched.Folded, sched.ReadAfterFold]>;
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2010-09-08 02:10:56 +08:00
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}
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2007-03-23 02:42:45 +08:00
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multiclass MMXI_binop_rmi_int<bits<8> opc, bits<8> opc2, Format ImmForm,
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2008-05-03 08:52:09 +08:00
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string OpcodeStr, Intrinsic IntId,
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2018-05-04 01:56:43 +08:00
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Intrinsic IntId2, X86FoldableSchedWrite sched,
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X86FoldableSchedWrite schedImm> {
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2008-03-21 08:40:09 +08:00
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def rr : MMXI<opc, MRMSrcReg, (outs VR64:$dst),
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(ins VR64:$src1, VR64:$src2),
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2007-08-01 04:11:57 +08:00
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!strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
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2018-04-12 18:49:57 +08:00
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[(set VR64:$dst, (IntId VR64:$src1, VR64:$src2))]>,
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Sched<[sched]>;
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2008-03-21 08:40:09 +08:00
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def rm : MMXI<opc, MRMSrcMem, (outs VR64:$dst),
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(ins VR64:$src1, i64mem:$src2),
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2007-08-01 04:11:57 +08:00
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!strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
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2007-03-23 02:42:45 +08:00
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[(set VR64:$dst, (IntId VR64:$src1,
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2018-04-12 18:49:57 +08:00
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(bitconvert (load_mmx addr:$src2))))]>,
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2018-10-06 01:57:29 +08:00
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Sched<[sched.Folded, sched.ReadAfterFold]>;
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2008-03-21 08:40:09 +08:00
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def ri : MMXIi8<opc2, ImmForm, (outs VR64:$dst),
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2015-01-25 10:21:16 +08:00
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(ins VR64:$src1, i32u8imm:$src2),
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2007-08-01 04:11:57 +08:00
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!strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
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2019-09-23 09:21:51 +08:00
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[(set VR64:$dst, (IntId2 VR64:$src1, timm:$src2))]>,
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2018-05-04 01:56:43 +08:00
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Sched<[schedImm]>;
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2007-03-23 02:42:45 +08:00
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}
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2007-03-09 06:09:11 +08:00
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}
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2010-09-09 09:02:39 +08:00
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/// Unary MMX instructions requiring SSSE3.
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multiclass SS3I_unop_rm_int_mm<bits<8> opc, string OpcodeStr,
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2018-04-12 18:49:57 +08:00
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Intrinsic IntId64, X86FoldableSchedWrite sched> {
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2018-01-25 12:45:30 +08:00
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def rr : MMXSS38I<opc, MRMSrcReg, (outs VR64:$dst), (ins VR64:$src),
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!strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
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2018-04-12 18:49:57 +08:00
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[(set VR64:$dst, (IntId64 VR64:$src))]>,
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Sched<[sched]>;
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2018-01-25 12:45:30 +08:00
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def rm : MMXSS38I<opc, MRMSrcMem, (outs VR64:$dst), (ins i64mem:$src),
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!strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
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[(set VR64:$dst,
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2018-04-12 18:49:57 +08:00
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(IntId64 (bitconvert (load_mmx addr:$src))))]>,
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Sched<[sched.Folded]>;
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2010-09-09 09:02:39 +08:00
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}
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/// Binary MMX instructions requiring SSSE3.
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let ImmT = NoImm, Constraints = "$src1 = $dst" in {
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multiclass SS3I_binop_rm_int_mm<bits<8> opc, string OpcodeStr,
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2018-04-12 18:49:57 +08:00
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Intrinsic IntId64, X86FoldableSchedWrite sched,
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2016-07-26 16:06:18 +08:00
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bit Commutable = 0> {
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let isCommutable = Commutable in
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2018-01-25 12:45:30 +08:00
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def rr : MMXSS38I<opc, MRMSrcReg, (outs VR64:$dst),
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2010-09-09 09:02:39 +08:00
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(ins VR64:$src1, VR64:$src2),
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!strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
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2018-04-12 18:49:57 +08:00
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[(set VR64:$dst, (IntId64 VR64:$src1, VR64:$src2))]>,
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Sched<[sched]>;
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2018-01-25 12:45:30 +08:00
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def rm : MMXSS38I<opc, MRMSrcMem, (outs VR64:$dst),
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2010-09-09 09:02:39 +08:00
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(ins VR64:$src1, i64mem:$src2),
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!strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
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[(set VR64:$dst,
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(IntId64 VR64:$src1,
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2018-04-12 18:49:57 +08:00
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(bitconvert (load_mmx addr:$src2))))]>,
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2018-10-06 01:57:29 +08:00
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Sched<[sched.Folded, sched.ReadAfterFold]>;
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2010-09-09 09:02:39 +08:00
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}
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}
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/// PALIGN MMX instructions (require SSSE3).
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2018-05-03 17:11:32 +08:00
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multiclass ssse3_palign_mm<string asm, Intrinsic IntId,
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X86FoldableSchedWrite sched> {
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2018-01-25 12:45:30 +08:00
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def rri : MMXSS3AI<0x0F, MRMSrcReg, (outs VR64:$dst),
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2015-01-21 16:43:49 +08:00
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(ins VR64:$src1, VR64:$src2, u8imm:$src3),
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2014-12-04 13:20:33 +08:00
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!strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
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2019-09-20 00:26:14 +08:00
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[(set VR64:$dst, (IntId VR64:$src1, VR64:$src2, (i8 timm:$src3)))]>,
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2018-05-03 17:11:32 +08:00
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Sched<[sched]>;
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2018-01-25 12:45:30 +08:00
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def rmi : MMXSS3AI<0x0F, MRMSrcMem, (outs VR64:$dst),
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2015-01-21 16:43:49 +08:00
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(ins VR64:$src1, i64mem:$src2, u8imm:$src3),
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2010-09-09 09:02:39 +08:00
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!strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
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[(set VR64:$dst, (IntId VR64:$src1,
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2019-09-20 00:26:14 +08:00
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(bitconvert (load_mmx addr:$src2)), (i8 timm:$src3)))]>,
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2018-10-06 01:57:29 +08:00
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Sched<[sched.Folded, sched.ReadAfterFold]>;
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2010-09-09 09:02:39 +08:00
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}
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2010-09-10 01:13:07 +08:00
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multiclass sse12_cvt_pint<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
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Intrinsic Int, X86MemOperand x86memop, PatFrag ld_frag,
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2018-04-12 18:49:57 +08:00
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string asm, X86FoldableSchedWrite sched, Domain d> {
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Introduce 'UseSSEx' to force SSE legacy encoding
- Add 'UseSSEx' to force SSE legacy insn not being selected when AVX is
enabled.
As the penalty of inter-mixing SSE and AVX instructions, we need
prevent SSE legacy insn from being generated except explicitly
specified through some intrinsics. For patterns supported by both
SSE and AVX, so far, we force AVX insn will be tried first relying on
AddedComplexity or position in td file. It's error-prone and
introduces bugs accidentally.
'UseSSEx' is disabled when AVX is turned on. For SSE insns inherited
by AVX, we need this predicate to force VEX encoding or SSE legacy
encoding only.
For insns not inherited by AVX, we still use the previous predicates,
i.e. 'HasSSEx'. So far, these insns fall into the following
categories:
* SSE insns with MMX operands
* SSE insns with GPR/MEM operands only (xFENCE, PREFETCH, CLFLUSH,
CRC, and etc.)
* SSE4A insns.
* MMX insns.
* x87 insns added by SSE.
2 test cases are modified:
- test/CodeGen/X86/fast-isel-x86-64.ll
AVX code generation is different from SSE one. 'vcvtsi2sdq' cannot be
selected by fast-isel due to complicated pattern and fast-isel
fallback to materialize it from constant pool.
- test/CodeGen/X86/widen_load-1.ll
AVX code generation is different from SSE one after fixing SSE/AVX
inter-mixing. Exec-domain fixing prefers 'vmovapd' instead of
'vmovaps'.
llvm-svn: 162919
2012-08-31 00:54:46 +08:00
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def irr : MMXPI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src), asm,
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2018-04-12 18:49:57 +08:00
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[(set DstRC:$dst, (Int SrcRC:$src))], d>,
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Sched<[sched]>;
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Introduce 'UseSSEx' to force SSE legacy encoding
- Add 'UseSSEx' to force SSE legacy insn not being selected when AVX is
enabled.
As the penalty of inter-mixing SSE and AVX instructions, we need
prevent SSE legacy insn from being generated except explicitly
specified through some intrinsics. For patterns supported by both
SSE and AVX, so far, we force AVX insn will be tried first relying on
AddedComplexity or position in td file. It's error-prone and
introduces bugs accidentally.
'UseSSEx' is disabled when AVX is turned on. For SSE insns inherited
by AVX, we need this predicate to force VEX encoding or SSE legacy
encoding only.
For insns not inherited by AVX, we still use the previous predicates,
i.e. 'HasSSEx'. So far, these insns fall into the following
categories:
* SSE insns with MMX operands
* SSE insns with GPR/MEM operands only (xFENCE, PREFETCH, CLFLUSH,
CRC, and etc.)
* SSE4A insns.
* MMX insns.
* x87 insns added by SSE.
2 test cases are modified:
- test/CodeGen/X86/fast-isel-x86-64.ll
AVX code generation is different from SSE one. 'vcvtsi2sdq' cannot be
selected by fast-isel due to complicated pattern and fast-isel
fallback to materialize it from constant pool.
- test/CodeGen/X86/widen_load-1.ll
AVX code generation is different from SSE one after fixing SSE/AVX
inter-mixing. Exec-domain fixing prefers 'vmovapd' instead of
'vmovaps'.
llvm-svn: 162919
2012-08-31 00:54:46 +08:00
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def irm : MMXPI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src), asm,
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2018-04-12 18:49:57 +08:00
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[(set DstRC:$dst, (Int (ld_frag addr:$src)))], d>,
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Sched<[sched.Folded]>;
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2010-09-10 01:13:07 +08:00
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}
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multiclass sse12_cvt_pint_3addr<bits<8> opc, RegisterClass SrcRC,
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RegisterClass DstRC, Intrinsic Int, X86MemOperand x86memop,
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2018-04-12 18:49:57 +08:00
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PatFrag ld_frag, string asm, Domain d> {
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2013-06-14 17:31:41 +08:00
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def irr : MMXPI<opc, MRMSrcReg, (outs DstRC:$dst),
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(ins DstRC:$src1, SrcRC:$src2), asm,
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2018-04-12 18:49:57 +08:00
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[(set DstRC:$dst, (Int DstRC:$src1, SrcRC:$src2))], d>,
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2018-05-16 18:53:45 +08:00
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Sched<[WriteCvtI2PS]>;
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2013-06-14 17:31:41 +08:00
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def irm : MMXPI<opc, MRMSrcMem, (outs DstRC:$dst),
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(ins DstRC:$src1, x86memop:$src2), asm,
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2018-04-12 18:49:57 +08:00
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[(set DstRC:$dst, (Int DstRC:$src1, (ld_frag addr:$src2)))], d>,
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2018-05-16 18:53:45 +08:00
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Sched<[WriteCvtI2PS.Folded]>;
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2010-09-10 01:13:07 +08:00
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}
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2007-03-07 02:53:42 +08:00
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//===----------------------------------------------------------------------===//
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2010-10-04 02:42:30 +08:00
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// MMX EMMS Instruction
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2007-03-07 02:53:42 +08:00
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//===----------------------------------------------------------------------===//
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2019-02-04 12:44:20 +08:00
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let SchedRW = [WriteEMMS],
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Defs = [MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7,
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ST0, ST1, ST2, ST3, ST4, ST5, ST6, ST7] in
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2018-04-12 18:49:57 +08:00
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def MMX_EMMS : MMXI<0x77, RawFrm, (outs), (ins), "emms", [(int_x86_mmx_emms)]>;
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2007-03-07 02:53:42 +08:00
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//===----------------------------------------------------------------------===//
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// MMX Scalar Instructions
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//===----------------------------------------------------------------------===//
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2007-03-06 07:09:45 +08:00
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2007-04-04 07:48:32 +08:00
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// Data Transfer Instructions
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Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
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def MMX_MOVD64rr : MMXI<0x6E, MRMSrcReg, (outs VR64:$dst), (ins GR32:$src),
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- When DAG combiner is folding a bit convert into a BUILD_VECTOR, it should check if it's essentially a SCALAR_TO_VECTOR. Avoid turning (v8i16) <10, u, u, u> to <10, 0, u, u, u, u, u, u>. Instead, simply convert it to a SCALAR_TO_VECTOR of the proper type.
- X86 now normalize SCALAR_TO_VECTOR to (BIT_CONVERT (v4i32 SCALAR_TO_VECTOR)). Get rid of X86ISD::S2VEC.
llvm-svn: 47290
2008-02-19 07:04:32 +08:00
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"movd\t{$src, $dst|$dst, $src}",
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2014-12-04 13:20:33 +08:00
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[(set VR64:$dst,
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2018-04-12 18:49:57 +08:00
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(x86mmx (scalar_to_vector GR32:$src)))]>,
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2018-05-19 01:58:36 +08:00
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Sched<[WriteVecMoveFromGpr]>;
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Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
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def MMX_MOVD64rm : MMXI<0x6E, MRMSrcMem, (outs VR64:$dst), (ins i32mem:$src),
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- When DAG combiner is folding a bit convert into a BUILD_VECTOR, it should check if it's essentially a SCALAR_TO_VECTOR. Avoid turning (v8i16) <10, u, u, u> to <10, 0, u, u, u, u, u, u>. Instead, simply convert it to a SCALAR_TO_VECTOR of the proper type.
- X86 now normalize SCALAR_TO_VECTOR to (BIT_CONVERT (v4i32 SCALAR_TO_VECTOR)). Get rid of X86ISD::S2VEC.
llvm-svn: 47290
2008-02-19 07:04:32 +08:00
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"movd\t{$src, $dst|$dst, $src}",
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2012-05-11 22:27:12 +08:00
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[(set VR64:$dst,
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2018-04-12 18:49:57 +08:00
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|
|
(x86mmx (scalar_to_vector (loadi32 addr:$src))))]>,
|
2018-05-18 22:08:01 +08:00
|
|
|
Sched<[WriteVecLoad]>;
|
2015-02-05 21:23:07 +08:00
|
|
|
|
|
|
|
let Predicates = [HasMMX] in {
|
2018-07-11 02:41:58 +08:00
|
|
|
def : Pat<(x86mmx (MMX_X86movw2d GR32:$src)),
|
|
|
|
(MMX_MOVD64rr GR32:$src)>;
|
|
|
|
def : Pat<(x86mmx (MMX_X86movw2d (i32 0))),
|
|
|
|
(MMX_SET0)>;
|
|
|
|
def : Pat<(x86mmx (MMX_X86movw2d (loadi32 addr:$src))),
|
|
|
|
(MMX_MOVD64rm addr:$src)>;
|
2015-02-05 21:23:07 +08:00
|
|
|
}
|
|
|
|
|
2009-08-11 06:37:37 +08:00
|
|
|
let mayStore = 1 in
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
|
|
def MMX_MOVD64mr : MMXI<0x7E, MRMDestMem, (outs), (ins i32mem:$dst, VR64:$src),
|
2018-04-12 18:49:57 +08:00
|
|
|
"movd\t{$src, $dst|$dst, $src}", []>,
|
2018-05-18 22:08:01 +08:00
|
|
|
Sched<[WriteVecStore]>;
|
2012-10-31 06:15:38 +08:00
|
|
|
|
|
|
|
def MMX_MOVD64grr : MMXI<0x7E, MRMDestReg, (outs GR32:$dst), (ins VR64:$src),
|
|
|
|
"movd\t{$src, $dst|$dst, $src}",
|
|
|
|
[(set GR32:$dst,
|
2018-04-12 18:49:57 +08:00
|
|
|
(MMX_X86movd2w (x86mmx VR64:$src)))]>,
|
2018-05-19 01:58:36 +08:00
|
|
|
Sched<[WriteVecMoveToGpr]>, FoldGenData<"MMX_MOVD64rr">;
|
2007-04-04 07:48:32 +08:00
|
|
|
|
[PeepholeOptimizer] Look through PHIs to find additional register sources
Reintroduce r245442. Remove an overly conservative assertion introduced
in r245442. We could replace the assertion to use `shareSameRegisterFile`
instead, but in that point in `insertPHI` we already lost the original
Def subreg to check against. So drop the assertion completely.
Original commit message:
- Teaches the ValueTracker in the PeepholeOptimizer to look through PHI
instructions.
- Add findNextSourceAndRewritePHI method to lookup into multiple sources
returnted by the ValueTracker and rewrite PHIs with new sources.
With these changes we can find more register sources and rewrite more
copies to allow coaslescing of bitcast instructions. Hence, we eliminate
unnecessary VR64 <-> GR64 copies in x86, but it could be extended to
other archs by marking "isBitcast" on target specific instructions. The
x86 example follows:
A:
psllq %mm1, %mm0
movd %mm0, %r9
jmp C
B:
por %mm1, %mm0
movd %mm0, %r9
jmp C
C:
movd %r9, %mm0
pshufw $238, %mm0, %mm0
Becomes:
A:
psllq %mm1, %mm0
jmp C
B:
por %mm1, %mm0
jmp C
C:
pshufw $238, %mm0, %mm0
Differential Revision: http://reviews.llvm.org/D11197
rdar://problem/20404526
llvm-svn: 245479
2015-08-20 02:53:36 +08:00
|
|
|
let isBitcast = 1 in
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
|
|
def MMX_MOVD64to64rr : MMXRI<0x6E, MRMSrcReg, (outs VR64:$dst), (ins GR64:$src),
|
2018-01-06 04:55:12 +08:00
|
|
|
"movq\t{$src, $dst|$dst, $src}",
|
2018-04-12 18:49:57 +08:00
|
|
|
[(set VR64:$dst, (bitconvert GR64:$src))]>,
|
2018-05-19 01:58:36 +08:00
|
|
|
Sched<[WriteVecMoveFromGpr]>;
|
2007-07-04 08:19:54 +08:00
|
|
|
|
2015-02-22 15:50:41 +08:00
|
|
|
let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0, mayLoad = 1 in
|
|
|
|
def MMX_MOVD64to64rm : MMXRI<0x6E, MRMSrcMem, (outs VR64:$dst),
|
2018-01-06 04:55:12 +08:00
|
|
|
(ins i64mem:$src), "movq\t{$src, $dst|$dst, $src}",
|
2018-05-12 00:38:59 +08:00
|
|
|
[]>, Sched<[SchedWriteVecMoveLS.MMX.RM]>;
|
2015-02-22 15:50:41 +08:00
|
|
|
|
2018-05-19 01:58:36 +08:00
|
|
|
let isBitcast = 1 in {
|
2009-08-03 11:27:05 +08:00
|
|
|
def MMX_MOVD64from64rr : MMXRI<0x7E, MRMDestReg,
|
2009-02-23 17:03:22 +08:00
|
|
|
(outs GR64:$dst), (ins VR64:$src),
|
2018-01-06 04:55:12 +08:00
|
|
|
"movq\t{$src, $dst|$dst, $src}",
|
2018-05-19 01:58:36 +08:00
|
|
|
[(set GR64:$dst, (bitconvert VR64:$src))]>,
|
|
|
|
Sched<[WriteVecMoveToGpr]>;
|
2018-05-23 23:28:28 +08:00
|
|
|
let SchedRW = [WriteVecMove], hasSideEffects = 0, isMoveReg = 1 in {
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
|
|
def MMX_MOVQ64rr : MMXI<0x6F, MRMSrcReg, (outs VR64:$dst), (ins VR64:$src),
|
2018-04-12 18:49:57 +08:00
|
|
|
"movq\t{$src, $dst|$dst, $src}", []>;
|
2018-05-19 01:58:36 +08:00
|
|
|
let isCodeGenOnly = 1, ForceDisassemble = 1 in
|
2014-04-17 14:33:45 +08:00
|
|
|
def MMX_MOVQ64rr_REV : MMXI<0x7F, MRMDestReg, (outs VR64:$dst), (ins VR64:$src),
|
2018-04-12 18:49:57 +08:00
|
|
|
"movq\t{$src, $dst|$dst, $src}", []>,
|
|
|
|
FoldGenData<"MMX_MOVQ64rr">;
|
2018-05-23 23:28:28 +08:00
|
|
|
} // SchedRW, hasSideEffects, isMoveReg
|
2018-05-19 01:58:36 +08:00
|
|
|
} // isBitcast
|
2013-03-27 02:24:20 +08:00
|
|
|
|
2018-06-18 13:00:50 +08:00
|
|
|
def : InstAlias<"movq.s\t{$src, $dst|$dst, $src}",
|
|
|
|
(MMX_MOVQ64rr_REV VR64:$dst, VR64:$src), 0>;
|
|
|
|
|
2015-02-22 15:50:41 +08:00
|
|
|
let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0, mayStore = 1 in
|
|
|
|
def MMX_MOVD64from64rm : MMXRI<0x7E, MRMDestMem,
|
2016-03-13 10:56:31 +08:00
|
|
|
(outs), (ins i64mem:$dst, VR64:$src),
|
2018-04-12 18:49:57 +08:00
|
|
|
"movq\t{$src, $dst|$dst, $src}", []>,
|
2018-05-12 00:38:59 +08:00
|
|
|
Sched<[SchedWriteVecMoveLS.MMX.MR]>;
|
2015-02-22 15:50:41 +08:00
|
|
|
|
2018-05-12 00:38:59 +08:00
|
|
|
let SchedRW = [SchedWriteVecMoveLS.MMX.RM] in {
|
2010-10-01 07:57:10 +08:00
|
|
|
let canFoldAsLoad = 1 in
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
|
|
def MMX_MOVQ64rm : MMXI<0x6F, MRMSrcMem, (outs VR64:$dst), (ins i64mem:$src),
|
2007-08-01 04:11:57 +08:00
|
|
|
"movq\t{$src, $dst|$dst, $src}",
|
2018-04-12 18:49:57 +08:00
|
|
|
[(set VR64:$dst, (load_mmx addr:$src))]>;
|
2014-04-24 03:30:26 +08:00
|
|
|
} // SchedRW
|
2017-03-12 04:23:59 +08:00
|
|
|
|
2018-05-12 00:38:59 +08:00
|
|
|
let SchedRW = [SchedWriteVecMoveLS.MMX.MR] in
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
|
|
def MMX_MOVQ64mr : MMXI<0x7F, MRMDestMem, (outs), (ins i64mem:$dst, VR64:$src),
|
2007-08-01 04:11:57 +08:00
|
|
|
"movq\t{$src, $dst|$dst, $src}",
|
2018-04-12 18:49:57 +08:00
|
|
|
[(store (x86mmx VR64:$src), addr:$dst)]>;
|
2007-04-04 07:48:32 +08:00
|
|
|
|
2018-05-11 20:46:54 +08:00
|
|
|
let SchedRW = [SchedWriteVecMoveLS.XMM.RR] in {
|
Introduce 'UseSSEx' to force SSE legacy encoding
- Add 'UseSSEx' to force SSE legacy insn not being selected when AVX is
enabled.
As the penalty of inter-mixing SSE and AVX instructions, we need
prevent SSE legacy insn from being generated except explicitly
specified through some intrinsics. For patterns supported by both
SSE and AVX, so far, we force AVX insn will be tried first relying on
AddedComplexity or position in td file. It's error-prone and
introduces bugs accidentally.
'UseSSEx' is disabled when AVX is turned on. For SSE insns inherited
by AVX, we need this predicate to force VEX encoding or SSE legacy
encoding only.
For insns not inherited by AVX, we still use the previous predicates,
i.e. 'HasSSEx'. So far, these insns fall into the following
categories:
* SSE insns with MMX operands
* SSE insns with GPR/MEM operands only (xFENCE, PREFETCH, CLFLUSH,
CRC, and etc.)
* SSE4A insns.
* MMX insns.
* x87 insns added by SSE.
2 test cases are modified:
- test/CodeGen/X86/fast-isel-x86-64.ll
AVX code generation is different from SSE one. 'vcvtsi2sdq' cannot be
selected by fast-isel due to complicated pattern and fast-isel
fallback to materialize it from constant pool.
- test/CodeGen/X86/widen_load-1.ll
AVX code generation is different from SSE one after fixing SSE/AVX
inter-mixing. Exec-domain fixing prefers 'vmovapd' instead of
'vmovaps'.
llvm-svn: 162919
2012-08-31 00:54:46 +08:00
|
|
|
def MMX_MOVDQ2Qrr : MMXSDIi8<0xD6, MRMSrcReg, (outs VR64:$dst),
|
|
|
|
(ins VR128:$src), "movdq2q\t{$src, $dst|$dst, $src}",
|
|
|
|
[(set VR64:$dst,
|
|
|
|
(x86mmx (bitconvert
|
2015-12-12 03:20:16 +08:00
|
|
|
(i64 (extractelt (v2i64 VR128:$src),
|
2018-04-12 18:49:57 +08:00
|
|
|
(iPTR 0))))))]>;
|
Introduce 'UseSSEx' to force SSE legacy encoding
- Add 'UseSSEx' to force SSE legacy insn not being selected when AVX is
enabled.
As the penalty of inter-mixing SSE and AVX instructions, we need
prevent SSE legacy insn from being generated except explicitly
specified through some intrinsics. For patterns supported by both
SSE and AVX, so far, we force AVX insn will be tried first relying on
AddedComplexity or position in td file. It's error-prone and
introduces bugs accidentally.
'UseSSEx' is disabled when AVX is turned on. For SSE insns inherited
by AVX, we need this predicate to force VEX encoding or SSE legacy
encoding only.
For insns not inherited by AVX, we still use the previous predicates,
i.e. 'HasSSEx'. So far, these insns fall into the following
categories:
* SSE insns with MMX operands
* SSE insns with GPR/MEM operands only (xFENCE, PREFETCH, CLFLUSH,
CRC, and etc.)
* SSE4A insns.
* MMX insns.
* x87 insns added by SSE.
2 test cases are modified:
- test/CodeGen/X86/fast-isel-x86-64.ll
AVX code generation is different from SSE one. 'vcvtsi2sdq' cannot be
selected by fast-isel due to complicated pattern and fast-isel
fallback to materialize it from constant pool.
- test/CodeGen/X86/widen_load-1.ll
AVX code generation is different from SSE one after fixing SSE/AVX
inter-mixing. Exec-domain fixing prefers 'vmovapd' instead of
'vmovaps'.
llvm-svn: 162919
2012-08-31 00:54:46 +08:00
|
|
|
|
|
|
|
def MMX_MOVQ2DQrr : MMXS2SIi8<0xD6, MRMSrcReg, (outs VR128:$dst),
|
|
|
|
(ins VR64:$src), "movq2dq\t{$src, $dst|$dst, $src}",
|
|
|
|
[(set VR128:$dst,
|
|
|
|
(v2i64
|
|
|
|
(scalar_to_vector
|
2018-04-12 18:49:57 +08:00
|
|
|
(i64 (bitconvert (x86mmx VR64:$src))))))]>;
|
2007-04-04 07:48:32 +08:00
|
|
|
|
2013-10-09 12:54:21 +08:00
|
|
|
let isCodeGenOnly = 1, hasSideEffects = 1 in {
|
Introduce 'UseSSEx' to force SSE legacy encoding
- Add 'UseSSEx' to force SSE legacy insn not being selected when AVX is
enabled.
As the penalty of inter-mixing SSE and AVX instructions, we need
prevent SSE legacy insn from being generated except explicitly
specified through some intrinsics. For patterns supported by both
SSE and AVX, so far, we force AVX insn will be tried first relying on
AddedComplexity or position in td file. It's error-prone and
introduces bugs accidentally.
'UseSSEx' is disabled when AVX is turned on. For SSE insns inherited
by AVX, we need this predicate to force VEX encoding or SSE legacy
encoding only.
For insns not inherited by AVX, we still use the previous predicates,
i.e. 'HasSSEx'. So far, these insns fall into the following
categories:
* SSE insns with MMX operands
* SSE insns with GPR/MEM operands only (xFENCE, PREFETCH, CLFLUSH,
CRC, and etc.)
* SSE4A insns.
* MMX insns.
* x87 insns added by SSE.
2 test cases are modified:
- test/CodeGen/X86/fast-isel-x86-64.ll
AVX code generation is different from SSE one. 'vcvtsi2sdq' cannot be
selected by fast-isel due to complicated pattern and fast-isel
fallback to materialize it from constant pool.
- test/CodeGen/X86/widen_load-1.ll
AVX code generation is different from SSE one after fixing SSE/AVX
inter-mixing. Exec-domain fixing prefers 'vmovapd' instead of
'vmovaps'.
llvm-svn: 162919
2012-08-31 00:54:46 +08:00
|
|
|
def MMX_MOVQ2FR64rr: MMXS2SIi8<0xD6, MRMSrcReg, (outs FR64:$dst),
|
|
|
|
(ins VR64:$src), "movq2dq\t{$src, $dst|$dst, $src}",
|
2018-04-12 18:49:57 +08:00
|
|
|
[]>;
|
2009-02-23 17:03:22 +08:00
|
|
|
|
Introduce 'UseSSEx' to force SSE legacy encoding
- Add 'UseSSEx' to force SSE legacy insn not being selected when AVX is
enabled.
As the penalty of inter-mixing SSE and AVX instructions, we need
prevent SSE legacy insn from being generated except explicitly
specified through some intrinsics. For patterns supported by both
SSE and AVX, so far, we force AVX insn will be tried first relying on
AddedComplexity or position in td file. It's error-prone and
introduces bugs accidentally.
'UseSSEx' is disabled when AVX is turned on. For SSE insns inherited
by AVX, we need this predicate to force VEX encoding or SSE legacy
encoding only.
For insns not inherited by AVX, we still use the previous predicates,
i.e. 'HasSSEx'. So far, these insns fall into the following
categories:
* SSE insns with MMX operands
* SSE insns with GPR/MEM operands only (xFENCE, PREFETCH, CLFLUSH,
CRC, and etc.)
* SSE4A insns.
* MMX insns.
* x87 insns added by SSE.
2 test cases are modified:
- test/CodeGen/X86/fast-isel-x86-64.ll
AVX code generation is different from SSE one. 'vcvtsi2sdq' cannot be
selected by fast-isel due to complicated pattern and fast-isel
fallback to materialize it from constant pool.
- test/CodeGen/X86/widen_load-1.ll
AVX code generation is different from SSE one after fixing SSE/AVX
inter-mixing. Exec-domain fixing prefers 'vmovapd' instead of
'vmovaps'.
llvm-svn: 162919
2012-08-31 00:54:46 +08:00
|
|
|
def MMX_MOVFR642Qrr: MMXSDIi8<0xD6, MRMSrcReg, (outs VR64:$dst),
|
|
|
|
(ins FR64:$src), "movdq2q\t{$src, $dst|$dst, $src}",
|
2018-04-12 18:49:57 +08:00
|
|
|
[]>;
|
2013-10-09 12:54:21 +08:00
|
|
|
}
|
2013-03-27 02:24:20 +08:00
|
|
|
} // SchedRW
|
2010-04-24 03:03:32 +08:00
|
|
|
|
2018-06-05 14:20:06 +08:00
|
|
|
let Predicates = [HasMMX, HasSSE1] in
|
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 09:14:50 +08:00
|
|
|
def MMX_MOVNTQmr : MMXI<0xE7, MRMDestMem, (outs), (ins i64mem:$dst, VR64:$src),
|
2007-08-01 04:11:57 +08:00
|
|
|
"movntq\t{$src, $dst|$dst, $src}",
|
2018-04-12 18:49:57 +08:00
|
|
|
[(int_x86_mmx_movnt_dq addr:$dst, VR64:$src)]>,
|
2018-05-15 02:37:19 +08:00
|
|
|
Sched<[SchedWriteVecMoveLSNT.MMX.MR]>;
|
2007-04-04 07:48:32 +08:00
|
|
|
|
2013-10-09 12:54:21 +08:00
|
|
|
let Predicates = [HasMMX] in {
|
|
|
|
// movd to MMX register zero-extends
|
|
|
|
def : Pat<(x86mmx (X86vzmovl (x86mmx (scalar_to_vector GR32:$src)))),
|
|
|
|
(MMX_MOVD64rr GR32:$src)>;
|
|
|
|
def : Pat<(x86mmx (X86vzmovl (x86mmx (scalar_to_vector (loadi32 addr:$src))))),
|
|
|
|
(MMX_MOVD64rm addr:$src)>;
|
|
|
|
}
|
2007-04-04 07:48:32 +08:00
|
|
|
|
2007-03-09 06:09:11 +08:00
|
|
|
// Arithmetic Instructions
|
2012-05-11 22:27:12 +08:00
|
|
|
defm MMX_PABSB : SS3I_unop_rm_int_mm<0x1C, "pabsb", int_x86_ssse3_pabs_b,
|
2018-05-03 17:11:32 +08:00
|
|
|
SchedWriteVecALU.MMX>;
|
2012-05-11 22:27:12 +08:00
|
|
|
defm MMX_PABSW : SS3I_unop_rm_int_mm<0x1D, "pabsw", int_x86_ssse3_pabs_w,
|
2018-05-03 17:11:32 +08:00
|
|
|
SchedWriteVecALU.MMX>;
|
2012-05-11 22:27:12 +08:00
|
|
|
defm MMX_PABSD : SS3I_unop_rm_int_mm<0x1E, "pabsd", int_x86_ssse3_pabs_d,
|
2018-05-03 17:11:32 +08:00
|
|
|
SchedWriteVecALU.MMX>;
|
2007-03-28 05:20:36 +08:00
|
|
|
// -- Addition
|
2012-05-11 22:27:12 +08:00
|
|
|
defm MMX_PADDB : MMXI_binop_rm_int<0xFC, "paddb", int_x86_mmx_padd_b,
|
2018-05-03 17:11:32 +08:00
|
|
|
SchedWriteVecALU.MMX, 1>;
|
2012-05-11 22:27:12 +08:00
|
|
|
defm MMX_PADDW : MMXI_binop_rm_int<0xFD, "paddw", int_x86_mmx_padd_w,
|
2018-05-03 17:11:32 +08:00
|
|
|
SchedWriteVecALU.MMX, 1>;
|
2012-05-11 22:27:12 +08:00
|
|
|
defm MMX_PADDD : MMXI_binop_rm_int<0xFE, "paddd", int_x86_mmx_padd_d,
|
2018-05-03 17:11:32 +08:00
|
|
|
SchedWriteVecALU.MMX, 1>;
|
2018-06-05 14:20:06 +08:00
|
|
|
let Predicates = [HasMMX, HasSSE2] in
|
2012-05-11 22:27:12 +08:00
|
|
|
defm MMX_PADDQ : MMXI_binop_rm_int<0xD4, "paddq", int_x86_mmx_padd_q,
|
2018-05-03 17:11:32 +08:00
|
|
|
SchedWriteVecALU.MMX, 1>;
|
2012-05-11 22:27:12 +08:00
|
|
|
defm MMX_PADDSB : MMXI_binop_rm_int<0xEC, "paddsb" , int_x86_mmx_padds_b,
|
2018-05-03 17:11:32 +08:00
|
|
|
SchedWriteVecALU.MMX, 1>;
|
2012-05-11 22:27:12 +08:00
|
|
|
defm MMX_PADDSW : MMXI_binop_rm_int<0xED, "paddsw" , int_x86_mmx_padds_w,
|
2018-05-03 17:11:32 +08:00
|
|
|
SchedWriteVecALU.MMX, 1>;
|
2012-05-11 22:27:12 +08:00
|
|
|
|
|
|
|
defm MMX_PADDUSB : MMXI_binop_rm_int<0xDC, "paddusb", int_x86_mmx_paddus_b,
|
2018-05-03 17:11:32 +08:00
|
|
|
SchedWriteVecALU.MMX, 1>;
|
2012-05-11 22:27:12 +08:00
|
|
|
defm MMX_PADDUSW : MMXI_binop_rm_int<0xDD, "paddusw", int_x86_mmx_paddus_w,
|
2018-05-03 17:11:32 +08:00
|
|
|
SchedWriteVecALU.MMX, 1>;
|
2012-05-11 22:27:12 +08:00
|
|
|
|
|
|
|
defm MMX_PHADDW : SS3I_binop_rm_int_mm<0x01, "phaddw", int_x86_ssse3_phadd_w,
|
2018-05-03 17:11:32 +08:00
|
|
|
SchedWritePHAdd.MMX>;
|
2018-01-25 12:45:32 +08:00
|
|
|
defm MMX_PHADDD : SS3I_binop_rm_int_mm<0x02, "phaddd", int_x86_ssse3_phadd_d,
|
2018-05-03 17:11:32 +08:00
|
|
|
SchedWritePHAdd.MMX>;
|
2012-05-11 22:27:12 +08:00
|
|
|
defm MMX_PHADDSW : SS3I_binop_rm_int_mm<0x03, "phaddsw",int_x86_ssse3_phadd_sw,
|
2018-05-03 17:11:32 +08:00
|
|
|
SchedWritePHAdd.MMX>;
|
2010-09-09 09:02:39 +08:00
|
|
|
|
2007-03-28 05:20:36 +08:00
|
|
|
// -- Subtraction
|
2012-05-11 22:27:12 +08:00
|
|
|
defm MMX_PSUBB : MMXI_binop_rm_int<0xF8, "psubb", int_x86_mmx_psub_b,
|
2018-05-03 17:11:32 +08:00
|
|
|
SchedWriteVecALU.MMX>;
|
2012-05-11 22:27:12 +08:00
|
|
|
defm MMX_PSUBW : MMXI_binop_rm_int<0xF9, "psubw", int_x86_mmx_psub_w,
|
2018-05-03 17:11:32 +08:00
|
|
|
SchedWriteVecALU.MMX>;
|
2012-05-11 22:27:12 +08:00
|
|
|
defm MMX_PSUBD : MMXI_binop_rm_int<0xFA, "psubd", int_x86_mmx_psub_d,
|
2018-05-03 17:11:32 +08:00
|
|
|
SchedWriteVecALU.MMX>;
|
2018-06-05 14:20:06 +08:00
|
|
|
let Predicates = [HasMMX, HasSSE2] in
|
2012-05-11 22:27:12 +08:00
|
|
|
defm MMX_PSUBQ : MMXI_binop_rm_int<0xFB, "psubq", int_x86_mmx_psub_q,
|
2018-05-03 17:11:32 +08:00
|
|
|
SchedWriteVecALU.MMX>;
|
2012-05-11 22:27:12 +08:00
|
|
|
|
|
|
|
defm MMX_PSUBSB : MMXI_binop_rm_int<0xE8, "psubsb" , int_x86_mmx_psubs_b,
|
2018-05-03 17:11:32 +08:00
|
|
|
SchedWriteVecALU.MMX>;
|
2012-05-11 22:27:12 +08:00
|
|
|
defm MMX_PSUBSW : MMXI_binop_rm_int<0xE9, "psubsw" , int_x86_mmx_psubs_w,
|
2018-05-03 17:11:32 +08:00
|
|
|
SchedWriteVecALU.MMX>;
|
2012-05-11 22:27:12 +08:00
|
|
|
|
|
|
|
defm MMX_PSUBUSB : MMXI_binop_rm_int<0xD8, "psubusb", int_x86_mmx_psubus_b,
|
2018-05-03 17:11:32 +08:00
|
|
|
SchedWriteVecALU.MMX>;
|
2012-05-11 22:27:12 +08:00
|
|
|
defm MMX_PSUBUSW : MMXI_binop_rm_int<0xD9, "psubusw", int_x86_mmx_psubus_w,
|
2018-05-03 17:11:32 +08:00
|
|
|
SchedWriteVecALU.MMX>;
|
2012-05-11 22:27:12 +08:00
|
|
|
|
|
|
|
defm MMX_PHSUBW : SS3I_binop_rm_int_mm<0x05, "phsubw", int_x86_ssse3_phsub_w,
|
2018-05-03 17:11:32 +08:00
|
|
|
SchedWritePHAdd.MMX>;
|
2012-05-11 22:27:12 +08:00
|
|
|
defm MMX_PHSUBD : SS3I_binop_rm_int_mm<0x06, "phsubd", int_x86_ssse3_phsub_d,
|
2018-05-03 17:11:32 +08:00
|
|
|
SchedWritePHAdd.MMX>;
|
2012-05-11 22:27:12 +08:00
|
|
|
defm MMX_PHSUBSW : SS3I_binop_rm_int_mm<0x07, "phsubsw",int_x86_ssse3_phsub_sw,
|
2018-05-03 17:11:32 +08:00
|
|
|
SchedWritePHAdd.MMX>;
|
2010-09-09 09:02:39 +08:00
|
|
|
|
2007-03-28 05:20:36 +08:00
|
|
|
// -- Multiplication
|
2012-05-11 22:27:12 +08:00
|
|
|
defm MMX_PMULLW : MMXI_binop_rm_int<0xD5, "pmullw", int_x86_mmx_pmull_w,
|
2018-05-03 17:11:32 +08:00
|
|
|
SchedWriteVecIMul.MMX, 1>;
|
2012-05-11 22:27:12 +08:00
|
|
|
|
|
|
|
defm MMX_PMULHW : MMXI_binop_rm_int<0xE5, "pmulhw", int_x86_mmx_pmulh_w,
|
2018-05-03 17:11:32 +08:00
|
|
|
SchedWriteVecIMul.MMX, 1>;
|
2018-06-05 14:20:06 +08:00
|
|
|
let Predicates = [HasMMX, HasSSE1] in
|
2012-05-11 22:27:12 +08:00
|
|
|
defm MMX_PMULHUW : MMXI_binop_rm_int<0xE4, "pmulhuw", int_x86_mmx_pmulhu_w,
|
2018-05-03 17:11:32 +08:00
|
|
|
SchedWriteVecIMul.MMX, 1>;
|
2018-06-05 14:20:06 +08:00
|
|
|
let Predicates = [HasMMX, HasSSE2] in
|
2012-05-11 22:27:12 +08:00
|
|
|
defm MMX_PMULUDQ : MMXI_binop_rm_int<0xF4, "pmuludq", int_x86_mmx_pmulu_dq,
|
2018-05-03 17:11:32 +08:00
|
|
|
SchedWriteVecIMul.MMX, 1>;
|
2010-10-01 07:57:10 +08:00
|
|
|
defm MMX_PMULHRSW : SS3I_binop_rm_int_mm<0x0B, "pmulhrsw",
|
2016-07-26 16:06:18 +08:00
|
|
|
int_x86_ssse3_pmul_hr_sw,
|
2018-05-03 17:11:32 +08:00
|
|
|
SchedWriteVecIMul.MMX, 1>;
|
2007-04-04 07:48:32 +08:00
|
|
|
|
|
|
|
// -- Miscellanea
|
2012-05-11 22:27:12 +08:00
|
|
|
defm MMX_PMADDWD : MMXI_binop_rm_int<0xF5, "pmaddwd", int_x86_mmx_pmadd_wd,
|
2018-05-03 17:11:32 +08:00
|
|
|
SchedWriteVecIMul.MMX, 1>;
|
2007-03-23 02:42:45 +08:00
|
|
|
|
2010-10-01 07:57:10 +08:00
|
|
|
defm MMX_PMADDUBSW : SS3I_binop_rm_int_mm<0x04, "pmaddubsw",
|
2018-05-03 17:11:32 +08:00
|
|
|
int_x86_ssse3_pmadd_ub_sw,
|
|
|
|
SchedWriteVecIMul.MMX>;
|
2018-06-05 14:20:06 +08:00
|
|
|
let Predicates = [HasMMX, HasSSE1] in {
|
2012-05-11 22:27:12 +08:00
|
|
|
defm MMX_PAVGB : MMXI_binop_rm_int<0xE0, "pavgb", int_x86_mmx_pavg_b,
|
2018-05-03 17:11:32 +08:00
|
|
|
SchedWriteVecALU.MMX, 1>;
|
2012-05-11 22:27:12 +08:00
|
|
|
defm MMX_PAVGW : MMXI_binop_rm_int<0xE3, "pavgw", int_x86_mmx_pavg_w,
|
2018-05-03 17:11:32 +08:00
|
|
|
SchedWriteVecALU.MMX, 1>;
|
2012-05-11 22:27:12 +08:00
|
|
|
|
|
|
|
defm MMX_PMINUB : MMXI_binop_rm_int<0xDA, "pminub", int_x86_mmx_pminu_b,
|
2018-05-03 17:11:32 +08:00
|
|
|
SchedWriteVecALU.MMX, 1>;
|
2012-05-11 22:27:12 +08:00
|
|
|
defm MMX_PMINSW : MMXI_binop_rm_int<0xEA, "pminsw", int_x86_mmx_pmins_w,
|
2018-05-03 17:11:32 +08:00
|
|
|
SchedWriteVecALU.MMX, 1>;
|
2012-05-11 22:27:12 +08:00
|
|
|
|
|
|
|
defm MMX_PMAXUB : MMXI_binop_rm_int<0xDE, "pmaxub", int_x86_mmx_pmaxu_b,
|
2018-05-03 17:11:32 +08:00
|
|
|
SchedWriteVecALU.MMX, 1>;
|
2012-05-11 22:27:12 +08:00
|
|
|
defm MMX_PMAXSW : MMXI_binop_rm_int<0xEE, "pmaxsw", int_x86_mmx_pmaxs_w,
|
2018-05-03 17:11:32 +08:00
|
|
|
SchedWriteVecALU.MMX, 1>;
|
2012-05-11 22:27:12 +08:00
|
|
|
|
|
|
|
defm MMX_PSADBW : MMXI_binop_rm_int<0xF6, "psadbw", int_x86_mmx_psad_bw,
|
2018-05-03 17:11:32 +08:00
|
|
|
SchedWritePSADBW.MMX, 1>;
|
2015-11-11 15:29:25 +08:00
|
|
|
}
|
2012-05-11 22:27:12 +08:00
|
|
|
|
|
|
|
defm MMX_PSIGNB : SS3I_binop_rm_int_mm<0x08, "psignb", int_x86_ssse3_psign_b,
|
2018-05-03 17:11:32 +08:00
|
|
|
SchedWriteVecALU.MMX>;
|
2012-05-11 22:27:12 +08:00
|
|
|
defm MMX_PSIGNW : SS3I_binop_rm_int_mm<0x09, "psignw", int_x86_ssse3_psign_w,
|
2018-05-03 17:11:32 +08:00
|
|
|
SchedWriteVecALU.MMX>;
|
2012-05-11 22:27:12 +08:00
|
|
|
defm MMX_PSIGND : SS3I_binop_rm_int_mm<0x0A, "psignd", int_x86_ssse3_psign_d,
|
2018-05-03 17:11:32 +08:00
|
|
|
SchedWriteVecALU.MMX>;
|
2010-09-09 09:02:39 +08:00
|
|
|
let Constraints = "$src1 = $dst" in
|
2018-05-03 17:11:32 +08:00
|
|
|
defm MMX_PALIGNR : ssse3_palign_mm<"palignr", int_x86_mmx_palignr_b,
|
|
|
|
SchedWriteShuffle.MMX>;
|
2010-09-09 09:02:39 +08:00
|
|
|
|
2007-03-16 17:44:46 +08:00
|
|
|
// Logical Instructions
|
2012-05-11 22:27:12 +08:00
|
|
|
defm MMX_PAND : MMXI_binop_rm_int<0xDB, "pand", int_x86_mmx_pand,
|
2018-05-03 17:11:32 +08:00
|
|
|
SchedWriteVecLogic.MMX, 1>;
|
2012-05-11 22:27:12 +08:00
|
|
|
defm MMX_POR : MMXI_binop_rm_int<0xEB, "por" , int_x86_mmx_por,
|
2018-05-03 17:11:32 +08:00
|
|
|
SchedWriteVecLogic.MMX, 1>;
|
2012-05-11 22:27:12 +08:00
|
|
|
defm MMX_PXOR : MMXI_binop_rm_int<0xEF, "pxor", int_x86_mmx_pxor,
|
2018-05-03 17:11:32 +08:00
|
|
|
SchedWriteVecLogic.MMX, 1>;
|
2012-05-11 22:27:12 +08:00
|
|
|
defm MMX_PANDN : MMXI_binop_rm_int<0xDF, "pandn", int_x86_mmx_pandn,
|
2018-05-03 17:11:32 +08:00
|
|
|
SchedWriteVecLogic.MMX>;
|
2007-03-16 17:44:46 +08:00
|
|
|
|
2007-03-23 02:42:45 +08:00
|
|
|
// Shift Instructions
|
|
|
|
defm MMX_PSRLW : MMXI_binop_rmi_int<0xD1, 0x71, MRM2r, "psrlw",
|
2012-05-11 22:27:12 +08:00
|
|
|
int_x86_mmx_psrl_w, int_x86_mmx_psrli_w,
|
2018-05-04 01:56:43 +08:00
|
|
|
SchedWriteVecShift.MMX,
|
|
|
|
SchedWriteVecShiftImm.MMX>;
|
2007-03-23 02:42:45 +08:00
|
|
|
defm MMX_PSRLD : MMXI_binop_rmi_int<0xD2, 0x72, MRM2r, "psrld",
|
2012-05-11 22:27:12 +08:00
|
|
|
int_x86_mmx_psrl_d, int_x86_mmx_psrli_d,
|
2018-05-04 01:56:43 +08:00
|
|
|
SchedWriteVecShift.MMX,
|
|
|
|
SchedWriteVecShiftImm.MMX>;
|
2007-03-23 02:42:45 +08:00
|
|
|
defm MMX_PSRLQ : MMXI_binop_rmi_int<0xD3, 0x73, MRM2r, "psrlq",
|
2012-05-11 22:27:12 +08:00
|
|
|
int_x86_mmx_psrl_q, int_x86_mmx_psrli_q,
|
2018-05-04 01:56:43 +08:00
|
|
|
SchedWriteVecShift.MMX,
|
|
|
|
SchedWriteVecShiftImm.MMX>;
|
2007-03-23 02:42:45 +08:00
|
|
|
|
|
|
|
defm MMX_PSLLW : MMXI_binop_rmi_int<0xF1, 0x71, MRM6r, "psllw",
|
2012-05-11 22:27:12 +08:00
|
|
|
int_x86_mmx_psll_w, int_x86_mmx_pslli_w,
|
2018-05-04 01:56:43 +08:00
|
|
|
SchedWriteVecShift.MMX,
|
|
|
|
SchedWriteVecShiftImm.MMX>;
|
2007-03-23 02:42:45 +08:00
|
|
|
defm MMX_PSLLD : MMXI_binop_rmi_int<0xF2, 0x72, MRM6r, "pslld",
|
2012-05-11 22:27:12 +08:00
|
|
|
int_x86_mmx_psll_d, int_x86_mmx_pslli_d,
|
2018-05-04 01:56:43 +08:00
|
|
|
SchedWriteVecShift.MMX,
|
|
|
|
SchedWriteVecShiftImm.MMX>;
|
2007-03-23 02:42:45 +08:00
|
|
|
defm MMX_PSLLQ : MMXI_binop_rmi_int<0xF3, 0x73, MRM6r, "psllq",
|
2012-05-11 22:27:12 +08:00
|
|
|
int_x86_mmx_psll_q, int_x86_mmx_pslli_q,
|
2018-05-04 01:56:43 +08:00
|
|
|
SchedWriteVecShift.MMX,
|
|
|
|
SchedWriteVecShiftImm.MMX>;
|
2007-03-23 02:42:45 +08:00
|
|
|
|
|
|
|
defm MMX_PSRAW : MMXI_binop_rmi_int<0xE1, 0x71, MRM4r, "psraw",
|
2012-05-11 22:27:12 +08:00
|
|
|
int_x86_mmx_psra_w, int_x86_mmx_psrai_w,
|
2018-05-04 01:56:43 +08:00
|
|
|
SchedWriteVecShift.MMX,
|
|
|
|
SchedWriteVecShiftImm.MMX>;
|
2007-03-23 02:42:45 +08:00
|
|
|
defm MMX_PSRAD : MMXI_binop_rmi_int<0xE2, 0x72, MRM4r, "psrad",
|
2012-05-11 22:27:12 +08:00
|
|
|
int_x86_mmx_psra_d, int_x86_mmx_psrai_d,
|
2018-05-04 01:56:43 +08:00
|
|
|
SchedWriteVecShift.MMX,
|
|
|
|
SchedWriteVecShiftImm.MMX>;
|
2007-03-23 02:42:45 +08:00
|
|
|
|
2007-03-28 05:20:36 +08:00
|
|
|
// Comparison Instructions
|
2012-05-11 22:27:12 +08:00
|
|
|
defm MMX_PCMPEQB : MMXI_binop_rm_int<0x74, "pcmpeqb", int_x86_mmx_pcmpeq_b,
|
2018-05-03 17:11:32 +08:00
|
|
|
SchedWriteVecALU.MMX>;
|
2012-05-11 22:27:12 +08:00
|
|
|
defm MMX_PCMPEQW : MMXI_binop_rm_int<0x75, "pcmpeqw", int_x86_mmx_pcmpeq_w,
|
2018-05-03 17:11:32 +08:00
|
|
|
SchedWriteVecALU.MMX>;
|
2012-05-11 22:27:12 +08:00
|
|
|
defm MMX_PCMPEQD : MMXI_binop_rm_int<0x76, "pcmpeqd", int_x86_mmx_pcmpeq_d,
|
2018-05-03 17:11:32 +08:00
|
|
|
SchedWriteVecALU.MMX>;
|
2012-05-11 22:27:12 +08:00
|
|
|
|
|
|
|
defm MMX_PCMPGTB : MMXI_binop_rm_int<0x64, "pcmpgtb", int_x86_mmx_pcmpgt_b,
|
2018-05-03 17:11:32 +08:00
|
|
|
SchedWriteVecALU.MMX>;
|
2012-05-11 22:27:12 +08:00
|
|
|
defm MMX_PCMPGTW : MMXI_binop_rm_int<0x65, "pcmpgtw", int_x86_mmx_pcmpgt_w,
|
2018-05-03 17:11:32 +08:00
|
|
|
SchedWriteVecALU.MMX>;
|
2012-05-11 22:27:12 +08:00
|
|
|
defm MMX_PCMPGTD : MMXI_binop_rm_int<0x66, "pcmpgtd", int_x86_mmx_pcmpgt_d,
|
2018-05-03 17:11:32 +08:00
|
|
|
SchedWriteVecALU.MMX>;
|
2007-03-28 04:22:40 +08:00
|
|
|
|
2007-03-28 05:20:36 +08:00
|
|
|
// -- Unpack Instructions
|
2014-12-04 13:20:33 +08:00
|
|
|
defm MMX_PUNPCKHBW : MMXI_binop_rm_int<0x68, "punpckhbw",
|
2012-05-11 22:27:12 +08:00
|
|
|
int_x86_mmx_punpckhbw,
|
2018-05-03 17:11:32 +08:00
|
|
|
SchedWriteShuffle.MMX>;
|
2014-12-04 13:20:33 +08:00
|
|
|
defm MMX_PUNPCKHWD : MMXI_binop_rm_int<0x69, "punpckhwd",
|
2012-05-11 22:27:12 +08:00
|
|
|
int_x86_mmx_punpckhwd,
|
2018-05-03 17:11:32 +08:00
|
|
|
SchedWriteShuffle.MMX>;
|
2014-12-04 13:20:33 +08:00
|
|
|
defm MMX_PUNPCKHDQ : MMXI_binop_rm_int<0x6A, "punpckhdq",
|
2012-05-11 22:27:12 +08:00
|
|
|
int_x86_mmx_punpckhdq,
|
2018-05-03 17:11:32 +08:00
|
|
|
SchedWriteShuffle.MMX>;
|
2014-12-04 13:20:33 +08:00
|
|
|
defm MMX_PUNPCKLBW : MMXI_binop_rm_int<0x60, "punpcklbw",
|
2012-05-11 22:27:12 +08:00
|
|
|
int_x86_mmx_punpcklbw,
|
2018-05-03 17:11:32 +08:00
|
|
|
SchedWriteShuffle.MMX,
|
2017-12-29 16:31:01 +08:00
|
|
|
0, i32mem>;
|
2014-12-04 13:20:33 +08:00
|
|
|
defm MMX_PUNPCKLWD : MMXI_binop_rm_int<0x61, "punpcklwd",
|
2012-05-11 22:27:12 +08:00
|
|
|
int_x86_mmx_punpcklwd,
|
2018-05-03 17:11:32 +08:00
|
|
|
SchedWriteShuffle.MMX,
|
2017-12-29 16:31:01 +08:00
|
|
|
0, i32mem>;
|
2010-09-09 04:54:00 +08:00
|
|
|
defm MMX_PUNPCKLDQ : MMXI_binop_rm_int<0x62, "punpckldq",
|
2012-05-11 22:27:12 +08:00
|
|
|
int_x86_mmx_punpckldq,
|
2018-05-03 17:11:32 +08:00
|
|
|
SchedWriteShuffle.MMX,
|
2017-12-29 16:31:01 +08:00
|
|
|
0, i32mem>;
|
2007-03-28 05:20:36 +08:00
|
|
|
|
|
|
|
// -- Pack Instructions
|
2012-05-11 22:27:12 +08:00
|
|
|
defm MMX_PACKSSWB : MMXI_binop_rm_int<0x63, "packsswb", int_x86_mmx_packsswb,
|
2018-05-03 17:11:32 +08:00
|
|
|
SchedWriteShuffle.MMX>;
|
2012-05-11 22:27:12 +08:00
|
|
|
defm MMX_PACKSSDW : MMXI_binop_rm_int<0x6B, "packssdw", int_x86_mmx_packssdw,
|
2018-05-03 17:11:32 +08:00
|
|
|
SchedWriteShuffle.MMX>;
|
2012-05-11 22:27:12 +08:00
|
|
|
defm MMX_PACKUSWB : MMXI_binop_rm_int<0x67, "packuswb", int_x86_mmx_packuswb,
|
2018-05-03 17:11:32 +08:00
|
|
|
SchedWriteShuffle.MMX>;
|
2007-03-28 05:20:36 +08:00
|
|
|
|
2007-04-25 05:18:37 +08:00
|
|
|
// -- Shuffle Instructions
|
2012-05-11 22:27:12 +08:00
|
|
|
defm MMX_PSHUFB : SS3I_binop_rm_int_mm<0x00, "pshufb", int_x86_ssse3_pshuf_b,
|
2018-05-03 17:11:32 +08:00
|
|
|
SchedWriteVarShuffle.MMX>;
|
2010-09-09 09:02:39 +08:00
|
|
|
|
2010-10-03 05:32:15 +08:00
|
|
|
def MMX_PSHUFWri : MMXIi8<0x70, MRMSrcReg,
|
2015-01-21 16:43:49 +08:00
|
|
|
(outs VR64:$dst), (ins VR64:$src1, u8imm:$src2),
|
2010-10-03 05:32:15 +08:00
|
|
|
"pshufw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
|
|
|
|
[(set VR64:$dst,
|
2019-09-20 00:26:14 +08:00
|
|
|
(int_x86_sse_pshuf_w VR64:$src1, timm:$src2))]>,
|
2018-05-03 17:11:32 +08:00
|
|
|
Sched<[SchedWriteShuffle.MMX]>;
|
2010-10-03 05:32:15 +08:00
|
|
|
def MMX_PSHUFWmi : MMXIi8<0x70, MRMSrcMem,
|
2015-01-21 16:43:49 +08:00
|
|
|
(outs VR64:$dst), (ins i64mem:$src1, u8imm:$src2),
|
2010-10-03 05:32:15 +08:00
|
|
|
"pshufw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
|
|
|
|
[(set VR64:$dst,
|
2010-10-05 04:24:01 +08:00
|
|
|
(int_x86_sse_pshuf_w (load_mmx addr:$src1),
|
2019-09-20 00:26:14 +08:00
|
|
|
timm:$src2))]>,
|
2018-05-03 17:11:32 +08:00
|
|
|
Sched<[SchedWriteShuffle.MMX.Folded]>;
|
2010-10-03 05:32:15 +08:00
|
|
|
|
2007-04-04 07:48:32 +08:00
|
|
|
// -- Conversion Instructions
|
2010-09-10 01:13:07 +08:00
|
|
|
defm MMX_CVTPS2PI : sse12_cvt_pint<0x2D, VR128, VR64, int_x86_sse_cvtps2pi,
|
|
|
|
f64mem, load, "cvtps2pi\t{$src, $dst|$dst, $src}",
|
2019-11-02 12:18:09 +08:00
|
|
|
WriteCvtPS2I, SSEPackedSingle>, PS, SIMD_EXC;
|
2010-09-10 01:13:07 +08:00
|
|
|
defm MMX_CVTPD2PI : sse12_cvt_pint<0x2D, VR128, VR64, int_x86_sse_cvtpd2pi,
|
|
|
|
f128mem, memop, "cvtpd2pi\t{$src, $dst|$dst, $src}",
|
2019-11-02 12:18:09 +08:00
|
|
|
WriteCvtPD2I, SSEPackedDouble>, PD, SIMD_EXC;
|
2010-09-10 01:13:07 +08:00
|
|
|
defm MMX_CVTTPS2PI : sse12_cvt_pint<0x2C, VR128, VR64, int_x86_sse_cvttps2pi,
|
|
|
|
f64mem, load, "cvttps2pi\t{$src, $dst|$dst, $src}",
|
2019-11-02 12:18:09 +08:00
|
|
|
WriteCvtPS2I, SSEPackedSingle>, PS, SIMD_EXC;
|
2010-09-10 01:13:07 +08:00
|
|
|
defm MMX_CVTTPD2PI : sse12_cvt_pint<0x2C, VR128, VR64, int_x86_sse_cvttpd2pi,
|
|
|
|
f128mem, memop, "cvttpd2pi\t{$src, $dst|$dst, $src}",
|
2019-11-02 12:18:09 +08:00
|
|
|
WriteCvtPD2I, SSEPackedDouble>, PD, SIMD_EXC;
|
2010-09-10 01:13:07 +08:00
|
|
|
defm MMX_CVTPI2PD : sse12_cvt_pint<0x2A, VR64, VR128, int_x86_sse_cvtpi2pd,
|
|
|
|
i64mem, load, "cvtpi2pd\t{$src, $dst|$dst, $src}",
|
2018-05-16 18:53:45 +08:00
|
|
|
WriteCvtI2PD, SSEPackedDouble>, PD;
|
2010-09-09 03:15:38 +08:00
|
|
|
let Constraints = "$src1 = $dst" in {
|
2010-09-10 01:13:07 +08:00
|
|
|
defm MMX_CVTPI2PS : sse12_cvt_pint_3addr<0x2A, VR64, VR128,
|
|
|
|
int_x86_sse_cvtpi2ps,
|
|
|
|
i64mem, load, "cvtpi2ps\t{$src2, $dst|$dst, $src2}",
|
2019-11-02 12:18:09 +08:00
|
|
|
SSEPackedSingle>, PS, SIMD_EXC;
|
2010-09-09 03:15:38 +08:00
|
|
|
}
|
2006-04-11 14:57:30 +08:00
|
|
|
|
2007-04-04 07:48:32 +08:00
|
|
|
// Extract / Insert
|
2018-06-05 14:20:06 +08:00
|
|
|
let Predicates = [HasMMX, HasSSE1] in
|
2018-01-25 01:58:51 +08:00
|
|
|
def MMX_PEXTRWrr: MMXIi8<0xC5, MRMSrcReg,
|
|
|
|
(outs GR32orGR64:$dst), (ins VR64:$src1, i32u8imm:$src2),
|
|
|
|
"pextrw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
|
|
|
|
[(set GR32orGR64:$dst, (int_x86_mmx_pextr_w VR64:$src1,
|
2019-09-20 14:00:35 +08:00
|
|
|
timm:$src2))]>,
|
2018-04-24 21:21:41 +08:00
|
|
|
Sched<[WriteVecExtract]>;
|
2009-08-11 06:37:37 +08:00
|
|
|
let Constraints = "$src1 = $dst" in {
|
2018-06-05 14:20:06 +08:00
|
|
|
let Predicates = [HasMMX, HasSSE1] in {
|
2018-01-25 01:58:51 +08:00
|
|
|
def MMX_PINSRWrr : MMXIi8<0xC4, MRMSrcReg,
|
|
|
|
(outs VR64:$dst),
|
|
|
|
(ins VR64:$src1, GR32orGR64:$src2, i32u8imm:$src3),
|
|
|
|
"pinsrw\t{$src3, $src2, $dst|$dst, $src2, $src3}",
|
|
|
|
[(set VR64:$dst, (int_x86_mmx_pinsr_w VR64:$src1,
|
2019-09-20 14:00:35 +08:00
|
|
|
GR32orGR64:$src2, timm:$src3))]>,
|
2019-01-24 00:35:07 +08:00
|
|
|
Sched<[WriteVecInsert, ReadDefault, ReadInt2Fpu]>;
|
2018-01-25 01:58:51 +08:00
|
|
|
|
|
|
|
def MMX_PINSRWrm : MMXIi8<0xC4, MRMSrcMem,
|
|
|
|
(outs VR64:$dst),
|
|
|
|
(ins VR64:$src1, i16mem:$src2, i32u8imm:$src3),
|
|
|
|
"pinsrw\t{$src3, $src2, $dst|$dst, $src2, $src3}",
|
|
|
|
[(set VR64:$dst, (int_x86_mmx_pinsr_w VR64:$src1,
|
|
|
|
(i32 (anyext (loadi16 addr:$src2))),
|
2019-09-20 14:00:35 +08:00
|
|
|
timm:$src3))]>,
|
2018-10-06 01:57:29 +08:00
|
|
|
Sched<[WriteVecInsert.Folded, WriteVecInsert.ReadAfterFold]>;
|
2007-04-04 07:48:32 +08:00
|
|
|
}
|
2015-11-11 15:29:25 +08:00
|
|
|
}
|
2006-04-11 14:57:30 +08:00
|
|
|
|
2010-10-01 07:57:10 +08:00
|
|
|
// Mask creation
|
2018-06-05 14:20:06 +08:00
|
|
|
let Predicates = [HasMMX, HasSSE1] in
|
2013-10-14 12:55:01 +08:00
|
|
|
def MMX_PMOVMSKBrr : MMXI<0xD7, MRMSrcReg, (outs GR32orGR64:$dst),
|
|
|
|
(ins VR64:$src),
|
2010-10-01 07:57:10 +08:00
|
|
|
"pmovmskb\t{$src, $dst|$dst, $src}",
|
2013-10-14 12:55:01 +08:00
|
|
|
[(set GR32orGR64:$dst,
|
2018-04-12 18:49:57 +08:00
|
|
|
(int_x86_mmx_pmovmskb VR64:$src))]>,
|
|
|
|
Sched<[WriteMMXMOVMSK]>;
|
2010-10-01 07:57:10 +08:00
|
|
|
|
2019-08-16 02:23:37 +08:00
|
|
|
// MMX to XMM for vector types
|
|
|
|
def MMX_X86movq2dq : SDNode<"X86ISD::MOVQ2DQ", SDTypeProfile<1, 1,
|
|
|
|
[SDTCisVT<0, v2i64>, SDTCisVT<1, x86mmx>]>>;
|
|
|
|
|
|
|
|
def : Pat<(v2i64 (MMX_X86movq2dq VR64:$src)),
|
|
|
|
(v2i64 (MMX_MOVQ2DQrr VR64:$src))>;
|
|
|
|
|
2010-10-01 07:57:10 +08:00
|
|
|
// Low word of XMM to MMX.
|
|
|
|
def MMX_X86movdq2q : SDNode<"X86ISD::MOVDQ2Q", SDTypeProfile<1, 1,
|
|
|
|
[SDTCisVT<0, x86mmx>, SDTCisVT<1, v2i64>]>>;
|
|
|
|
|
|
|
|
def : Pat<(x86mmx (MMX_X86movdq2q VR128:$src)),
|
|
|
|
(x86mmx (MMX_MOVDQ2Qrr VR128:$src))>;
|
|
|
|
|
2019-09-13 07:03:39 +08:00
|
|
|
def : Pat<(x86mmx (MMX_X86movdq2q (v2i64 (simple_load addr:$src)))),
|
2010-10-01 07:57:10 +08:00
|
|
|
(x86mmx (MMX_MOVQ64rm addr:$src))>;
|
2007-04-04 07:48:32 +08:00
|
|
|
|
2019-08-15 14:46:30 +08:00
|
|
|
def : Pat<(v2i64 (X86vzmovl (scalar_to_vector
|
|
|
|
(i64 (bitconvert (x86mmx VR64:$src)))))),
|
|
|
|
(MMX_MOVQ2DQrr VR64:$src)>;
|
|
|
|
|
2007-04-04 07:48:32 +08:00
|
|
|
// Misc.
|
2018-05-03 17:11:32 +08:00
|
|
|
let SchedRW = [SchedWriteShuffle.MMX] in {
|
2018-06-05 14:20:06 +08:00
|
|
|
let Uses = [EDI], Predicates = [HasMMX, HasSSE1,Not64BitMode] in
|
2013-10-09 10:18:34 +08:00
|
|
|
def MMX_MASKMOVQ : MMXI32<0xF7, MRMSrcReg, (outs), (ins VR64:$src, VR64:$mask),
|
|
|
|
"maskmovq\t{$mask, $src|$src, $mask}",
|
2018-04-12 18:49:57 +08:00
|
|
|
[(int_x86_mmx_maskmovq VR64:$src, VR64:$mask, EDI)]>;
|
2018-06-05 14:20:06 +08:00
|
|
|
let Uses = [RDI], Predicates = [HasMMX, HasSSE1,In64BitMode] in
|
2009-06-24 03:52:59 +08:00
|
|
|
def MMX_MASKMOVQ64: MMXI64<0xF7, MRMSrcReg, (outs), (ins VR64:$src, VR64:$mask),
|
2008-08-23 23:53:19 +08:00
|
|
|
"maskmovq\t{$mask, $src|$src, $mask}",
|
2018-04-12 18:49:57 +08:00
|
|
|
[(int_x86_mmx_maskmovq VR64:$src, VR64:$mask, RDI)]>;
|
2013-03-27 02:24:20 +08:00
|
|
|
}
|
2007-03-07 02:53:42 +08:00
|
|
|
|
2007-07-04 08:19:54 +08:00
|
|
|
// 64-bit bit convert.
|
2018-06-05 14:20:06 +08:00
|
|
|
let Predicates = [HasMMX, HasSSE2] in {
|
2010-10-01 07:57:10 +08:00
|
|
|
def : Pat<(f64 (bitconvert (x86mmx VR64:$src))),
|
2009-02-23 17:03:22 +08:00
|
|
|
(MMX_MOVQ2FR64rr VR64:$src)>;
|
2010-10-01 07:57:10 +08:00
|
|
|
def : Pat<(x86mmx (bitconvert (f64 FR64:$src))),
|
2010-04-24 03:03:32 +08:00
|
|
|
(MMX_MOVFR642Qrr FR64:$src)>;
|
2017-03-29 05:32:11 +08:00
|
|
|
def : Pat<(x86mmx (MMX_X86movdq2q
|
2018-02-25 02:58:07 +08:00
|
|
|
(bc_v2i64 (v4i32 (X86cvtp2Int (v4f32 VR128:$src)))))),
|
2017-03-29 05:32:11 +08:00
|
|
|
(MMX_CVTPS2PIirr VR128:$src)>;
|
2018-06-14 11:16:58 +08:00
|
|
|
def : Pat<(x86mmx (MMX_X86movdq2q
|
|
|
|
(bc_v2i64 (v4i32 (X86cvttp2si (v4f32 VR128:$src)))))),
|
|
|
|
(MMX_CVTTPS2PIirr VR128:$src)>;
|
2017-03-29 05:32:11 +08:00
|
|
|
def : Pat<(x86mmx (MMX_X86movdq2q
|
|
|
|
(bc_v2i64 (v4i32 (X86cvtp2Int (v2f64 VR128:$src)))))),
|
|
|
|
(MMX_CVTPD2PIirr VR128:$src)>;
|
|
|
|
def : Pat<(x86mmx (MMX_X86movdq2q
|
|
|
|
(bc_v2i64 (v4i32 (X86cvttp2si (v2f64 VR128:$src)))))),
|
|
|
|
(MMX_CVTTPD2PIirr VR128:$src)>;
|
Introduce 'UseSSEx' to force SSE legacy encoding
- Add 'UseSSEx' to force SSE legacy insn not being selected when AVX is
enabled.
As the penalty of inter-mixing SSE and AVX instructions, we need
prevent SSE legacy insn from being generated except explicitly
specified through some intrinsics. For patterns supported by both
SSE and AVX, so far, we force AVX insn will be tried first relying on
AddedComplexity or position in td file. It's error-prone and
introduces bugs accidentally.
'UseSSEx' is disabled when AVX is turned on. For SSE insns inherited
by AVX, we need this predicate to force VEX encoding or SSE legacy
encoding only.
For insns not inherited by AVX, we still use the previous predicates,
i.e. 'HasSSEx'. So far, these insns fall into the following
categories:
* SSE insns with MMX operands
* SSE insns with GPR/MEM operands only (xFENCE, PREFETCH, CLFLUSH,
CRC, and etc.)
* SSE4A insns.
* MMX insns.
* x87 insns added by SSE.
2 test cases are modified:
- test/CodeGen/X86/fast-isel-x86-64.ll
AVX code generation is different from SSE one. 'vcvtsi2sdq' cannot be
selected by fast-isel due to complicated pattern and fast-isel
fallback to materialize it from constant pool.
- test/CodeGen/X86/widen_load-1.ll
AVX code generation is different from SSE one after fixing SSE/AVX
inter-mixing. Exec-domain fixing prefers 'vmovapd' instead of
'vmovaps'.
llvm-svn: 162919
2012-08-31 00:54:46 +08:00
|
|
|
}
|