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llvm-project/llvm/test/CodeGen/ARM/sub.ll

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Improve 64-subtraction of immediates when parts of the immediate can fit in the literal field of an instruction. E.g., long long foo(long long a) { return a - 734439407618LL; } rdar://7038284 llvm-svn: 108339
2010-07-15 01:45:16 +08:00
; RUN: llc -march=arm < %s | FileCheck %s
; 171 = 0x000000ab
define i64 @f1(i64 %a) {
; CHECK: f1
; CHECK: subs r0, r0, #171
; CHECK: sbc r1, r1, #0
%tmp = sub i64 %a, 171
ret i64 %tmp
}
; 66846720 = 0x03fc0000
define i64 @f2(i64 %a) {
; CHECK: f2
Simplify printing of ARM shifted immediates. Print shifted immediate values directly rather than as a payload+shifter value pair. This makes for more readable output assembly code, simplifies the instruction printer, and is consistent with how Thumb immediates are displayed. llvm-svn: 134902
2011-07-12 00:48:36 +08:00
; CHECK: subs r0, r0, #66846720
Improve 64-subtraction of immediates when parts of the immediate can fit in the literal field of an instruction. E.g., long long foo(long long a) { return a - 734439407618LL; } rdar://7038284 llvm-svn: 108339
2010-07-15 01:45:16 +08:00
; CHECK: sbc r1, r1, #0
%tmp = sub i64 %a, 66846720
ret i64 %tmp
}
; 734439407618 = 0x000000ab00000002
define i64 @f3(i64 %a) {
; CHECK: f3
; CHECK: subs r0, r0, #2
; CHECK: sbc r1, r1, #171
%tmp = sub i64 %a, 734439407618
ret i64 %tmp
}
Teach the ARM peephole optimizer that RSB, RSC, ADC, and SBC can be used for folded comparisons, just like ADD and SUB. llvm-svn: 129038
2011-04-07 07:35:59 +08:00
define i32 @f4(i32 %x) {
entry:
; CHECK: f4
; CHECK: rsbs
%sub = sub i32 1, %x
%cmp = icmp ugt i32 %sub, 0
%sel = select i1 %cmp, i32 1, i32 %sub
ret i32 %sel
}
(sub X, imm) gets canonicalized to (add X, -imm) There are patterns to handle immediates when they fit in the immediate field. e.g. %sub = add i32 %x, -123 => sub r0, r0, #123 Add patterns to catch immediates that do not fit but should be materialized with a single movw instruction rather than movw + movt pair. e.g. %sub = add i32 %x, -65535 => movw r1, #65535 sub r0, r0, r1 rdar://11726136 llvm-svn: 159057
2012-06-23 08:29:06 +08:00
; rdar://11726136
define i32 @f5(i32 %x) {
entry:
; CHECK: f5
; CHECK: movw r1, #65535
; CHECK-NOT: movt
; CHECK-NOT: add
; CHECK: sub r0, r0, r1
%sub = add i32 %x, -65535
ret i32 %sub
}