forked from OSchip/llvm-project
137 lines
3.9 KiB
LLVM
137 lines
3.9 KiB
LLVM
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; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
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; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
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; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
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; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
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; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
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; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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@glob = common local_unnamed_addr global i8 0, align 1
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define signext i32 @test_ineuc(i8 zeroext %a, i8 zeroext %b) {
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; CHECK-LABEL: test_ineuc:
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; CHECK: # BB#0: # %entry
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; CHECK-NEXT: xor r3, r3, r4
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; CHECK-NEXT: cntlzw r3, r3
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; CHECK-NEXT: srwi r3, r3, 5
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; CHECK-NEXT: xori r3, r3, 1
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; CHECK-NEXT: blr
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entry:
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%cmp = icmp ne i8 %a, %b
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%conv2 = zext i1 %cmp to i32
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ret i32 %conv2
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}
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define signext i32 @test_ineuc_sext(i8 zeroext %a, i8 zeroext %b) {
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; CHECK-LABEL: test_ineuc_sext:
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; CHECK: # BB#0: # %entry
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; CHECK-NEXT: xor r3, r3, r4
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; CHECK-NEXT: cntlzw r3, r3
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; CHECK-NEXT: srwi r3, r3, 5
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; CHECK-NEXT: xori r3, r3, 1
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; CHECK-NEXT: neg r3, r3
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; CHECK-NEXT: blr
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entry:
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%cmp = icmp ne i8 %a, %b
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%sub = sext i1 %cmp to i32
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ret i32 %sub
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}
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define signext i32 @test_ineuc_z(i8 zeroext %a) {
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; CHECK-LABEL: test_ineuc_z:
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; CHECK: # BB#0: # %entry
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; CHECK-NEXT: cntlzw r3, r3
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; CHECK-NEXT: srwi r3, r3, 5
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; CHECK-NEXT: xori r3, r3, 1
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; CHECK-NEXT: blr
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entry:
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%cmp = icmp ne i8 %a, 0
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%conv1 = zext i1 %cmp to i32
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ret i32 %conv1
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}
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define signext i32 @test_ineuc_sext_z(i8 zeroext %a) {
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; CHECK-LABEL: test_ineuc_sext_z:
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; CHECK: # BB#0: # %entry
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; CHECK-NEXT: cntlzw r3, r3
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; CHECK-NEXT: srwi r3, r3, 5
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; CHECK-NEXT: xori r3, r3, 1
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; CHECK-NEXT: neg r3, r3
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; CHECK-NEXT: blr
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entry:
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%cmp = icmp ne i8 %a, 0
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%sub = sext i1 %cmp to i32
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ret i32 %sub
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}
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define void @test_ineuc_store(i8 zeroext %a, i8 zeroext %b) {
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; CHECK-LABEL: test_ineuc_store:
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; CHECK: # BB#0: # %entry
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; CHECK-NEXT: xor r3, r3, r4
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; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
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; CHECK-NEXT: cntlzw r3, r3
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; CHECK-NEXT: ld r4, .LC0@toc@l(r5)
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; CHECK-NEXT: srwi r3, r3, 5
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; CHECK-NEXT: xori r3, r3, 1
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; CHECK-NEXT: stb r3, 0(r4)
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; CHECK-NEXT: blr
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entry:
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%cmp = icmp ne i8 %a, %b
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%conv3 = zext i1 %cmp to i8
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store i8 %conv3, i8* @glob, align 1
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ret void
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}
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define void @test_ineuc_sext_store(i8 zeroext %a, i8 zeroext %b) {
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; CHECK-LABEL: test_ineuc_sext_store:
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; CHECK: # BB#0: # %entry
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; CHECK-NEXT: xor r3, r3, r4
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; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
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; CHECK-NEXT: cntlzw r3, r3
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; CHECK-NEXT: ld r4, .LC0@toc@l(r5)
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; CHECK-NEXT: srwi r3, r3, 5
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; CHECK-NEXT: xori r3, r3, 1
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; CHECK-NEXT: neg r3, r3
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; CHECK-NEXT: stb r3, 0(r4)
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; CHECK-NEXT: blr
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entry:
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%cmp = icmp ne i8 %a, %b
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%conv3 = sext i1 %cmp to i8
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store i8 %conv3, i8* @glob, align 1
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ret void
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}
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define void @test_ineuc_z_store(i8 zeroext %a) {
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; CHECK-LABEL: test_ineuc_z_store:
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; CHECK: # BB#0: # %entry
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; CHECK-NEXT: addis r4, r2, .LC0@toc@ha
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; CHECK-NEXT: cntlzw r3, r3
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; CHECK-NEXT: ld r4, .LC0@toc@l(r4)
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; CHECK-NEXT: srwi r3, r3, 5
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; CHECK-NEXT: xori r3, r3, 1
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; CHECK-NEXT: stb r3, 0(r4)
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; CHECK-NEXT: blr
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entry:
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%cmp = icmp ne i8 %a, 0
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%conv2 = zext i1 %cmp to i8
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store i8 %conv2, i8* @glob, align 1
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ret void
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}
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define void @test_ineuc_sext_z_store(i8 zeroext %a) {
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; CHECK-LABEL: test_ineuc_sext_z_store:
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; CHECK: # BB#0: # %entry
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; CHECK-NEXT: addis r4, r2, .LC0@toc@ha
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; CHECK-NEXT: cntlzw r3, r3
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; CHECK-NEXT: srwi r3, r3, 5
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; CHECK-NEXT: ld r4, .LC0@toc@l(r4)
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; CHECK-NEXT: xori r3, r3, 1
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; CHECK-NEXT: neg r3, r3
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; CHECK-NEXT: stb r3, 0(r4)
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; CHECK-NEXT: blr
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entry:
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%cmp = icmp ne i8 %a, 0
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%conv2 = sext i1 %cmp to i8
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store i8 %conv2, i8* @glob, align 1
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ret void
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}
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