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llvm-project/llvm/test/CodeGen/AArch64/arm64-2012-01-11-Comparison...

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[AARCH64] Enable AARCH64 lit tests on windows dev machines As discussed on PR27654, this patch fixes the triples of a lot of aarch64 tests and enables lit tests on windows This will hopefully help stop cases where windows developers break the aarch64 target Differential Revision: https://reviews.llvm.org/D22191 llvm-svn: 275973
2016-07-19 21:35:11 +08:00
; RUN: llc < %s -mtriple=arm64-eabi
ARM64: initial backend import This adds a second implementation of the AArch64 architecture to LLVM, accessible in parallel via the "arm64" triple. The plan over the coming weeks & months is to merge the two into a single backend, during which time thorough code review should naturally occur. Everything will be easier with the target in-tree though, hence this commit. llvm-svn: 205090
2014-03-29 18:18:08 +08:00
; The target lowering for integer comparisons was replacing some DAG nodes
; during operation legalization, which resulted in dangling pointers,
; cycles in DAGs, and eventually crashes. This is the testcase for
; one of those crashes. (rdar://10653656)
define void @test(i1 zeroext %IsArrow) nounwind ssp align 2 {
entry:
br i1 undef, label %return, label %lor.lhs.false
lor.lhs.false:
br i1 undef, label %return, label %if.end
if.end:
[opaque pointer type] Add textual IR support for explicit type parameter to load instruction Essentially the same as the GEP change in r230786. A similar migration script can be used to update test cases, though a few more test case improvements/changes were required this time around: (r229269-r229278) import fileinput import sys import re pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)") for line in sys.stdin: sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line)) Reviewers: rafael, dexonsmith, grosser Differential Revision: http://reviews.llvm.org/D7649 llvm-svn: 230794
2015-02-28 05:17:42 +08:00
%tmp.i = load i64, i64* undef, align 8
ARM64: initial backend import This adds a second implementation of the AArch64 architecture to LLVM, accessible in parallel via the "arm64" triple. The plan over the coming weeks & months is to merge the two into a single backend, during which time thorough code review should naturally occur. Everything will be easier with the target in-tree though, hence this commit. llvm-svn: 205090
2014-03-29 18:18:08 +08:00
%and.i.i.i = and i64 %tmp.i, -16
br i1 %IsArrow, label %if.else_crit_edge, label %if.end32
if.else_crit_edge:
br i1 undef, label %if.end32, label %return
if.end32:
%0 = icmp ult i32 undef, 3
%1 = zext i64 %tmp.i to i320
%.pn.v = select i1 %0, i320 128, i320 64
%.pn = shl i320 %1, %.pn.v
%ins346392 = or i320 %.pn, 0
store i320 %ins346392, i320* undef, align 8
br i1 undef, label %sw.bb.i.i, label %exit
sw.bb.i.i:
unreachable
exit:
unreachable
return:
ret void
}