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llvm-project/llvm/test/CodeGen/SPARC/float.ll

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[Sparc] Fix double-float fabs and fneg on little endian CPUs. The SparcV8 fneg and fabs instructions interestingly come only in a single-float variant. Since the sign bit is always the topmost bit no matter what size float it is, you simply operate on the high subregister, as if it were a single float. However, the layout of double-floats in the float registers is reversed on little-endian CPUs, so that the high bits are in the second subregister, rather than the first. Thus, this expansion must check the endianness to use the correct subregister. llvm-svn: 267489
2016-04-26 06:54:09 +08:00
; RUN: llc -march=sparc < %s | FileCheck %s -check-prefix=V8 -check-prefix=V8-BE
; RUN: llc -march=sparcel < %s | FileCheck %s -check-prefix=V8 -check-prefix=V8-EL
[Sparc] Delete FPMover Pass and remove Fp* Pseudo-instructions from Sparc backend. llvm-svn: 183613
2013-06-08 23:32:59 +08:00
; RUN: llc -march=sparc -O0 < %s | FileCheck %s -check-prefix=V8-UNOPT
; RUN: llc -march=sparc -mattr=v9 < %s | FileCheck %s -check-prefix=V9
[SparcV9] Handle i64 <-> float conversions in sparcv9 mode. llvm-svn: 193957
2013-11-03 20:28:40 +08:00
; RUN: llc -mtriple=sparc64-unknown-linux < %s | FileCheck %s -check-prefix=SPARC64
[Sparc] Delete FPMover Pass and remove Fp* Pseudo-instructions from Sparc backend. llvm-svn: 183613
2013-06-08 23:32:59 +08:00
Convert CodeGen/*/*.ll tests to use the new CHECK-LABEL for easier debugging. No functionality change and all tests pass after conversion. This was done with the following sed invocation to catch label lines demarking function boundaries: sed -i '' "s/^;\( *\)\([A-Z0-9_]*\):\( *\)test\([A-Za-z0-9_-]*\):\( *\)$/;\1\2-LABEL:\3test\4:\5/g" test/CodeGen/*/*.ll which was written conservatively to avoid false positives rather than false negatives. I scanned through all the changes and everything looks correct. llvm-svn: 186258
2013-07-14 04:38:47 +08:00
; V8-LABEL: test_neg:
[Sparc] Delete FPMover Pass and remove Fp* Pseudo-instructions from Sparc backend. llvm-svn: 183613
2013-06-08 23:32:59 +08:00
; V8: call get_double
[Sparc] Fix double-float fabs and fneg on little endian CPUs. The SparcV8 fneg and fabs instructions interestingly come only in a single-float variant. Since the sign bit is always the topmost bit no matter what size float it is, you simply operate on the high subregister, as if it were a single float. However, the layout of double-floats in the float registers is reversed on little-endian CPUs, so that the high bits are in the second subregister, rather than the first. Thus, this expansion must check the endianness to use the correct subregister. llvm-svn: 267489
2016-04-26 06:54:09 +08:00
; V8-BE: fnegs %f0, %f0
; V8-EL: fnegs %f1, %f1
[Sparc] Delete FPMover Pass and remove Fp* Pseudo-instructions from Sparc backend. llvm-svn: 183613
2013-06-08 23:32:59 +08:00
Mass update to CodeGen tests to use CHECK-LABEL for labels corresponding to function definitions for more informative error messages. No functionality change and all updated tests passed locally. This update was done with the following bash script: find test/CodeGen -name "*.ll" | \ while read NAME; do echo "$NAME" if ! grep -q "^; *RUN: *llc.*debug" $NAME; then TEMP=`mktemp -t temp` cp $NAME $TEMP sed -n "s/^define [^@]*@\([A-Za-z0-9_]*\)(.*$/\1/p" < $NAME | \ while read FUNC; do sed -i '' "s/;\(.*\)\([A-Za-z0-9_-]*\):\( *\)$FUNC: *\$/;\1\2-LABEL:\3$FUNC:/g" $TEMP done sed -i '' "s/;\(.*\)-LABEL-LABEL:/;\1-LABEL:/" $TEMP sed -i '' "s/;\(.*\)-NEXT-LABEL:/;\1-NEXT:/" $TEMP sed -i '' "s/;\(.*\)-NOT-LABEL:/;\1-NOT:/" $TEMP sed -i '' "s/;\(.*\)-DAG-LABEL:/;\1-DAG:/" $TEMP mv $TEMP $NAME fi done llvm-svn: 186280
2013-07-14 14:24:09 +08:00
; V8-UNOPT-LABEL: test_neg:
[Sparc] Delete FPMover Pass and remove Fp* Pseudo-instructions from Sparc backend. llvm-svn: 183613
2013-06-08 23:32:59 +08:00
; V8-UNOPT: fnegs
; V8-UNOPT: ! implicit-def
; V8-UNOPT: fmovs {{.+}}, %f0
; V8-UNOPT: fmovs {{.+}}, %f1
Convert CodeGen/*/*.ll tests to use the new CHECK-LABEL for easier debugging. No functionality change and all tests pass after conversion. This was done with the following sed invocation to catch label lines demarking function boundaries: sed -i '' "s/^;\( *\)\([A-Z0-9_]*\):\( *\)test\([A-Za-z0-9_-]*\):\( *\)$/;\1\2-LABEL:\3test\4:\5/g" test/CodeGen/*/*.ll which was written conservatively to avoid false positives rather than false negatives. I scanned through all the changes and everything looks correct. llvm-svn: 186258
2013-07-14 04:38:47 +08:00
; V9-LABEL: test_neg:
[Sparc] Delete FPMover Pass and remove Fp* Pseudo-instructions from Sparc backend. llvm-svn: 183613
2013-06-08 23:32:59 +08:00
; V9: fnegd %f0, %f0
[SparcV9] Handle i64 <-> float conversions in sparcv9 mode. llvm-svn: 193957
2013-11-03 20:28:40 +08:00
; SPARC64-LABEL: test_neg:
; SPARC64: fnegd %f0, %f0
[Sparc] Delete FPMover Pass and remove Fp* Pseudo-instructions from Sparc backend. llvm-svn: 183613
2013-06-08 23:32:59 +08:00
define double @test_neg() {
entry:
%0 = tail call double @get_double()
%1 = fsub double -0.000000e+00, %0
ret double %1
}
Convert CodeGen/*/*.ll tests to use the new CHECK-LABEL for easier debugging. No functionality change and all tests pass after conversion. This was done with the following sed invocation to catch label lines demarking function boundaries: sed -i '' "s/^;\( *\)\([A-Z0-9_]*\):\( *\)test\([A-Za-z0-9_-]*\):\( *\)$/;\1\2-LABEL:\3test\4:\5/g" test/CodeGen/*/*.ll which was written conservatively to avoid false positives rather than false negatives. I scanned through all the changes and everything looks correct. llvm-svn: 186258
2013-07-14 04:38:47 +08:00
; V8-LABEL: test_abs:
[Sparc] Fix double-float fabs and fneg on little endian CPUs. The SparcV8 fneg and fabs instructions interestingly come only in a single-float variant. Since the sign bit is always the topmost bit no matter what size float it is, you simply operate on the high subregister, as if it were a single float. However, the layout of double-floats in the float registers is reversed on little-endian CPUs, so that the high bits are in the second subregister, rather than the first. Thus, this expansion must check the endianness to use the correct subregister. llvm-svn: 267489
2016-04-26 06:54:09 +08:00
; V8-BE: fabss %f0, %f0
; V8-EL: fabss %f1, %f1
[Sparc] Delete FPMover Pass and remove Fp* Pseudo-instructions from Sparc backend. llvm-svn: 183613
2013-06-08 23:32:59 +08:00
Mass update to CodeGen tests to use CHECK-LABEL for labels corresponding to function definitions for more informative error messages. No functionality change and all updated tests passed locally. This update was done with the following bash script: find test/CodeGen -name "*.ll" | \ while read NAME; do echo "$NAME" if ! grep -q "^; *RUN: *llc.*debug" $NAME; then TEMP=`mktemp -t temp` cp $NAME $TEMP sed -n "s/^define [^@]*@\([A-Za-z0-9_]*\)(.*$/\1/p" < $NAME | \ while read FUNC; do sed -i '' "s/;\(.*\)\([A-Za-z0-9_-]*\):\( *\)$FUNC: *\$/;\1\2-LABEL:\3$FUNC:/g" $TEMP done sed -i '' "s/;\(.*\)-LABEL-LABEL:/;\1-LABEL:/" $TEMP sed -i '' "s/;\(.*\)-NEXT-LABEL:/;\1-NEXT:/" $TEMP sed -i '' "s/;\(.*\)-NOT-LABEL:/;\1-NOT:/" $TEMP sed -i '' "s/;\(.*\)-DAG-LABEL:/;\1-DAG:/" $TEMP mv $TEMP $NAME fi done llvm-svn: 186280
2013-07-14 14:24:09 +08:00
; V8-UNOPT-LABEL: test_abs:
[Sparc] Delete FPMover Pass and remove Fp* Pseudo-instructions from Sparc backend. llvm-svn: 183613
2013-06-08 23:32:59 +08:00
; V8-UNOPT: fabss
; V8-UNOPT: ! implicit-def
; V8-UNOPT: fmovs {{.+}}, %f0
; V8-UNOPT: fmovs {{.+}}, %f1
Convert CodeGen/*/*.ll tests to use the new CHECK-LABEL for easier debugging. No functionality change and all tests pass after conversion. This was done with the following sed invocation to catch label lines demarking function boundaries: sed -i '' "s/^;\( *\)\([A-Z0-9_]*\):\( *\)test\([A-Za-z0-9_-]*\):\( *\)$/;\1\2-LABEL:\3test\4:\5/g" test/CodeGen/*/*.ll which was written conservatively to avoid false positives rather than false negatives. I scanned through all the changes and everything looks correct. llvm-svn: 186258
2013-07-14 04:38:47 +08:00
; V9-LABEL: test_abs:
[Sparc] Delete FPMover Pass and remove Fp* Pseudo-instructions from Sparc backend. llvm-svn: 183613
2013-06-08 23:32:59 +08:00
; V9: fabsd %f0, %f0
[SparcV9] Handle i64 <-> float conversions in sparcv9 mode. llvm-svn: 193957
2013-11-03 20:28:40 +08:00
; SPARC64-LABEL: test_abs:
; SPARC64: fabsd %f0, %f0
[Sparc] Delete FPMover Pass and remove Fp* Pseudo-instructions from Sparc backend. llvm-svn: 183613
2013-06-08 23:32:59 +08:00
define double @test_abs() {
entry:
%0 = tail call double @get_double()
%1 = tail call double @llvm.fabs.f64(double %0)
ret double %1
}
declare double @get_double()
declare double @llvm.fabs.f64(double) nounwind readonly
[Sparc] Added V9's extra floating point registers and their aliases. llvm-svn: 189195
2013-08-26 01:03:02 +08:00
; V8-LABEL: test_v9_floatreg:
[SPARC] Switch to the Machine Scheduler. The (mostly-deprecated) SelectionDAG-based ILPListDAGScheduler scheduler was making poor scheduling decisions, causing high register pressure and extraneous register spills. Switching to the newer machine scheduler generates better code -- even without there being a machine model defined for SPARC yet. (Actually committing the test changes too, this time, unlike r247315) llvm-svn: 247343
2015-09-11 05:49:06 +08:00
; V8: fsubd {{.+}}, {{.+}}, [[R:%f(((1|2)?(0|2|4|6|8))|30)]]
[Sparc] Added V9's extra floating point registers and their aliases. llvm-svn: 189195
2013-08-26 01:03:02 +08:00
; V8: std [[R]], [%{{.+}}]
; V8: ldd [%{{.+}}], %f0
[SPARC] Switch to the Machine Scheduler. The (mostly-deprecated) SelectionDAG-based ILPListDAGScheduler scheduler was making poor scheduling decisions, causing high register pressure and extraneous register spills. Switching to the newer machine scheduler generates better code -- even without there being a machine model defined for SPARC yet. (Actually committing the test changes too, this time, unlike r247315) llvm-svn: 247343
2015-09-11 05:49:06 +08:00
; V8: faddd {{.+}}, {{.+}}, {{.+}}
[Sparc] Added V9's extra floating point registers and their aliases. llvm-svn: 189195
2013-08-26 01:03:02 +08:00
; V9-LABEL: test_v9_floatreg:
; V9: fsubd {{.+}}, {{.+}}, {{.+}}
[SPARC] Switch to the Machine Scheduler. The (mostly-deprecated) SelectionDAG-based ILPListDAGScheduler scheduler was making poor scheduling decisions, causing high register pressure and extraneous register spills. Switching to the newer machine scheduler generates better code -- even without there being a machine model defined for SPARC yet. (Actually committing the test changes too, this time, unlike r247315) llvm-svn: 247343
2015-09-11 05:49:06 +08:00
; V9: faddd {{.+}}, {{.+}}, %f0
[Sparc] Added V9's extra floating point registers and their aliases. llvm-svn: 189195
2013-08-26 01:03:02 +08:00
[SparcV9] Handle i64 <-> float conversions in sparcv9 mode. llvm-svn: 193957
2013-11-03 20:28:40 +08:00
; SPARC64-LABEL: test_v9_floatreg:
; SPARC64: fsubd {{.+}}, {{.+}}, {{.+}}
[SPARC] Switch to the Machine Scheduler. The (mostly-deprecated) SelectionDAG-based ILPListDAGScheduler scheduler was making poor scheduling decisions, causing high register pressure and extraneous register spills. Switching to the newer machine scheduler generates better code -- even without there being a machine model defined for SPARC yet. (Actually committing the test changes too, this time, unlike r247315) llvm-svn: 247343
2015-09-11 05:49:06 +08:00
; SPARC64: faddd {{.+}}, {{.+}}, %f0
[Sparc] Added V9's extra floating point registers and their aliases. llvm-svn: 189195
2013-08-26 01:03:02 +08:00
define double @test_v9_floatreg() {
entry:
%0 = tail call double @get_double()
%1 = tail call double @get_double()
%2 = fsub double %0, %1
tail call void asm sideeffect "", "~{f0},~{f2},~{f3},~{f4},~{f5},~{f6},~{f7},~{f8},~{f9},~{f10},~{f11},~{f12},~{f13},~{f14},~{f15},~{f16},~{f17},~{f18},~{f19},~{f20},~{f21},~{f22},~{f23},~{f24},~{f25},~{f26},~{f27},~{f28},~{f29},~{f30},~{f31}"()
%3 = fadd double %2, %2
ret double %3
}
[SparcV9] Handle i64 <-> float conversions in sparcv9 mode. llvm-svn: 193957
2013-11-03 20:28:40 +08:00
; V8-LABEL: test_xtos_stox
; V8: call __floatdisf
; V8: call __fixsfdi
; V9-LABEL: test_xtos_stox
; V9: call __floatdisf
; V9: call __fixsfdi
; SPARC64-LABEL: test_xtos_stox
; SPARC64: fxtos
; SPARC64: fstox
define void @test_xtos_stox(i64 %a, i64* %ptr0, float* %ptr1) {
entry:
%0 = sitofp i64 %a to float
store float %0, float* %ptr1, align 8
%1 = fptosi float %0 to i64
store i64 %1, i64* %ptr0, align 8
ret void
}
; V8-LABEL: test_itos_stoi
; V8: fitos
; V8: fstoi
; V9-LABEL: test_itos_stoi
; V9: fitos
; V9: fstoi
; SPARC64-LABEL: test_itos_stoi
; SPARC64: fitos
; SPARC64: fstoi
define void @test_itos_stoi(i32 %a, i32* %ptr0, float* %ptr1) {
entry:
%0 = sitofp i32 %a to float
store float %0, float* %ptr1, align 8
%1 = fptosi float %0 to i32
store i32 %1, i32* %ptr0, align 8
ret void
}
; V8-LABEL: test_xtod_dtox
; V8: call __floatdidf
; V8: call __fixdfdi
; V9-LABEL: test_xtod_dtox
; V9: call __floatdidf
; V9: call __fixdfdi
; SPARC64-LABEL: test_xtod_dtox
; SPARC64: fxtod
; SPARC64: fdtox
define void @test_xtod_dtox(i64 %a, i64* %ptr0, double* %ptr1) {
entry:
%0 = sitofp i64 %a to double
store double %0, double* %ptr1, align 8
%1 = fptosi double %0 to i64
store i64 %1, i64* %ptr0, align 8
ret void
}
; V8-LABEL: test_itod_dtoi
; V8: fitod
; V8: fdtoi
; V9-LABEL: test_itod_dtoi
; V9: fitod
; V9: fdtoi
; SPARC64-LABEL: test_itod_dtoi
; SPARC64: fitod
; SPARC64: fdtoi
SelectionDAG: fold (fp_to_u/sint (s/uint_to_fp)) here too Update SPARC tests to match. From: Fiona Glaser <fglaser@apple.com> llvm-svn: 229438
2015-02-17 05:47:58 +08:00
define void @test_itod_dtoi(i32 %a, double %b, i32* %ptr0, double* %ptr1) {
[SparcV9] Handle i64 <-> float conversions in sparcv9 mode. llvm-svn: 193957
2013-11-03 20:28:40 +08:00
entry:
%0 = sitofp i32 %a to double
store double %0, double* %ptr1, align 8
SelectionDAG: fold (fp_to_u/sint (s/uint_to_fp)) here too Update SPARC tests to match. From: Fiona Glaser <fglaser@apple.com> llvm-svn: 229438
2015-02-17 05:47:58 +08:00
%1 = fptosi double %b to i32
[SparcV9] Handle i64 <-> float conversions in sparcv9 mode. llvm-svn: 193957
2013-11-03 20:28:40 +08:00
store i32 %1, i32* %ptr0, align 8
ret void
}
; V8-LABEL: test_uxtos_stoux
; V8: call __floatundisf
; V8: call __fixunssfdi
; V9-LABEL: test_uxtos_stoux
; V9: call __floatundisf
; V9: call __fixunssfdi
; SPARC64-LABEL: test_uxtos_stoux
; SPARC64-NOT: call __floatundisf
; SPARC64-NOT: call __fixunssfdi
define void @test_uxtos_stoux(i64 %a, i64* %ptr0, float* %ptr1) {
entry:
%0 = uitofp i64 %a to float
store float %0, float* %ptr1, align 8
%1 = fptoui float %0 to i64
store i64 %1, i64* %ptr0, align 8
ret void
}
; V8-LABEL: test_utos_stou
; V8: fdtos
; V8: fstoi
; V9-LABEL: test_utos_stou
; V9: fdtos
; V9: fstoi
; SPARC64-LABEL: test_utos_stou
Revert r318704 - [Sparc] efficient pattern for UINT_TO_FP conversion See bug https://bugs.llvm.org/show_bug.cgi?id=35631 r318704 is giving a fatal error on some code with unsigned to floating point conversions. llvm-svn: 320429
2017-12-12 06:25:04 +08:00
; SPARC64: fdtos
[SparcV9] Handle i64 <-> float conversions in sparcv9 mode. llvm-svn: 193957
2013-11-03 20:28:40 +08:00
; SPARC64: fstoi
define void @test_utos_stou(i32 %a, i32* %ptr0, float* %ptr1) {
entry:
%0 = uitofp i32 %a to float
store float %0, float* %ptr1, align 8
%1 = fptoui float %0 to i32
store i32 %1, i32* %ptr0, align 8
ret void
}
; V8-LABEL: test_uxtod_dtoux
; V8: call __floatundidf
; V8: call __fixunsdfdi
; V9-LABEL: test_uxtod_dtoux
; V9: call __floatundidf
; V9: call __fixunsdfdi
[Sparc] Added V9's extra floating point registers and their aliases. llvm-svn: 189195
2013-08-26 01:03:02 +08:00
[SparcV9] Handle i64 <-> float conversions in sparcv9 mode. llvm-svn: 193957
2013-11-03 20:28:40 +08:00
; SPARC64-LABEL: test_uxtod_dtoux
; SPARC64-NOT: call __floatundidf
; SPARC64-NOT: call __floatunsdfdi
define void @test_uxtod_dtoux(i64 %a, i64* %ptr0, double* %ptr1) {
entry:
%0 = uitofp i64 %a to double
store double %0, double* %ptr1, align 8
%1 = fptoui double %0 to i64
store i64 %1, i64* %ptr0, align 8
ret void
}
; V8-LABEL: test_utod_dtou
; V8-NOT: fitod
; V8: fdtoi
; V9-LABEL: test_utod_dtou
; V9-NOT: fitod
; V9: fdtoi
; SPARC64-LABEL: test_utod_dtou
; SPARC64-NOT: fitod
; SPARC64: fdtoi
define void @test_utod_dtou(i32 %a, double %b, i32* %ptr0, double* %ptr1) {
entry:
%0 = uitofp i32 %a to double
store double %0, double* %ptr1, align 8
%1 = fptoui double %b to i32
store i32 %1, i32* %ptr0, align 8
ret void
}