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llvm-project/llvm/test/CodeGen/ARM/select-imm.ll

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ARM: fixup more tests to specify the target more explicitly This changes the tests that were targeting ARM EABI to explicitly specify the environment rather than relying on the default. This breaks with the new Windows on ARM support when running the tests on Windows where the default environment is no longer EABI. Take the opportunity to avoid a pointless redirect (helps when trying to debug with providing a command line invocation which can be copy and pasted) and removing a few greps in favour of FileCheck. llvm-svn: 205541
2014-04-04 00:01:44 +08:00
; RUN: llc -mtriple=arm-eabi %s -o - | FileCheck %s --check-prefix=ARM
; RUN: llc -mtriple=arm-eabi -mcpu=arm1156t2-s -mattr=+thumb2 %s -o - \
; RUN: | FileCheck %s --check-prefix=ARMT2
[ARM] Add tests for D34515 This is NFC and a preparatory step for D34515. Differential Revision: https://reviews.llvm.org/D41122 llvm-svn: 320795
2017-12-15 17:24:46 +08:00
; RUN: llc -mtriple=thumb-eabi -mcpu=cortex-m0 %s -o - \
; RUN: | FileCheck %s --check-prefix=THUMB1
ARM: fixup more tests to specify the target more explicitly This changes the tests that were targeting ARM EABI to explicitly specify the environment rather than relying on the default. This breaks with the new Windows on ARM support when running the tests on Windows where the default environment is no longer EABI. Take the opportunity to avoid a pointless redirect (helps when trying to debug with providing a command line invocation which can be copy and pasted) and removing a few greps in favour of FileCheck. llvm-svn: 205541
2014-04-04 00:01:44 +08:00
; RUN: llc -mtriple=thumb-eabi -mcpu=arm1156t2-s -mattr=+thumb2 %s -o - \
; RUN: | FileCheck %s --check-prefix=THUMB2
Fix codegen of conditional move of immediates. We were not making use of the immediate forms of cmov instructions at all. llvm-svn: 89423
2009-11-20 08:54:03 +08:00
[ARM] Add tests for D34515 This is NFC and a preparatory step for D34515. Differential Revision: https://reviews.llvm.org/D41122 llvm-svn: 320795
2017-12-15 17:24:46 +08:00
; RUN: llc -mtriple=thumbv8m.base-eabi %s -o - \
; RUN: | FileCheck %s --check-prefix=V8MBASE
Remove arm_apcscc from the test files. It is the default and doing this matches what llvm-gcc and clang now produce. llvm-svn: 106221
2010-06-17 23:18:27 +08:00
define i32 @t1(i32 %c) nounwind readnone {
Fix codegen of conditional move of immediates. We were not making use of the immediate forms of cmov instructions at all. llvm-svn: 89423
2009-11-20 08:54:03 +08:00
entry:
Mass update to CodeGen tests to use CHECK-LABEL for labels corresponding to function definitions for more informative error messages. No functionality change and all updated tests passed locally. This update was done with the following bash script: find test/CodeGen -name "*.ll" | \ while read NAME; do echo "$NAME" if ! grep -q "^; *RUN: *llc.*debug" $NAME; then TEMP=`mktemp -t temp` cp $NAME $TEMP sed -n "s/^define [^@]*@\([A-Za-z0-9_]*\)(.*$/\1/p" < $NAME | \ while read FUNC; do sed -i '' "s/;\(.*\)\([A-Za-z0-9_-]*\):\( *\)$FUNC: *\$/;\1\2-LABEL:\3$FUNC:/g" $TEMP done sed -i '' "s/;\(.*\)-LABEL-LABEL:/;\1-LABEL:/" $TEMP sed -i '' "s/;\(.*\)-NEXT-LABEL:/;\1-NEXT:/" $TEMP sed -i '' "s/;\(.*\)-NOT-LABEL:/;\1-NOT:/" $TEMP sed -i '' "s/;\(.*\)-DAG-LABEL:/;\1-DAG:/" $TEMP mv $TEMP $NAME fi done llvm-svn: 186280
2013-07-14 14:24:09 +08:00
; ARM-LABEL: t1:
Fix a bunch of ARM tests to be register allocation independent. llvm-svn: 130800
2011-05-04 06:31:21 +08:00
; ARM: mov [[R1:r[0-9]+]], #101
Simplify printing of ARM shifted immediates. Print shifted immediate values directly rather than as a payload+shifter value pair. This makes for more readable output assembly code, simplifies the instruction printer, and is consistent with how Thumb immediates are displayed. llvm-svn: 134902
2011-07-12 00:48:36 +08:00
; ARM: orr [[R1b:r[0-9]+]], [[R1]], #256
Allocate local registers in order for optimal coloring. Also avoid locals evicting locals just because they want a cheaper register. Problem: MI Sched knows exactly how many registers we have and assumes they can be colored. In cases where we have large blocks, usually from unrolled loops, greedy coloring fails. This is a source of "regressions" from the MI Scheduler on x86. I noticed this issue on x86 where we have long chains of two-address defs in the same live range. It's easy to see this in matrix multiplication benchmarks like IRSmk and even the unit test misched-matmul.ll. A fundamental difference between the LLVM register allocator and conventional graph coloring is that in our model a live range can't discover its neighbors, it can only verify its neighbors. That's why we initially went for greedy coloring and added eviction to deal with the hard cases. However, for singly defined and two-address live ranges, we can optimally color without visiting neighbors simply by processing the live ranges in instruction order. Other beneficial side effects: It is much easier to understand and debug regalloc for large blocks when the live ranges are allocated in order. Yes, global allocation is still very confusing, but it's nice to be able to comprehend what happened locally. Heuristics could be added to bias register assignment based on instruction locality (think late register pairing, banks...). Intuituvely this will make some test cases that are on the threshold of register pressure more stable. llvm-svn: 187139
2013-07-26 02:35:14 +08:00
; ARM: movgt {{r[0-1]}}, #123
Fix codegen of conditional move of immediates. We were not making use of the immediate forms of cmov instructions at all. llvm-svn: 89423
2009-11-20 08:54:03 +08:00
Mass update to CodeGen tests to use CHECK-LABEL for labels corresponding to function definitions for more informative error messages. No functionality change and all updated tests passed locally. This update was done with the following bash script: find test/CodeGen -name "*.ll" | \ while read NAME; do echo "$NAME" if ! grep -q "^; *RUN: *llc.*debug" $NAME; then TEMP=`mktemp -t temp` cp $NAME $TEMP sed -n "s/^define [^@]*@\([A-Za-z0-9_]*\)(.*$/\1/p" < $NAME | \ while read FUNC; do sed -i '' "s/;\(.*\)\([A-Za-z0-9_-]*\):\( *\)$FUNC: *\$/;\1\2-LABEL:\3$FUNC:/g" $TEMP done sed -i '' "s/;\(.*\)-LABEL-LABEL:/;\1-LABEL:/" $TEMP sed -i '' "s/;\(.*\)-NEXT-LABEL:/;\1-NEXT:/" $TEMP sed -i '' "s/;\(.*\)-NOT-LABEL:/;\1-NOT:/" $TEMP sed -i '' "s/;\(.*\)-DAG-LABEL:/;\1-DAG:/" $TEMP mv $TEMP $NAME fi done llvm-svn: 186280
2013-07-14 14:24:09 +08:00
; ARMT2-LABEL: t1:
Allocate local registers in order for optimal coloring. Also avoid locals evicting locals just because they want a cheaper register. Problem: MI Sched knows exactly how many registers we have and assumes they can be colored. In cases where we have large blocks, usually from unrolled loops, greedy coloring fails. This is a source of "regressions" from the MI Scheduler on x86. I noticed this issue on x86 where we have long chains of two-address defs in the same live range. It's easy to see this in matrix multiplication benchmarks like IRSmk and even the unit test misched-matmul.ll. A fundamental difference between the LLVM register allocator and conventional graph coloring is that in our model a live range can't discover its neighbors, it can only verify its neighbors. That's why we initially went for greedy coloring and added eviction to deal with the hard cases. However, for singly defined and two-address live ranges, we can optimally color without visiting neighbors simply by processing the live ranges in instruction order. Other beneficial side effects: It is much easier to understand and debug regalloc for large blocks when the live ranges are allocated in order. Yes, global allocation is still very confusing, but it's nice to be able to comprehend what happened locally. Heuristics could be added to bias register assignment based on instruction locality (think late register pairing, banks...). Intuituvely this will make some test cases that are on the threshold of register pressure more stable. llvm-svn: 187139
2013-07-26 02:35:14 +08:00
; ARMT2: movw [[R:r[0-1]]], #357
ARM: use TableGen patterns to select CMOV operations. Back in the mists of time (2008), it seems TableGen couldn't handle the patterns necessary to match ARM's CMOV node that we convert select operations to, so we wrote a lot of fairly hairy C++ to do it for us. TableGen can deal with it now: there were a few minor differences to CodeGen (see tests), but nothing obviously worse that I could see, so we should probably address anything that *does* come up in a localised manner. llvm-svn: 188995
2013-08-22 17:57:11 +08:00
; ARMT2: movwgt [[R]], #123
Add conditional move of large immediate. llvm-svn: 118968
2010-11-13 10:25:14 +08:00
[ARM] Add tests for D34515 This is NFC and a preparatory step for D34515. Differential Revision: https://reviews.llvm.org/D41122 llvm-svn: 320795
2017-12-15 17:24:46 +08:00
; THUMB1-LABEL: t1:
; THUMB1: mov r1, r0
; THUMB1: movs r2, #255
; THUMB1: adds r2, #102
; THUMB1: movs r0, #123
; THUMB1: cmp r1, #1
; THUMB1: bgt
Mass update to CodeGen tests to use CHECK-LABEL for labels corresponding to function definitions for more informative error messages. No functionality change and all updated tests passed locally. This update was done with the following bash script: find test/CodeGen -name "*.ll" | \ while read NAME; do echo "$NAME" if ! grep -q "^; *RUN: *llc.*debug" $NAME; then TEMP=`mktemp -t temp` cp $NAME $TEMP sed -n "s/^define [^@]*@\([A-Za-z0-9_]*\)(.*$/\1/p" < $NAME | \ while read FUNC; do sed -i '' "s/;\(.*\)\([A-Za-z0-9_-]*\):\( *\)$FUNC: *\$/;\1\2-LABEL:\3$FUNC:/g" $TEMP done sed -i '' "s/;\(.*\)-LABEL-LABEL:/;\1-LABEL:/" $TEMP sed -i '' "s/;\(.*\)-NEXT-LABEL:/;\1-NEXT:/" $TEMP sed -i '' "s/;\(.*\)-NOT-LABEL:/;\1-NOT:/" $TEMP sed -i '' "s/;\(.*\)-DAG-LABEL:/;\1-DAG:/" $TEMP mv $TEMP $NAME fi done llvm-svn: 186280
2013-07-14 14:24:09 +08:00
; THUMB2-LABEL: t1:
Allocate local registers in order for optimal coloring. Also avoid locals evicting locals just because they want a cheaper register. Problem: MI Sched knows exactly how many registers we have and assumes they can be colored. In cases where we have large blocks, usually from unrolled loops, greedy coloring fails. This is a source of "regressions" from the MI Scheduler on x86. I noticed this issue on x86 where we have long chains of two-address defs in the same live range. It's easy to see this in matrix multiplication benchmarks like IRSmk and even the unit test misched-matmul.ll. A fundamental difference between the LLVM register allocator and conventional graph coloring is that in our model a live range can't discover its neighbors, it can only verify its neighbors. That's why we initially went for greedy coloring and added eviction to deal with the hard cases. However, for singly defined and two-address live ranges, we can optimally color without visiting neighbors simply by processing the live ranges in instruction order. Other beneficial side effects: It is much easier to understand and debug regalloc for large blocks when the live ranges are allocated in order. Yes, global allocation is still very confusing, but it's nice to be able to comprehend what happened locally. Heuristics could be added to bias register assignment based on instruction locality (think late register pairing, banks...). Intuituvely this will make some test cases that are on the threshold of register pressure more stable. llvm-svn: 187139
2013-07-26 02:35:14 +08:00
; THUMB2: movw [[R:r[0-1]]], #357
; THUMB2: movgt [[R]], #123
Fix codegen of conditional move of immediates. We were not making use of the immediate forms of cmov instructions at all. llvm-svn: 89423
2009-11-20 08:54:03 +08:00
%0 = icmp sgt i32 %c, 1
%1 = select i1 %0, i32 123, i32 357
ret i32 %1
}
Remove arm_apcscc from the test files. It is the default and doing this matches what llvm-gcc and clang now produce. llvm-svn: 106221
2010-06-17 23:18:27 +08:00
define i32 @t2(i32 %c) nounwind readnone {
Fix codegen of conditional move of immediates. We were not making use of the immediate forms of cmov instructions at all. llvm-svn: 89423
2009-11-20 08:54:03 +08:00
entry:
Mass update to CodeGen tests to use CHECK-LABEL for labels corresponding to function definitions for more informative error messages. No functionality change and all updated tests passed locally. This update was done with the following bash script: find test/CodeGen -name "*.ll" | \ while read NAME; do echo "$NAME" if ! grep -q "^; *RUN: *llc.*debug" $NAME; then TEMP=`mktemp -t temp` cp $NAME $TEMP sed -n "s/^define [^@]*@\([A-Za-z0-9_]*\)(.*$/\1/p" < $NAME | \ while read FUNC; do sed -i '' "s/;\(.*\)\([A-Za-z0-9_-]*\):\( *\)$FUNC: *\$/;\1\2-LABEL:\3$FUNC:/g" $TEMP done sed -i '' "s/;\(.*\)-LABEL-LABEL:/;\1-LABEL:/" $TEMP sed -i '' "s/;\(.*\)-NEXT-LABEL:/;\1-NEXT:/" $TEMP sed -i '' "s/;\(.*\)-NOT-LABEL:/;\1-NOT:/" $TEMP sed -i '' "s/;\(.*\)-DAG-LABEL:/;\1-DAG:/" $TEMP mv $TEMP $NAME fi done llvm-svn: 186280
2013-07-14 14:24:09 +08:00
; ARM-LABEL: t2:
ARM: use TableGen patterns to select CMOV operations. Back in the mists of time (2008), it seems TableGen couldn't handle the patterns necessary to match ARM's CMOV node that we convert select operations to, so we wrote a lot of fairly hairy C++ to do it for us. TableGen can deal with it now: there were a few minor differences to CodeGen (see tests), but nothing obviously worse that I could see, so we should probably address anything that *does* come up in a localised manner. llvm-svn: 188995
2013-08-22 17:57:11 +08:00
; ARM: mov [[R:r[0-9]+]], #101
; ARM: orr [[R]], [[R]], #256
; ARM: movle [[R]], #123
Fix codegen of conditional move of immediates. We were not making use of the immediate forms of cmov instructions at all. llvm-svn: 89423
2009-11-20 08:54:03 +08:00
Mass update to CodeGen tests to use CHECK-LABEL for labels corresponding to function definitions for more informative error messages. No functionality change and all updated tests passed locally. This update was done with the following bash script: find test/CodeGen -name "*.ll" | \ while read NAME; do echo "$NAME" if ! grep -q "^; *RUN: *llc.*debug" $NAME; then TEMP=`mktemp -t temp` cp $NAME $TEMP sed -n "s/^define [^@]*@\([A-Za-z0-9_]*\)(.*$/\1/p" < $NAME | \ while read FUNC; do sed -i '' "s/;\(.*\)\([A-Za-z0-9_-]*\):\( *\)$FUNC: *\$/;\1\2-LABEL:\3$FUNC:/g" $TEMP done sed -i '' "s/;\(.*\)-LABEL-LABEL:/;\1-LABEL:/" $TEMP sed -i '' "s/;\(.*\)-NEXT-LABEL:/;\1-NEXT:/" $TEMP sed -i '' "s/;\(.*\)-NOT-LABEL:/;\1-NOT:/" $TEMP sed -i '' "s/;\(.*\)-DAG-LABEL:/;\1-DAG:/" $TEMP mv $TEMP $NAME fi done llvm-svn: 186280
2013-07-14 14:24:09 +08:00
; ARMT2-LABEL: t2:
Allocate local registers in order for optimal coloring. Also avoid locals evicting locals just because they want a cheaper register. Problem: MI Sched knows exactly how many registers we have and assumes they can be colored. In cases where we have large blocks, usually from unrolled loops, greedy coloring fails. This is a source of "regressions" from the MI Scheduler on x86. I noticed this issue on x86 where we have long chains of two-address defs in the same live range. It's easy to see this in matrix multiplication benchmarks like IRSmk and even the unit test misched-matmul.ll. A fundamental difference between the LLVM register allocator and conventional graph coloring is that in our model a live range can't discover its neighbors, it can only verify its neighbors. That's why we initially went for greedy coloring and added eviction to deal with the hard cases. However, for singly defined and two-address live ranges, we can optimally color without visiting neighbors simply by processing the live ranges in instruction order. Other beneficial side effects: It is much easier to understand and debug regalloc for large blocks when the live ranges are allocated in order. Yes, global allocation is still very confusing, but it's nice to be able to comprehend what happened locally. Heuristics could be added to bias register assignment based on instruction locality (think late register pairing, banks...). Intuituvely this will make some test cases that are on the threshold of register pressure more stable. llvm-svn: 187139
2013-07-26 02:35:14 +08:00
; ARMT2: mov [[R:r[0-1]]], #123
; ARMT2: movwgt [[R]], #357
Add conditional move of large immediate. llvm-svn: 118968
2010-11-13 10:25:14 +08:00
[ARM] Add tests for D34515 This is NFC and a preparatory step for D34515. Differential Revision: https://reviews.llvm.org/D41122 llvm-svn: 320795
2017-12-15 17:24:46 +08:00
; THUMB1-LABEL: t2:
; THUMB1: cmp r{{[0-9]+}}, #1
; THUMB1: bgt
Mass update to CodeGen tests to use CHECK-LABEL for labels corresponding to function definitions for more informative error messages. No functionality change and all updated tests passed locally. This update was done with the following bash script: find test/CodeGen -name "*.ll" | \ while read NAME; do echo "$NAME" if ! grep -q "^; *RUN: *llc.*debug" $NAME; then TEMP=`mktemp -t temp` cp $NAME $TEMP sed -n "s/^define [^@]*@\([A-Za-z0-9_]*\)(.*$/\1/p" < $NAME | \ while read FUNC; do sed -i '' "s/;\(.*\)\([A-Za-z0-9_-]*\):\( *\)$FUNC: *\$/;\1\2-LABEL:\3$FUNC:/g" $TEMP done sed -i '' "s/;\(.*\)-LABEL-LABEL:/;\1-LABEL:/" $TEMP sed -i '' "s/;\(.*\)-NEXT-LABEL:/;\1-NEXT:/" $TEMP sed -i '' "s/;\(.*\)-NOT-LABEL:/;\1-NOT:/" $TEMP sed -i '' "s/;\(.*\)-DAG-LABEL:/;\1-DAG:/" $TEMP mv $TEMP $NAME fi done llvm-svn: 186280
2013-07-14 14:24:09 +08:00
; THUMB2-LABEL: t2:
Allocate local registers in order for optimal coloring. Also avoid locals evicting locals just because they want a cheaper register. Problem: MI Sched knows exactly how many registers we have and assumes they can be colored. In cases where we have large blocks, usually from unrolled loops, greedy coloring fails. This is a source of "regressions" from the MI Scheduler on x86. I noticed this issue on x86 where we have long chains of two-address defs in the same live range. It's easy to see this in matrix multiplication benchmarks like IRSmk and even the unit test misched-matmul.ll. A fundamental difference between the LLVM register allocator and conventional graph coloring is that in our model a live range can't discover its neighbors, it can only verify its neighbors. That's why we initially went for greedy coloring and added eviction to deal with the hard cases. However, for singly defined and two-address live ranges, we can optimally color without visiting neighbors simply by processing the live ranges in instruction order. Other beneficial side effects: It is much easier to understand and debug regalloc for large blocks when the live ranges are allocated in order. Yes, global allocation is still very confusing, but it's nice to be able to comprehend what happened locally. Heuristics could be added to bias register assignment based on instruction locality (think late register pairing, banks...). Intuituvely this will make some test cases that are on the threshold of register pressure more stable. llvm-svn: 187139
2013-07-26 02:35:14 +08:00
; THUMB2: mov{{(s|\.w)}} [[R:r[0-1]]], #123
; THUMB2: movwgt [[R]], #357
Fix codegen of conditional move of immediates. We were not making use of the immediate forms of cmov instructions at all. llvm-svn: 89423
2009-11-20 08:54:03 +08:00
%0 = icmp sgt i32 %c, 1
%1 = select i1 %0, i32 357, i32 123
ret i32 %1
}
Remove arm_apcscc from the test files. It is the default and doing this matches what llvm-gcc and clang now produce. llvm-svn: 106221
2010-06-17 23:18:27 +08:00
define i32 @t3(i32 %a) nounwind readnone {
Fix codegen of conditional move of immediates. We were not making use of the immediate forms of cmov instructions at all. llvm-svn: 89423
2009-11-20 08:54:03 +08:00
entry:
Mass update to CodeGen tests to use CHECK-LABEL for labels corresponding to function definitions for more informative error messages. No functionality change and all updated tests passed locally. This update was done with the following bash script: find test/CodeGen -name "*.ll" | \ while read NAME; do echo "$NAME" if ! grep -q "^; *RUN: *llc.*debug" $NAME; then TEMP=`mktemp -t temp` cp $NAME $TEMP sed -n "s/^define [^@]*@\([A-Za-z0-9_]*\)(.*$/\1/p" < $NAME | \ while read FUNC; do sed -i '' "s/;\(.*\)\([A-Za-z0-9_-]*\):\( *\)$FUNC: *\$/;\1\2-LABEL:\3$FUNC:/g" $TEMP done sed -i '' "s/;\(.*\)-LABEL-LABEL:/;\1-LABEL:/" $TEMP sed -i '' "s/;\(.*\)-NEXT-LABEL:/;\1-NEXT:/" $TEMP sed -i '' "s/;\(.*\)-NOT-LABEL:/;\1-NOT:/" $TEMP sed -i '' "s/;\(.*\)-DAG-LABEL:/;\1-DAG:/" $TEMP mv $TEMP $NAME fi done llvm-svn: 186280
2013-07-14 14:24:09 +08:00
; ARM-LABEL: t3:
[ARM] Materialise some boolean values to avoid a branch This patch combines some cases of ARMISD::CMOV for integers that arise in comparisons of the form a != b ? x : 0 a == b ? 0 : x and that currently (e.g. in Thumb1) are emitted as branches. Differential Revision: https://reviews.llvm.org/D34515 llvm-svn: 325323
2018-02-16 17:23:59 +08:00
; ARM: rsbs r1, r0, #0
; ARM: adc r0, r0, r1
Fix codegen of conditional move of immediates. We were not making use of the immediate forms of cmov instructions at all. llvm-svn: 89423
2009-11-20 08:54:03 +08:00
Mass update to CodeGen tests to use CHECK-LABEL for labels corresponding to function definitions for more informative error messages. No functionality change and all updated tests passed locally. This update was done with the following bash script: find test/CodeGen -name "*.ll" | \ while read NAME; do echo "$NAME" if ! grep -q "^; *RUN: *llc.*debug" $NAME; then TEMP=`mktemp -t temp` cp $NAME $TEMP sed -n "s/^define [^@]*@\([A-Za-z0-9_]*\)(.*$/\1/p" < $NAME | \ while read FUNC; do sed -i '' "s/;\(.*\)\([A-Za-z0-9_-]*\):\( *\)$FUNC: *\$/;\1\2-LABEL:\3$FUNC:/g" $TEMP done sed -i '' "s/;\(.*\)-LABEL-LABEL:/;\1-LABEL:/" $TEMP sed -i '' "s/;\(.*\)-NEXT-LABEL:/;\1-NEXT:/" $TEMP sed -i '' "s/;\(.*\)-NOT-LABEL:/;\1-NOT:/" $TEMP sed -i '' "s/;\(.*\)-DAG-LABEL:/;\1-DAG:/" $TEMP mv $TEMP $NAME fi done llvm-svn: 186280
2013-07-14 14:24:09 +08:00
; ARMT2-LABEL: t3:
[ARM] Materialise some boolean values to avoid a branch This patch combines some cases of ARMISD::CMOV for integers that arise in comparisons of the form a != b ? x : 0 a == b ? 0 : x and that currently (e.g. in Thumb1) are emitted as branches. Differential Revision: https://reviews.llvm.org/D34515 llvm-svn: 325323
2018-02-16 17:23:59 +08:00
; ARMT2: clz r0, r0
; ARMT2: lsr r0, r0, #5
Add conditional move of large immediate. llvm-svn: 118968
2010-11-13 10:25:14 +08:00
[ARM] Add tests for D34515 This is NFC and a preparatory step for D34515. Differential Revision: https://reviews.llvm.org/D41122 llvm-svn: 320795
2017-12-15 17:24:46 +08:00
; THUMB1-LABEL: t3:
[ARM] Materialise some boolean values to avoid a branch This patch combines some cases of ARMISD::CMOV for integers that arise in comparisons of the form a != b ? x : 0 a == b ? 0 : x and that currently (e.g. in Thumb1) are emitted as branches. Differential Revision: https://reviews.llvm.org/D34515 llvm-svn: 325323
2018-02-16 17:23:59 +08:00
; THUMB1: movs r1, #0
; THUMB1: subs r1, r1, r0
; THUMB1: adcs r0, r1
[ARM] Add tests for D34515 This is NFC and a preparatory step for D34515. Differential Revision: https://reviews.llvm.org/D41122 llvm-svn: 320795
2017-12-15 17:24:46 +08:00
Mass update to CodeGen tests to use CHECK-LABEL for labels corresponding to function definitions for more informative error messages. No functionality change and all updated tests passed locally. This update was done with the following bash script: find test/CodeGen -name "*.ll" | \ while read NAME; do echo "$NAME" if ! grep -q "^; *RUN: *llc.*debug" $NAME; then TEMP=`mktemp -t temp` cp $NAME $TEMP sed -n "s/^define [^@]*@\([A-Za-z0-9_]*\)(.*$/\1/p" < $NAME | \ while read FUNC; do sed -i '' "s/;\(.*\)\([A-Za-z0-9_-]*\):\( *\)$FUNC: *\$/;\1\2-LABEL:\3$FUNC:/g" $TEMP done sed -i '' "s/;\(.*\)-LABEL-LABEL:/;\1-LABEL:/" $TEMP sed -i '' "s/;\(.*\)-NEXT-LABEL:/;\1-NEXT:/" $TEMP sed -i '' "s/;\(.*\)-NOT-LABEL:/;\1-NOT:/" $TEMP sed -i '' "s/;\(.*\)-DAG-LABEL:/;\1-DAG:/" $TEMP mv $TEMP $NAME fi done llvm-svn: 186280
2013-07-14 14:24:09 +08:00
; THUMB2-LABEL: t3:
[ARM] Materialise some boolean values to avoid a branch This patch combines some cases of ARMISD::CMOV for integers that arise in comparisons of the form a != b ? x : 0 a == b ? 0 : x and that currently (e.g. in Thumb1) are emitted as branches. Differential Revision: https://reviews.llvm.org/D34515 llvm-svn: 325323
2018-02-16 17:23:59 +08:00
; THUMB2: clz r0, r0
; THUMB2: lsrs r0, r0, #5
Fix codegen of conditional move of immediates. We were not making use of the immediate forms of cmov instructions at all. llvm-svn: 89423
2009-11-20 08:54:03 +08:00
%0 = icmp eq i32 %a, 160
%1 = zext i1 %0 to i32
ret i32 %1
}
Fix an obvious typo which inverted an immediate. llvm-svn: 118951
2010-11-13 08:27:47 +08:00
define i32 @t4(i32 %a, i32 %b, i32 %x) nounwind {
entry:
Mass update to CodeGen tests to use CHECK-LABEL for labels corresponding to function definitions for more informative error messages. No functionality change and all updated tests passed locally. This update was done with the following bash script: find test/CodeGen -name "*.ll" | \ while read NAME; do echo "$NAME" if ! grep -q "^; *RUN: *llc.*debug" $NAME; then TEMP=`mktemp -t temp` cp $NAME $TEMP sed -n "s/^define [^@]*@\([A-Za-z0-9_]*\)(.*$/\1/p" < $NAME | \ while read FUNC; do sed -i '' "s/;\(.*\)\([A-Za-z0-9_-]*\):\( *\)$FUNC: *\$/;\1\2-LABEL:\3$FUNC:/g" $TEMP done sed -i '' "s/;\(.*\)-LABEL-LABEL:/;\1-LABEL:/" $TEMP sed -i '' "s/;\(.*\)-NEXT-LABEL:/;\1-NEXT:/" $TEMP sed -i '' "s/;\(.*\)-NOT-LABEL:/;\1-NOT:/" $TEMP sed -i '' "s/;\(.*\)-DAG-LABEL:/;\1-DAG:/" $TEMP mv $TEMP $NAME fi done llvm-svn: 186280
2013-07-14 14:24:09 +08:00
; ARM-LABEL: t4:
Fix an obvious typo which inverted an immediate. llvm-svn: 118951
2010-11-13 08:27:47 +08:00
; ARM: ldr
Implement ARMBaseInstrInfo::commuteInstruction() for MOVCCr. A MOVCCr instruction can be commuted by inverting the condition. This can help reduce register pressure and remove unnecessary copies in some cases. <rdar://problem/11182914> llvm-svn: 154033
2012-04-05 02:23:42 +08:00
; ARM: mov{{lt|ge}}
Fix an obvious typo which inverted an immediate. llvm-svn: 118951
2010-11-13 08:27:47 +08:00
Mass update to CodeGen tests to use CHECK-LABEL for labels corresponding to function definitions for more informative error messages. No functionality change and all updated tests passed locally. This update was done with the following bash script: find test/CodeGen -name "*.ll" | \ while read NAME; do echo "$NAME" if ! grep -q "^; *RUN: *llc.*debug" $NAME; then TEMP=`mktemp -t temp` cp $NAME $TEMP sed -n "s/^define [^@]*@\([A-Za-z0-9_]*\)(.*$/\1/p" < $NAME | \ while read FUNC; do sed -i '' "s/;\(.*\)\([A-Za-z0-9_-]*\):\( *\)$FUNC: *\$/;\1\2-LABEL:\3$FUNC:/g" $TEMP done sed -i '' "s/;\(.*\)-LABEL-LABEL:/;\1-LABEL:/" $TEMP sed -i '' "s/;\(.*\)-NEXT-LABEL:/;\1-NEXT:/" $TEMP sed -i '' "s/;\(.*\)-NOT-LABEL:/;\1-NOT:/" $TEMP sed -i '' "s/;\(.*\)-DAG-LABEL:/;\1-DAG:/" $TEMP mv $TEMP $NAME fi done llvm-svn: 186280
2013-07-14 14:24:09 +08:00
; ARMT2-LABEL: t4:
Fix a bunch of ARM tests to be register allocation independent. llvm-svn: 130800
2011-05-04 06:31:21 +08:00
; ARMT2: movwlt [[R0:r[0-9]+]], #65365
; ARMT2: movtlt [[R0]], #65365
Add conditional move of large immediate. llvm-svn: 118968
2010-11-13 10:25:14 +08:00
[ARM] Add tests for D34515 This is NFC and a preparatory step for D34515. Differential Revision: https://reviews.llvm.org/D41122 llvm-svn: 320795
2017-12-15 17:24:46 +08:00
; THUMB1-LABEL: t4:
; THUMB1: cmp r{{[0-9]+}}, r{{[0-9]+}}
; THUMB1: b{{lt|ge}}
Mass update to CodeGen tests to use CHECK-LABEL for labels corresponding to function definitions for more informative error messages. No functionality change and all updated tests passed locally. This update was done with the following bash script: find test/CodeGen -name "*.ll" | \ while read NAME; do echo "$NAME" if ! grep -q "^; *RUN: *llc.*debug" $NAME; then TEMP=`mktemp -t temp` cp $NAME $TEMP sed -n "s/^define [^@]*@\([A-Za-z0-9_]*\)(.*$/\1/p" < $NAME | \ while read FUNC; do sed -i '' "s/;\(.*\)\([A-Za-z0-9_-]*\):\( *\)$FUNC: *\$/;\1\2-LABEL:\3$FUNC:/g" $TEMP done sed -i '' "s/;\(.*\)-LABEL-LABEL:/;\1-LABEL:/" $TEMP sed -i '' "s/;\(.*\)-NEXT-LABEL:/;\1-NEXT:/" $TEMP sed -i '' "s/;\(.*\)-NOT-LABEL:/;\1-NOT:/" $TEMP sed -i '' "s/;\(.*\)-DAG-LABEL:/;\1-DAG:/" $TEMP mv $TEMP $NAME fi done llvm-svn: 186280
2013-07-14 14:24:09 +08:00
; THUMB2-LABEL: t4:
Thumb2 remove redundant ".w" suffix from t2MVNCCi pattern. llvm-svn: 143034
2011-10-27 01:28:15 +08:00
; THUMB2: mvnlt [[R0:r[0-9]+]], #11141290
Fix an obvious typo which inverted an immediate. llvm-svn: 118951
2010-11-13 08:27:47 +08:00
%0 = icmp slt i32 %a, %b
%1 = select i1 %0, i32 4283826005, i32 %x
ret i32 %1
}
Improve codegen for select's: if (x != 0) x = 1 if (x == 1) x = 1 Previous codegen looks like this: mov r1, r0 cmp r1, #1 mov r0, #0 moveq r0, #1 The naive lowering select between two different values. It should recognize the test is equality test so it's more a conditional move rather than a select: cmp r0, #1 movne r0, #0 rdar://9758317 llvm-svn: 135017
2011-07-13 08:42:17 +08:00
; rdar://9758317
define i32 @t5(i32 %a) nounwind {
entry:
Mass update to CodeGen tests to use CHECK-LABEL for labels corresponding to function definitions for more informative error messages. No functionality change and all updated tests passed locally. This update was done with the following bash script: find test/CodeGen -name "*.ll" | \ while read NAME; do echo "$NAME" if ! grep -q "^; *RUN: *llc.*debug" $NAME; then TEMP=`mktemp -t temp` cp $NAME $TEMP sed -n "s/^define [^@]*@\([A-Za-z0-9_]*\)(.*$/\1/p" < $NAME | \ while read FUNC; do sed -i '' "s/;\(.*\)\([A-Za-z0-9_-]*\):\( *\)$FUNC: *\$/;\1\2-LABEL:\3$FUNC:/g" $TEMP done sed -i '' "s/;\(.*\)-LABEL-LABEL:/;\1-LABEL:/" $TEMP sed -i '' "s/;\(.*\)-NEXT-LABEL:/;\1-NEXT:/" $TEMP sed -i '' "s/;\(.*\)-NOT-LABEL:/;\1-NOT:/" $TEMP sed -i '' "s/;\(.*\)-DAG-LABEL:/;\1-DAG:/" $TEMP mv $TEMP $NAME fi done llvm-svn: 186280
2013-07-14 14:24:09 +08:00
; ARM-LABEL: t5:
Improve codegen for select's: if (x != 0) x = 1 if (x == 1) x = 1 Previous codegen looks like this: mov r1, r0 cmp r1, #1 mov r0, #0 moveq r0, #1 The naive lowering select between two different values. It should recognize the test is equality test so it's more a conditional move rather than a select: cmp r0, #1 movne r0, #0 rdar://9758317 llvm-svn: 135017
2011-07-13 08:42:17 +08:00
; ARM-NOT: mov
[ARM] Materialise some boolean values to avoid a branch This patch combines some cases of ARMISD::CMOV for integers that arise in comparisons of the form a != b ? x : 0 a == b ? 0 : x and that currently (e.g. in Thumb1) are emitted as branches. Differential Revision: https://reviews.llvm.org/D34515 llvm-svn: 325323
2018-02-16 17:23:59 +08:00
; ARM: sub r0, r0, #1
Improve codegen for select's: if (x != 0) x = 1 if (x == 1) x = 1 Previous codegen looks like this: mov r1, r0 cmp r1, #1 mov r0, #0 moveq r0, #1 The naive lowering select between two different values. It should recognize the test is equality test so it's more a conditional move rather than a select: cmp r0, #1 movne r0, #0 rdar://9758317 llvm-svn: 135017
2011-07-13 08:42:17 +08:00
; ARM-NOT: mov
[ARM] Materialise some boolean values to avoid a branch This patch combines some cases of ARMISD::CMOV for integers that arise in comparisons of the form a != b ? x : 0 a == b ? 0 : x and that currently (e.g. in Thumb1) are emitted as branches. Differential Revision: https://reviews.llvm.org/D34515 llvm-svn: 325323
2018-02-16 17:23:59 +08:00
; ARM: rsbs r1, r0, #0
; ARM: adc r0, r0, r1
Improve codegen for select's: if (x != 0) x = 1 if (x == 1) x = 1 Previous codegen looks like this: mov r1, r0 cmp r1, #1 mov r0, #0 moveq r0, #1 The naive lowering select between two different values. It should recognize the test is equality test so it's more a conditional move rather than a select: cmp r0, #1 movne r0, #0 rdar://9758317 llvm-svn: 135017
2011-07-13 08:42:17 +08:00
[ARM] Add tests for D34515 This is NFC and a preparatory step for D34515. Differential Revision: https://reviews.llvm.org/D41122 llvm-svn: 320795
2017-12-15 17:24:46 +08:00
; THUMB1-LABEL: t5:
[ARM] Materialise some boolean values to avoid a branch This patch combines some cases of ARMISD::CMOV for integers that arise in comparisons of the form a != b ? x : 0 a == b ? 0 : x and that currently (e.g. in Thumb1) are emitted as branches. Differential Revision: https://reviews.llvm.org/D34515 llvm-svn: 325323
2018-02-16 17:23:59 +08:00
; THUMB1-NOT: bne
; THUMB1: movs r0, #0
; THUMB1: subs r0, r0, r1
; THUMB1: adcs r0, r1
[ARM] Add tests for D34515 This is NFC and a preparatory step for D34515. Differential Revision: https://reviews.llvm.org/D41122 llvm-svn: 320795
2017-12-15 17:24:46 +08:00
Mass update to CodeGen tests to use CHECK-LABEL for labels corresponding to function definitions for more informative error messages. No functionality change and all updated tests passed locally. This update was done with the following bash script: find test/CodeGen -name "*.ll" | \ while read NAME; do echo "$NAME" if ! grep -q "^; *RUN: *llc.*debug" $NAME; then TEMP=`mktemp -t temp` cp $NAME $TEMP sed -n "s/^define [^@]*@\([A-Za-z0-9_]*\)(.*$/\1/p" < $NAME | \ while read FUNC; do sed -i '' "s/;\(.*\)\([A-Za-z0-9_-]*\):\( *\)$FUNC: *\$/;\1\2-LABEL:\3$FUNC:/g" $TEMP done sed -i '' "s/;\(.*\)-LABEL-LABEL:/;\1-LABEL:/" $TEMP sed -i '' "s/;\(.*\)-NEXT-LABEL:/;\1-NEXT:/" $TEMP sed -i '' "s/;\(.*\)-NOT-LABEL:/;\1-NOT:/" $TEMP sed -i '' "s/;\(.*\)-DAG-LABEL:/;\1-DAG:/" $TEMP mv $TEMP $NAME fi done llvm-svn: 186280
2013-07-14 14:24:09 +08:00
; THUMB2-LABEL: t5:
Improve codegen for select's: if (x != 0) x = 1 if (x == 1) x = 1 Previous codegen looks like this: mov r1, r0 cmp r1, #1 mov r0, #0 moveq r0, #1 The naive lowering select between two different values. It should recognize the test is equality test so it's more a conditional move rather than a select: cmp r0, #1 movne r0, #0 rdar://9758317 llvm-svn: 135017
2011-07-13 08:42:17 +08:00
; THUMB2-NOT: mov
[ARM] Materialise some boolean values to avoid a branch This patch combines some cases of ARMISD::CMOV for integers that arise in comparisons of the form a != b ? x : 0 a == b ? 0 : x and that currently (e.g. in Thumb1) are emitted as branches. Differential Revision: https://reviews.llvm.org/D34515 llvm-svn: 325323
2018-02-16 17:23:59 +08:00
; THUMB2: subs r0, #1
; THUMB2: clz r0, r0
; THUMB2: lsrs r0, r0, #5
Improve codegen for select's: if (x != 0) x = 1 if (x == 1) x = 1 Previous codegen looks like this: mov r1, r0 cmp r1, #1 mov r0, #0 moveq r0, #1 The naive lowering select between two different values. It should recognize the test is equality test so it's more a conditional move rather than a select: cmp r0, #1 movne r0, #0 rdar://9758317 llvm-svn: 135017
2011-07-13 08:42:17 +08:00
%cmp = icmp eq i32 %a, 1
%conv = zext i1 %cmp to i32
ret i32 %conv
}
define i32 @t6(i32 %a) nounwind {
entry:
Mass update to CodeGen tests to use CHECK-LABEL for labels corresponding to function definitions for more informative error messages. No functionality change and all updated tests passed locally. This update was done with the following bash script: find test/CodeGen -name "*.ll" | \ while read NAME; do echo "$NAME" if ! grep -q "^; *RUN: *llc.*debug" $NAME; then TEMP=`mktemp -t temp` cp $NAME $TEMP sed -n "s/^define [^@]*@\([A-Za-z0-9_]*\)(.*$/\1/p" < $NAME | \ while read FUNC; do sed -i '' "s/;\(.*\)\([A-Za-z0-9_-]*\):\( *\)$FUNC: *\$/;\1\2-LABEL:\3$FUNC:/g" $TEMP done sed -i '' "s/;\(.*\)-LABEL-LABEL:/;\1-LABEL:/" $TEMP sed -i '' "s/;\(.*\)-NEXT-LABEL:/;\1-NEXT:/" $TEMP sed -i '' "s/;\(.*\)-NOT-LABEL:/;\1-NOT:/" $TEMP sed -i '' "s/;\(.*\)-DAG-LABEL:/;\1-DAG:/" $TEMP mv $TEMP $NAME fi done llvm-svn: 186280
2013-07-14 14:24:09 +08:00
; ARM-LABEL: t6:
Improve codegen for select's: if (x != 0) x = 1 if (x == 1) x = 1 Previous codegen looks like this: mov r1, r0 cmp r1, #1 mov r0, #0 moveq r0, #1 The naive lowering select between two different values. It should recognize the test is equality test so it's more a conditional move rather than a select: cmp r0, #1 movne r0, #0 rdar://9758317 llvm-svn: 135017
2011-07-13 08:42:17 +08:00
; ARM-NOT: mov
; ARM: cmp r0, #0
; ARM: movne r0, #1
[ARM] Add tests for D34515 This is NFC and a preparatory step for D34515. Differential Revision: https://reviews.llvm.org/D41122 llvm-svn: 320795
2017-12-15 17:24:46 +08:00
; THUMB1-LABEL: t6:
; THUMB1: cmp r{{[0-9]+}}, #0
; THUMB1: bne
Mass update to CodeGen tests to use CHECK-LABEL for labels corresponding to function definitions for more informative error messages. No functionality change and all updated tests passed locally. This update was done with the following bash script: find test/CodeGen -name "*.ll" | \ while read NAME; do echo "$NAME" if ! grep -q "^; *RUN: *llc.*debug" $NAME; then TEMP=`mktemp -t temp` cp $NAME $TEMP sed -n "s/^define [^@]*@\([A-Za-z0-9_]*\)(.*$/\1/p" < $NAME | \ while read FUNC; do sed -i '' "s/;\(.*\)\([A-Za-z0-9_-]*\):\( *\)$FUNC: *\$/;\1\2-LABEL:\3$FUNC:/g" $TEMP done sed -i '' "s/;\(.*\)-LABEL-LABEL:/;\1-LABEL:/" $TEMP sed -i '' "s/;\(.*\)-NEXT-LABEL:/;\1-NEXT:/" $TEMP sed -i '' "s/;\(.*\)-NOT-LABEL:/;\1-NOT:/" $TEMP sed -i '' "s/;\(.*\)-DAG-LABEL:/;\1-DAG:/" $TEMP mv $TEMP $NAME fi done llvm-svn: 186280
2013-07-14 14:24:09 +08:00
; THUMB2-LABEL: t6:
Improve codegen for select's: if (x != 0) x = 1 if (x == 1) x = 1 Previous codegen looks like this: mov r1, r0 cmp r1, #1 mov r0, #0 moveq r0, #1 The naive lowering select between two different values. It should recognize the test is equality test so it's more a conditional move rather than a select: cmp r0, #1 movne r0, #0 rdar://9758317 llvm-svn: 135017
2011-07-13 08:42:17 +08:00
; THUMB2-NOT: mov
; THUMB2: cmp r0, #0
; THUMB2: it ne
; THUMB2: movne r0, #1
%tobool = icmp ne i32 %a, 0
%lnot.ext = zext i1 %tobool to i32
ret i32 %lnot.ext
}
[ARM] Add tests for D34515 This is NFC and a preparatory step for D34515. Differential Revision: https://reviews.llvm.org/D41122 llvm-svn: 320795
2017-12-15 17:24:46 +08:00
define i32 @t7(i32 %a, i32 %b) nounwind readnone {
entry:
; ARM-LABEL: t7:
[ARM] Materialise some boolean values to avoid a branch This patch combines some cases of ARMISD::CMOV for integers that arise in comparisons of the form a != b ? x : 0 a == b ? 0 : x and that currently (e.g. in Thumb1) are emitted as branches. Differential Revision: https://reviews.llvm.org/D34515 llvm-svn: 325323
2018-02-16 17:23:59 +08:00
; ARM: subs r0, r0, r1
; ARM: movne r0, #1
; ARM: lsl r0, r0, #2
[ARM] Add tests for D34515 This is NFC and a preparatory step for D34515. Differential Revision: https://reviews.llvm.org/D41122 llvm-svn: 320795
2017-12-15 17:24:46 +08:00
; ARMT2-LABEL: t7:
[ARM] Materialise some boolean values to avoid a branch This patch combines some cases of ARMISD::CMOV for integers that arise in comparisons of the form a != b ? x : 0 a == b ? 0 : x and that currently (e.g. in Thumb1) are emitted as branches. Differential Revision: https://reviews.llvm.org/D34515 llvm-svn: 325323
2018-02-16 17:23:59 +08:00
; ARMT2: subs r0, r0, r1
; ARMT2: movwne r0, #1
; ARMT2: lsl r0, r0, #2
[ARM] Add tests for D34515 This is NFC and a preparatory step for D34515. Differential Revision: https://reviews.llvm.org/D41122 llvm-svn: 320795
2017-12-15 17:24:46 +08:00
; THUMB1-LABEL: t7:
[ARM] Materialise some boolean values to avoid a branch This patch combines some cases of ARMISD::CMOV for integers that arise in comparisons of the form a != b ? x : 0 a == b ? 0 : x and that currently (e.g. in Thumb1) are emitted as branches. Differential Revision: https://reviews.llvm.org/D34515 llvm-svn: 325323
2018-02-16 17:23:59 +08:00
; THUMB1: subs r0, r0, r1
; THUMB1: subs r1, r0, #1
; THUMB1: sbcs r0, r1
; THUMB1: lsls r0, r0, #2
[ARM] Add tests for D34515 This is NFC and a preparatory step for D34515. Differential Revision: https://reviews.llvm.org/D41122 llvm-svn: 320795
2017-12-15 17:24:46 +08:00
; THUMB2-LABEL: t7:
[ARM] Materialise some boolean values to avoid a branch This patch combines some cases of ARMISD::CMOV for integers that arise in comparisons of the form a != b ? x : 0 a == b ? 0 : x and that currently (e.g. in Thumb1) are emitted as branches. Differential Revision: https://reviews.llvm.org/D34515 llvm-svn: 325323
2018-02-16 17:23:59 +08:00
; THUMB2: subs r0, r0, r1
; THUMB2: it ne
; THUMB2: movne r0, #1
; THUMB2: lsls r0, r0, #2
[ARM] Add tests for D34515 This is NFC and a preparatory step for D34515. Differential Revision: https://reviews.llvm.org/D41122 llvm-svn: 320795
2017-12-15 17:24:46 +08:00
%0 = icmp ne i32 %a, %b
%1 = select i1 %0, i32 4, i32 0
ret i32 %1
}
define void @t8(i32 %a) {
entry:
; ARM scheduler emits icmp/zext before both calls, so isn't relevant
; ARMT2-LABEL: t8:
[ARM] Materialise some boolean values to avoid a branch This patch combines some cases of ARMISD::CMOV for integers that arise in comparisons of the form a != b ? x : 0 a == b ? 0 : x and that currently (e.g. in Thumb1) are emitted as branches. Differential Revision: https://reviews.llvm.org/D34515 llvm-svn: 325323
2018-02-16 17:23:59 +08:00
; ARMT2: bl t7
; ARMT2: mov r1, r0
; ARMT2: sub r0, r4, #5
; ARMT2: clz r0, r0
; ARMT2: lsr r0, r0, #5
[ARM] Add tests for D34515 This is NFC and a preparatory step for D34515. Differential Revision: https://reviews.llvm.org/D41122 llvm-svn: 320795
2017-12-15 17:24:46 +08:00
; THUMB1-LABEL: t8:
[ARM] Materialise some boolean values to avoid a branch This patch combines some cases of ARMISD::CMOV for integers that arise in comparisons of the form a != b ? x : 0 a == b ? 0 : x and that currently (e.g. in Thumb1) are emitted as branches. Differential Revision: https://reviews.llvm.org/D34515 llvm-svn: 325323
2018-02-16 17:23:59 +08:00
; THUMB1: bl t7
; THUMB1: mov r1, r0
; THUMB1: subs r2, r4, #5
; THUMB1: movs r0, #0
; THUMB1: subs r0, r0, r2
; THUMB1: adcs r0, r2
[ARM] Add tests for D34515 This is NFC and a preparatory step for D34515. Differential Revision: https://reviews.llvm.org/D41122 llvm-svn: 320795
2017-12-15 17:24:46 +08:00
; THUMB2-LABEL: t8:
[ARM] Materialise some boolean values to avoid a branch This patch combines some cases of ARMISD::CMOV for integers that arise in comparisons of the form a != b ? x : 0 a == b ? 0 : x and that currently (e.g. in Thumb1) are emitted as branches. Differential Revision: https://reviews.llvm.org/D34515 llvm-svn: 325323
2018-02-16 17:23:59 +08:00
; THUMB2: bl t7
; THUMB2: mov r1, r0
; THUMB2: subs r0, r4, #5
; THUMB2: clz r0, r0
; THUMB2: lsrs r0, r0, #5
[ARM] Add tests for D34515 This is NFC and a preparatory step for D34515. Differential Revision: https://reviews.llvm.org/D41122 llvm-svn: 320795
2017-12-15 17:24:46 +08:00
%cmp = icmp eq i32 %a, 5
%conv = zext i1 %cmp to i32
%call = tail call i32 @t7(i32 9, i32 %a)
tail call i32 @t7(i32 %conv, i32 %call)
ret void
}
define void @t9(i8* %a, i8 %b) {
entry:
; ARM scheduler emits icmp/zext before both calls, so isn't relevant
; ARMT2-LABEL: t9:
[ARM] Materialise some boolean values to avoid a branch This patch combines some cases of ARMISD::CMOV for integers that arise in comparisons of the form a != b ? x : 0 a == b ? 0 : x and that currently (e.g. in Thumb1) are emitted as branches. Differential Revision: https://reviews.llvm.org/D34515 llvm-svn: 325323
2018-02-16 17:23:59 +08:00
; ARMT2: bl f
; ARMT2: uxtb r0, r4
; ARMT2: cmp r0, r0
; ARMT2: add r1, r4, #1
; ARMT2: mov r2, r0
; ARMT2: add r2, r2, #1
; ARMT2: add r1, r1, #1
; ARMT2: uxtb r3, r2
; ARMT2: cmp r3, r0
[ARM] Add tests for D34515 This is NFC and a preparatory step for D34515. Differential Revision: https://reviews.llvm.org/D41122 llvm-svn: 320795
2017-12-15 17:24:46 +08:00
; THUMB1-LABEL: t9:
[ARM] Materialise some boolean values to avoid a branch This patch combines some cases of ARMISD::CMOV for integers that arise in comparisons of the form a != b ? x : 0 a == b ? 0 : x and that currently (e.g. in Thumb1) are emitted as branches. Differential Revision: https://reviews.llvm.org/D34515 llvm-svn: 325323
2018-02-16 17:23:59 +08:00
; THUMB1: bl f
; THUMB1: sxtb r1, r4
; THUMB1: uxtb r0, r1
; THUMB1: cmp r0, r0
; THUMB1: adds r1, r1, #1
; THUMB1: mov r2, r0
; THUMB1: adds r1, r1, #1
; THUMB1: adds r2, r2, #1
; THUMB1: uxtb r3, r2
; THUMB1: cmp r3, r0
[ARM] Add tests for D34515 This is NFC and a preparatory step for D34515. Differential Revision: https://reviews.llvm.org/D41122 llvm-svn: 320795
2017-12-15 17:24:46 +08:00
; THUMB2-LABEL: t9:
[ARM] Materialise some boolean values to avoid a branch This patch combines some cases of ARMISD::CMOV for integers that arise in comparisons of the form a != b ? x : 0 a == b ? 0 : x and that currently (e.g. in Thumb1) are emitted as branches. Differential Revision: https://reviews.llvm.org/D34515 llvm-svn: 325323
2018-02-16 17:23:59 +08:00
; THUMB2: bl f
; THUMB2: uxtb r0, r4
; THUMB2: cmp r0, r0
; THUMB2: adds r1, r4, #1
; THUMB2: mov r2, r0
; THUMB2: adds r2, #1
; THUMB2: adds r1, #1
; THUMB2: uxtb r3, r2
; THUMB2: cmp r3, r0
[ARM] Add tests for D34515 This is NFC and a preparatory step for D34515. Differential Revision: https://reviews.llvm.org/D41122 llvm-svn: 320795
2017-12-15 17:24:46 +08:00
%0 = load i8, i8* %a
%conv = sext i8 %0 to i32
%conv119 = zext i8 %0 to i32
%conv522 = and i32 %conv, 255
%cmp723 = icmp eq i32 %conv522, %conv119
tail call void @f(i1 zeroext %cmp723)
br i1 %cmp723, label %while.body, label %while.end
while.body: ; preds = %entry, %while.body
%ref.025 = phi i8 [ %inc9, %while.body ], [ %0, %entry ]
%in.024 = phi i32 [ %inc, %while.body ], [ %conv, %entry ]
%inc = add i32 %in.024, 1
%inc9 = add i8 %ref.025, 1
%conv1 = zext i8 %inc9 to i32
%cmp = icmp slt i32 %conv1, %conv119
%conv5 = and i32 %inc, 255
br i1 %cmp, label %while.body, label %while.end
while.end:
ret void
}
declare void @f(i1 zeroext)
define i1 @t10() {
entry:
%q = alloca i32
%p = alloca i32
store i32 -3, i32* %q
store i32 -8, i32* %p
%0 = load i32, i32* %q
%1 = load i32, i32* %p
%div = sdiv i32 %0, %1
%mul = mul nsw i32 %div, %1
%rem = srem i32 %0, %1
%add = add nsw i32 %mul, %rem
%cmp = icmp eq i32 %add, %0
ret i1 %cmp
; ARM-LABEL: t10:
[ARM] Materialise some boolean values to avoid a branch This patch combines some cases of ARMISD::CMOV for integers that arise in comparisons of the form a != b ? x : 0 a == b ? 0 : x and that currently (e.g. in Thumb1) are emitted as branches. Differential Revision: https://reviews.llvm.org/D34515 llvm-svn: 325323
2018-02-16 17:23:59 +08:00
; ARM: rsbs r1, r0, #0
; ARM: adc r0, r0, r1
[ARM] Add tests for D34515 This is NFC and a preparatory step for D34515. Differential Revision: https://reviews.llvm.org/D41122 llvm-svn: 320795
2017-12-15 17:24:46 +08:00
; ARMT2-LABEL: t10:
[ARM] Materialise some boolean values to avoid a branch This patch combines some cases of ARMISD::CMOV for integers that arise in comparisons of the form a != b ? x : 0 a == b ? 0 : x and that currently (e.g. in Thumb1) are emitted as branches. Differential Revision: https://reviews.llvm.org/D34515 llvm-svn: 325323
2018-02-16 17:23:59 +08:00
; ARMT2: clz r0, r0
; ARMT2: lsr r0, r0, #5
[ARM] Add tests for D34515 This is NFC and a preparatory step for D34515. Differential Revision: https://reviews.llvm.org/D41122 llvm-svn: 320795
2017-12-15 17:24:46 +08:00
; THUMB1-LABEL: t10:
[ARM] Materialise some boolean values to avoid a branch This patch combines some cases of ARMISD::CMOV for integers that arise in comparisons of the form a != b ? x : 0 a == b ? 0 : x and that currently (e.g. in Thumb1) are emitted as branches. Differential Revision: https://reviews.llvm.org/D34515 llvm-svn: 325323
2018-02-16 17:23:59 +08:00
; THUMB1: movs r0, #0
; THUMB1: subs r0, r0, r1
; THUMB1: adcs r0, r1
[ARM] Add tests for D34515 This is NFC and a preparatory step for D34515. Differential Revision: https://reviews.llvm.org/D41122 llvm-svn: 320795
2017-12-15 17:24:46 +08:00
; THUMB2-LABEL: t10:
[ARM] Materialise some boolean values to avoid a branch This patch combines some cases of ARMISD::CMOV for integers that arise in comparisons of the form a != b ? x : 0 a == b ? 0 : x and that currently (e.g. in Thumb1) are emitted as branches. Differential Revision: https://reviews.llvm.org/D34515 llvm-svn: 325323
2018-02-16 17:23:59 +08:00
; THUMB2: clz r0, r0
; THUMB2: lsrs r0, r0, #5
[ARM] Add tests for D34515 This is NFC and a preparatory step for D34515. Differential Revision: https://reviews.llvm.org/D41122 llvm-svn: 320795
2017-12-15 17:24:46 +08:00
; V8MBASE-LABEL: t10:
; V8MBASE-NOT: movs r0, #0
; V8MBASE: movs r0, #7
}
define i1 @t11() {
entry:
%bit = alloca i32
%load = load i32, i32* %bit
%clear = and i32 %load, -4096
%set = or i32 %clear, 33
store i32 %set, i32* %bit
%load1 = load i32, i32* %bit
%clear2 = and i32 %load1, -33550337
%set3 = or i32 %clear2, 40960
%clear5 = and i32 %set3, 4095
%rem = srem i32 %clear5, 10
%clear9 = and i32 %set3, -4096
%set10 = or i32 %clear9, %rem
store i32 %set10, i32* %bit
%clear12 = and i32 %set10, 4095
%cmp = icmp eq i32 %clear12, 3
ret i1 %cmp
; ARM-LABEL: t11:
[ARM] Materialise some boolean values to avoid a branch This patch combines some cases of ARMISD::CMOV for integers that arise in comparisons of the form a != b ? x : 0 a == b ? 0 : x and that currently (e.g. in Thumb1) are emitted as branches. Differential Revision: https://reviews.llvm.org/D34515 llvm-svn: 325323
2018-02-16 17:23:59 +08:00
; ARM: rsbs r1, r0, #0
; ARM: adc r0, r0, r1
[ARM] Add tests for D34515 This is NFC and a preparatory step for D34515. Differential Revision: https://reviews.llvm.org/D41122 llvm-svn: 320795
2017-12-15 17:24:46 +08:00
; ARMT2-LABEL: t11:
[ARM] Materialise some boolean values to avoid a branch This patch combines some cases of ARMISD::CMOV for integers that arise in comparisons of the form a != b ? x : 0 a == b ? 0 : x and that currently (e.g. in Thumb1) are emitted as branches. Differential Revision: https://reviews.llvm.org/D34515 llvm-svn: 325323
2018-02-16 17:23:59 +08:00
; ARMT2: clz r0, r0
; ARMT2: lsr r0, r0, #5
[ARM] Add tests for D34515 This is NFC and a preparatory step for D34515. Differential Revision: https://reviews.llvm.org/D41122 llvm-svn: 320795
2017-12-15 17:24:46 +08:00
; THUMB1-LABEL: t11:
; THUMB1-NOT: movs r0, #0
; THUMB1: movs r0, #5
; THUMB2-LABEL: t11:
[ARM] Materialise some boolean values to avoid a branch This patch combines some cases of ARMISD::CMOV for integers that arise in comparisons of the form a != b ? x : 0 a == b ? 0 : x and that currently (e.g. in Thumb1) are emitted as branches. Differential Revision: https://reviews.llvm.org/D34515 llvm-svn: 325323
2018-02-16 17:23:59 +08:00
; THUMB2: clz r0, r0
; THUMB2: lsrs r0, r0, #5
[ARM] Add tests for D34515 This is NFC and a preparatory step for D34515. Differential Revision: https://reviews.llvm.org/D41122 llvm-svn: 320795
2017-12-15 17:24:46 +08:00
; V8MBASE-LABEL: t11:
; V8MBASE-NOT: movs r0, #0
[ARM] Materialise some boolean values to avoid a branch This patch combines some cases of ARMISD::CMOV for integers that arise in comparisons of the form a != b ? x : 0 a == b ? 0 : x and that currently (e.g. in Thumb1) are emitted as branches. Differential Revision: https://reviews.llvm.org/D34515 llvm-svn: 325323
2018-02-16 17:23:59 +08:00
; V8MBASE: movw r0, #40960
[ARM] Add tests for D34515 This is NFC and a preparatory step for D34515. Differential Revision: https://reviews.llvm.org/D41122 llvm-svn: 320795
2017-12-15 17:24:46 +08:00
}