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llvm-project/llvm/test/CodeGen/Mips/fcopysign-f32-f64.ll

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[mips] Do not use SLL for ANY_EXTEND nodes as the high bits are undefined. Reviewers: dsanders Subscribers: dsanders, llvm-commits Differential Revision: http://reviews.llvm.org/D15420 llvm-svn: 262230
2016-02-29 23:58:12 +08:00
; RUN: llc < %s -march=mips64el -mcpu=mips4 -target-abi=n64 | \
; RUN: FileCheck %s -check-prefix=ALL -check-prefix=64
; RUN: llc < %s -march=mips64el -mcpu=mips64 -target-abi=n64 | \
; RUN: FileCheck %s -check-prefix=ALL -check-prefix=64
; RUN: llc < %s -march=mips64el -mcpu=mips64r2 -target-abi=n64 | \
; RUN: FileCheck %s -check-prefix=ALL -check-prefix=64R2
Fix bugs in lowering of FCOPYSIGN nodes. - FCOPYSIGN nodes that have operands of different types were not handled. - Different code was generated depending on the endianness of the target. Additionally, code is added that emits INS and EXT instructions, if they are supported by target (they are R2 instructions). llvm-svn: 154540
2012-04-12 06:13:04 +08:00
declare double @copysign(double, double) nounwind readnone
declare float @copysignf(float, float) nounwind readnone
define float @func2(float %d, double %f) nounwind readnone {
entry:
[mips] Do not use SLL for ANY_EXTEND nodes as the high bits are undefined. Reviewers: dsanders Subscribers: dsanders, llvm-commits Differential Revision: http://reviews.llvm.org/D15420 llvm-svn: 262230
2016-02-29 23:58:12 +08:00
; ALL-LABEL: func2:
[mips] Implement MipsTargetMachine::getInstrItineraryData(). llvm-svn: 186227
2013-07-13 07:33:22 +08:00
; 64-DAG: lui $[[T0:[0-9]+]], 32767
; 64-DAG: ori $[[MSK0:[0-9]+]], $[[T0]], 65535
; 64-DAG: and $[[AND0:[0-9]+]], ${{[0-9]+}}, $[[MSK0]]
; 64-DAG: dsrl $[[DSRL:[0-9]+]], ${{[0-9]+}}, 63
; 64-DAG: sll $[[SLL0:[0-9]+]], $[[DSRL]], 0
; 64-DAG: sll $[[SLL1:[0-9]+]], $[[SLL0]], 31
; 64: or $[[OR:[0-9]+]], $[[AND0]], $[[SLL1]]
; 64: mtc1 $[[OR]], $f0
Fix bugs in lowering of FCOPYSIGN nodes. - FCOPYSIGN nodes that have operands of different types were not handled. - Different code was generated depending on the endianness of the target. Additionally, code is added that emits INS and EXT instructions, if they are supported by target (they are R2 instructions). llvm-svn: 154540
2012-04-12 06:13:04 +08:00
[mips] Make isel select the correct DEXT variant up front. Summary: Previously, it would always select DEXT and substitute any invalid matches for DEXTU/DEXTM during MipsMCCodeEmitter::encodeInstruction(). This works but causes problems when adding range checked immediates to IAS. Now isel selects the correct variant up front. Reviewers: vkalintiris Subscribers: dsanders, llvm-commits Differential Revision: http://reviews.llvm.org/D16810 llvm-svn: 262229
2016-02-29 23:26:54 +08:00
; 64R2: dextu ${{[0-9]+}}, ${{[0-9]+}}, 63, 1
Fix bugs in lowering of FCOPYSIGN nodes. - FCOPYSIGN nodes that have operands of different types were not handled. - Different code was generated depending on the endianness of the target. Additionally, code is added that emits INS and EXT instructions, if they are supported by target (they are R2 instructions). llvm-svn: 154540
2012-04-12 06:13:04 +08:00
; 64R2: ins $[[INS:[0-9]+]], ${{[0-9]+}}, 31, 1
; 64R2: mtc1 $[[INS]], $f0
%add = fadd float %d, 1.000000e+00
%conv = fptrunc double %f to float
%call = tail call float @copysignf(float %add, float %conv) nounwind readnone
ret float %call
}
define double @func3(double %d, float %f) nounwind readnone {
entry:
[mips] Do not use SLL for ANY_EXTEND nodes as the high bits are undefined. Reviewers: dsanders Subscribers: dsanders, llvm-commits Differential Revision: http://reviews.llvm.org/D15420 llvm-svn: 262230
2016-02-29 23:58:12 +08:00
; ALL-LABEL: func3:
; 64-DAG: mfc1 $[[MFC:[0-9]+]], $f13
; 64-DAG: srl $[[SRL:[0-9]+]], $[[MFC:[0-9]+]], 31
; 64: dsll $[[DSLL:[0-9]+]], $[[SRL]], 63
; 64-DAG: daddiu $[[R1:[0-9]+]], $zero, 1
; 64-DAG: dsll $[[R2:[0-9]+]], $[[R1]], 63
; 64-DAG: daddiu $[[R3:[0-9]+]], $[[R2]], -1
; 64-DAG: dmfc1 $[[R0:[0-9]+]], ${{.*}}
; 64: and $[[AND0:[0-9]+]], $[[R0]], $[[R3]]
; 64: or $[[OR:[0-9]+]], $[[AND0]], $[[DSLL]]
; 64: dmtc1 $[[OR]], $f0
Fix bugs in lowering of FCOPYSIGN nodes. - FCOPYSIGN nodes that have operands of different types were not handled. - Different code was generated depending on the endianness of the target. Additionally, code is added that emits INS and EXT instructions, if they are supported by target (they are R2 instructions). llvm-svn: 154540
2012-04-12 06:13:04 +08:00
; 64R2: ext ${{[0-9]+}}, ${{[0-9]+}}, 31, 1
; 64R2: dins $[[INS:[0-9]+]], ${{[0-9]+}}, 63, 1
; 64R2: dmtc1 $[[INS]], $f0
%add = fadd double %d, 1.000000e+00
%conv = fpext float %f to double
%call = tail call double @copysign(double %add, double %conv) nounwind readnone
ret double %call
}