2016-01-05 11:40:16 +08:00
|
|
|
; RUN: llc -march=amdgcn -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=GCN-NOHSA -check-prefix=SI %s
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|
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|
|
; RUN: llc -march=amdgcn -mcpu=bonaire -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=GCN-NOHSA -check-prefix=CI %s
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|
|
|
|
; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=bonaire -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=CI --check-prefix=GCN-HSA %s
|
2015-09-29 04:54:32 +08:00
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|
2016-02-11 14:02:01 +08:00
|
|
|
declare i32 @llvm.amdgcn.workitem.id.x() #0
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|
declare i32 @llvm.amdgcn.workitem.id.y() #0
|
2014-03-21 23:51:54 +08:00
|
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|
|
|
; In this test both the pointer and the offset operands to the
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|
|
; BUFFER_LOAD instructions end up being stored in vgprs. This
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; requires us to add the pointer and offset together, store the
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; result in the offset operand (vaddr), and then store 0 in an
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; sgpr register pair and use that for the pointer operand
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; (low 64-bits of srsrc).
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|
2015-09-29 04:54:32 +08:00
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|
|
; GCN-LABEL: {{^}}mubuf:
|
2014-03-21 23:51:57 +08:00
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|
2014-11-05 22:50:53 +08:00
|
|
|
; Make sure we aren't using VGPRs for the source operand of s_mov_b64
|
2015-09-29 04:54:32 +08:00
|
|
|
; GCN-NOT: s_mov_b64 s[{{[0-9]+:[0-9]+}}], v
|
2014-03-21 23:51:57 +08:00
|
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|
; Make sure we aren't using VGPR's for the srsrc operand of BUFFER_LOAD_*
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; instructions
|
2016-01-05 11:40:16 +08:00
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; GCN-NOHSA: buffer_load_ubyte v{{[0-9]+}}, v[{{[0-9]+:[0-9]+}}], s[{{[0-9]+:[0-9]+}}], 0 addr64
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|
; GCN-NOHSA: buffer_load_ubyte v{{[0-9]+}}, v[{{[0-9]+:[0-9]+}}], s[{{[0-9]+:[0-9]+}}], 0 addr64
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|
; GCN-HSA: flat_load_ubyte v{{[0-9]+}}, v[{{[0-9]+:[0-9]+}}
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; GCN-HSA: flat_load_ubyte v{{[0-9]+}}, v[{{[0-9]+:[0-9]+}}
|
2015-09-29 04:54:32 +08:00
|
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|
|
define void @mubuf(i32 addrspace(1)* %out, i8 addrspace(1)* %in) #1 {
|
2014-03-21 23:51:54 +08:00
|
|
|
entry:
|
2016-02-11 14:02:01 +08:00
|
|
|
%tmp = call i32 @llvm.amdgcn.workitem.id.x()
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|
%tmp1 = call i32 @llvm.amdgcn.workitem.id.y()
|
2015-09-29 04:54:32 +08:00
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|
|
%tmp2 = sext i32 %tmp to i64
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|
%tmp3 = sext i32 %tmp1 to i64
|
2014-03-21 23:51:54 +08:00
|
|
|
br label %loop
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|
2015-09-29 04:54:32 +08:00
|
|
|
loop: ; preds = %loop, %entry
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|
%tmp4 = phi i64 [ 0, %entry ], [ %tmp5, %loop ]
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|
%tmp5 = add i64 %tmp2, %tmp4
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|
%tmp6 = getelementptr i8, i8 addrspace(1)* %in, i64 %tmp5
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|
%tmp7 = load i8, i8 addrspace(1)* %tmp6, align 1
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|
%tmp8 = or i64 %tmp5, 1
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|
%tmp9 = getelementptr i8, i8 addrspace(1)* %in, i64 %tmp8
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|
%tmp10 = load i8, i8 addrspace(1)* %tmp9, align 1
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|
|
%tmp11 = add i8 %tmp7, %tmp10
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|
|
%tmp12 = sext i8 %tmp11 to i32
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|
|
store i32 %tmp12, i32 addrspace(1)* %out
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|
%tmp13 = icmp slt i64 %tmp5, 10
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|
|
br i1 %tmp13, label %loop, label %done
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|
|
done: ; preds = %loop
|
2014-03-21 23:51:54 +08:00
|
|
|
ret void
|
|
|
|
|
}
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|
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|
|
2014-04-30 23:31:29 +08:00
|
|
|
; Test moving an SMRD instruction to the VALU
|
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|
2015-09-29 04:54:32 +08:00
|
|
|
; GCN-LABEL: {{^}}smrd_valu:
|
2016-02-20 08:37:25 +08:00
|
|
|
; SI: s_movk_i32 [[OFFSET:s[0-9]+]], 0x2ee0
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|
|
; GCN: v_readfirstlane_b32 s[[PTR_LO:[0-9]+]], v{{[0-9]+}}
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|
|
; GCN: v_readfirstlane_b32 s[[PTR_HI:[0-9]+]], v{{[0-9]+}}
|
2016-04-13 02:40:43 +08:00
|
|
|
; SI-NEXT: s_nop
|
2016-02-20 08:37:25 +08:00
|
|
|
; SI: s_load_dword [[OUT:s[0-9]+]], s{{\[}}[[PTR_LO]]:[[PTR_HI]]{{\]}}, [[OFFSET]]
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|
; CI: s_load_dword [[OUT:s[0-9]+]], s{{\[}}[[PTR_LO]]:[[PTR_HI]]{{\]}}, 0xbb8
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|
; GCN: v_mov_b32_e32 [[V_OUT:v[0-9]+]], [[OUT]]
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|
; GCN-NOHSA: buffer_store_dword [[V_OUT]]
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|
; GCN-HSA: flat_store_dword {{.*}}, [[V_OUT]]
|
2015-09-29 04:54:32 +08:00
|
|
|
define void @smrd_valu(i32 addrspace(2)* addrspace(1)* %in, i32 %a, i32 %b, i32 addrspace(1)* %out) #1 {
|
2014-04-30 23:31:29 +08:00
|
|
|
entry:
|
2015-09-29 04:54:32 +08:00
|
|
|
%tmp = icmp ne i32 %a, 0
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|
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|
|
br i1 %tmp, label %if, label %else
|
2014-04-30 23:31:29 +08:00
|
|
|
|
2015-09-29 04:54:32 +08:00
|
|
|
if: ; preds = %entry
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|
|
%tmp1 = load i32 addrspace(2)*, i32 addrspace(2)* addrspace(1)* %in
|
2014-04-30 23:31:29 +08:00
|
|
|
br label %endif
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|
|
|
|
|
2015-09-29 04:54:32 +08:00
|
|
|
else: ; preds = %entry
|
|
|
|
|
%tmp2 = getelementptr i32 addrspace(2)*, i32 addrspace(2)* addrspace(1)* %in
|
|
|
|
|
%tmp3 = load i32 addrspace(2)*, i32 addrspace(2)* addrspace(1)* %tmp2
|
2014-04-30 23:31:29 +08:00
|
|
|
br label %endif
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|
|
|
2015-09-29 04:54:32 +08:00
|
|
|
endif: ; preds = %else, %if
|
|
|
|
|
%tmp4 = phi i32 addrspace(2)* [ %tmp1, %if ], [ %tmp3, %else ]
|
|
|
|
|
%tmp5 = getelementptr i32, i32 addrspace(2)* %tmp4, i32 3000
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|
|
|
|
%tmp6 = load i32, i32 addrspace(2)* %tmp5
|
|
|
|
|
store i32 %tmp6, i32 addrspace(1)* %out
|
2014-04-30 23:31:29 +08:00
|
|
|
ret void
|
|
|
|
|
}
|
2014-05-10 00:42:22 +08:00
|
|
|
|
2015-08-08 04:18:34 +08:00
|
|
|
; Test moving an SMRD with an immediate offset to the VALU
|
2014-05-10 00:42:22 +08:00
|
|
|
|
2015-09-29 04:54:32 +08:00
|
|
|
; GCN-LABEL: {{^}}smrd_valu2:
|
2016-01-05 11:40:16 +08:00
|
|
|
; GCN-NOHSA-NOT: v_add
|
|
|
|
|
; GCN-NOHSA: buffer_load_dword v{{[0-9]+}}, v{{\[[0-9]+:[0-9]+\]}}, s[{{[0-9]+:[0-9]+}}], 0 addr64 offset:16{{$}}
|
|
|
|
|
; GCN-HSA: flat_load_dword v{{[0-9]+}}, v[{{[0-9]+:[0-9]+}}]
|
2015-09-29 04:54:32 +08:00
|
|
|
define void @smrd_valu2(i32 addrspace(1)* %out, [8 x i32] addrspace(2)* %in) #1 {
|
2014-05-10 00:42:22 +08:00
|
|
|
entry:
|
2016-02-11 14:02:01 +08:00
|
|
|
%tmp = call i32 @llvm.amdgcn.workitem.id.x()
|
2015-09-29 04:54:32 +08:00
|
|
|
%tmp1 = add i32 %tmp, 4
|
|
|
|
|
%tmp2 = getelementptr [8 x i32], [8 x i32] addrspace(2)* %in, i32 %tmp, i32 4
|
|
|
|
|
%tmp3 = load i32, i32 addrspace(2)* %tmp2
|
|
|
|
|
store i32 %tmp3, i32 addrspace(1)* %out
|
2014-05-10 00:42:22 +08:00
|
|
|
ret void
|
|
|
|
|
}
|
2014-08-22 04:41:00 +08:00
|
|
|
|
2015-09-29 04:54:46 +08:00
|
|
|
; Use a big offset that will use the SMRD literal offset on CI
|
|
|
|
|
; GCN-LABEL: {{^}}smrd_valu_ci_offset:
|
2016-01-05 11:40:16 +08:00
|
|
|
; GCN-NOHSA-NOT: v_add
|
|
|
|
|
; GCN-NOHSA: s_movk_i32 [[OFFSET:s[0-9]+]], 0x4e20{{$}}
|
|
|
|
|
; GCN-NOHSA-NOT: v_add
|
|
|
|
|
; GCN-NOHSA: buffer_load_dword v{{[0-9]+}}, v{{\[[0-9]+:[0-9]+\]}}, s[{{[0-9]+:[0-9]+}}], [[OFFSET]] addr64{{$}}
|
|
|
|
|
; GCN-NOHSA: v_add_i32_e32
|
|
|
|
|
; GCN-NOHSA: buffer_store_dword
|
|
|
|
|
; GCN-HSA: flat_load_dword v{{[0-9]+}}, v[{{[0-9]+:[0-9]+}}]
|
2016-02-13 01:57:54 +08:00
|
|
|
; GCN-HSA: flat_store_dword v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}}
|
2015-09-29 04:54:46 +08:00
|
|
|
define void @smrd_valu_ci_offset(i32 addrspace(1)* %out, i32 addrspace(2)* %in, i32 %c) #1 {
|
|
|
|
|
entry:
|
2016-02-11 14:02:01 +08:00
|
|
|
%tmp = call i32 @llvm.amdgcn.workitem.id.x()
|
2015-09-29 04:54:46 +08:00
|
|
|
%tmp2 = getelementptr i32, i32 addrspace(2)* %in, i32 %tmp
|
|
|
|
|
%tmp3 = getelementptr i32, i32 addrspace(2)* %tmp2, i32 5000
|
|
|
|
|
%tmp4 = load i32, i32 addrspace(2)* %tmp3
|
|
|
|
|
%tmp5 = add i32 %tmp4, %c
|
|
|
|
|
store i32 %tmp5, i32 addrspace(1)* %out
|
|
|
|
|
ret void
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
; GCN-LABEL: {{^}}smrd_valu_ci_offset_x2:
|
2016-01-05 11:40:16 +08:00
|
|
|
; GCN-NOHSA-NOT: v_add
|
|
|
|
|
; GCN-NOHSA: s_mov_b32 [[OFFSET:s[0-9]+]], 0x9c40{{$}}
|
|
|
|
|
; GCN-NOHSA-NOT: v_add
|
|
|
|
|
; GCN-NOHSA: buffer_load_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, v{{\[[0-9]+:[0-9]+\]}}, s[{{[0-9]+:[0-9]+}}], [[OFFSET]] addr64{{$}}
|
|
|
|
|
; GCN-NOHSA: v_or_b32_e32 {{v[0-9]+}}, {{s[0-9]+}}, {{v[0-9]+}}
|
|
|
|
|
; GCN-NOHSA: v_or_b32_e32 {{v[0-9]+}}, {{s[0-9]+}}, {{v[0-9]+}}
|
|
|
|
|
; GCN-NOHSA: buffer_store_dwordx2
|
|
|
|
|
; GCN-HSA: flat_load_dwordx2 v[{{[0-9]+:[0-9]+}}], v[{{[0-9]+:[0-9]+}}]
|
2015-09-29 04:54:46 +08:00
|
|
|
define void @smrd_valu_ci_offset_x2(i64 addrspace(1)* %out, i64 addrspace(2)* %in, i64 %c) #1 {
|
|
|
|
|
entry:
|
2016-02-11 14:02:01 +08:00
|
|
|
%tmp = call i32 @llvm.amdgcn.workitem.id.x()
|
2015-09-29 04:54:46 +08:00
|
|
|
%tmp2 = getelementptr i64, i64 addrspace(2)* %in, i32 %tmp
|
|
|
|
|
%tmp3 = getelementptr i64, i64 addrspace(2)* %tmp2, i32 5000
|
|
|
|
|
%tmp4 = load i64, i64 addrspace(2)* %tmp3
|
|
|
|
|
%tmp5 = or i64 %tmp4, %c
|
|
|
|
|
store i64 %tmp5, i64 addrspace(1)* %out
|
|
|
|
|
ret void
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
; GCN-LABEL: {{^}}smrd_valu_ci_offset_x4:
|
2016-01-05 11:40:16 +08:00
|
|
|
; GCN-NOHSA-NOT: v_add
|
|
|
|
|
; GCN-NOHSA: s_movk_i32 [[OFFSET:s[0-9]+]], 0x4d20{{$}}
|
|
|
|
|
; GCN-NOHSA-NOT: v_add
|
|
|
|
|
; GCN-NOHSA: buffer_load_dwordx4 v{{\[[0-9]+:[0-9]+\]}}, v{{\[[0-9]+:[0-9]+\]}}, s[{{[0-9]+:[0-9]+}}], [[OFFSET]] addr64{{$}}
|
|
|
|
|
; GCN-NOHSA: v_or_b32_e32 {{v[0-9]+}}, {{s[0-9]+}}, {{v[0-9]+}}
|
|
|
|
|
; GCN-NOHSA: v_or_b32_e32 {{v[0-9]+}}, {{s[0-9]+}}, {{v[0-9]+}}
|
|
|
|
|
; GCN-NOHSA: v_or_b32_e32 {{v[0-9]+}}, {{s[0-9]+}}, {{v[0-9]+}}
|
|
|
|
|
; GCN-NOHSA: v_or_b32_e32 {{v[0-9]+}}, {{s[0-9]+}}, {{v[0-9]+}}
|
|
|
|
|
; GCN-NOHSA: buffer_store_dwordx4
|
|
|
|
|
; GCN-HSA: flat_load_dwordx4 v[{{[0-9]+:[0-9]+}}], v[{{[0-9]+:[0-9]+}}]
|
2015-09-29 04:54:46 +08:00
|
|
|
define void @smrd_valu_ci_offset_x4(<4 x i32> addrspace(1)* %out, <4 x i32> addrspace(2)* %in, <4 x i32> %c) #1 {
|
|
|
|
|
entry:
|
2016-02-11 14:02:01 +08:00
|
|
|
%tmp = call i32 @llvm.amdgcn.workitem.id.x()
|
2015-09-29 04:54:46 +08:00
|
|
|
%tmp2 = getelementptr <4 x i32>, <4 x i32> addrspace(2)* %in, i32 %tmp
|
|
|
|
|
%tmp3 = getelementptr <4 x i32>, <4 x i32> addrspace(2)* %tmp2, i32 1234
|
|
|
|
|
%tmp4 = load <4 x i32>, <4 x i32> addrspace(2)* %tmp3
|
|
|
|
|
%tmp5 = or <4 x i32> %tmp4, %c
|
|
|
|
|
store <4 x i32> %tmp5, <4 x i32> addrspace(1)* %out
|
|
|
|
|
ret void
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
; Original scalar load uses SGPR offset on SI and 32-bit literal on
|
|
|
|
|
; CI.
|
|
|
|
|
|
|
|
|
|
; GCN-LABEL: {{^}}smrd_valu_ci_offset_x8:
|
2016-01-05 11:40:16 +08:00
|
|
|
; GCN-NOHSA-NOT: v_add
|
|
|
|
|
; GCN-NOHSA: s_mov_b32 [[OFFSET0:s[0-9]+]], 0x9a40{{$}}
|
|
|
|
|
; GCN-NOHSA-NOT: v_add
|
|
|
|
|
; GCN-NOHSA: buffer_load_dwordx4 v{{\[[0-9]+:[0-9]+\]}}, v{{\[[0-9]+:[0-9]+\]}}, s[{{[0-9]+:[0-9]+}}], [[OFFSET0]] addr64{{$}}
|
|
|
|
|
; GCN-NOHSA-NOT: v_add
|
|
|
|
|
; GCN-NOHSA: s_mov_b32 [[OFFSET1:s[0-9]+]], 0x9a50{{$}}
|
|
|
|
|
; GCN-NOHSA-NOT: v_add
|
|
|
|
|
; GCN-NOHSA: buffer_load_dwordx4 v{{\[[0-9]+:[0-9]+\]}}, v{{\[[0-9]+:[0-9]+\]}}, s[{{[0-9]+:[0-9]+}}], [[OFFSET1]] addr64{{$}}
|
|
|
|
|
|
|
|
|
|
; GCN-NOHSA: v_or_b32_e32 {{v[0-9]+}}, {{s[0-9]+}}, {{v[0-9]+}}
|
|
|
|
|
; GCN-NOHSA: v_or_b32_e32 {{v[0-9]+}}, {{s[0-9]+}}, {{v[0-9]+}}
|
|
|
|
|
; GCN-NOHSA: v_or_b32_e32 {{v[0-9]+}}, {{s[0-9]+}}, {{v[0-9]+}}
|
|
|
|
|
; GCN-NOHSA: v_or_b32_e32 {{v[0-9]+}}, {{s[0-9]+}}, {{v[0-9]+}}
|
|
|
|
|
; GCN-NOHSA: v_or_b32_e32 {{v[0-9]+}}, {{s[0-9]+}}, {{v[0-9]+}}
|
|
|
|
|
; GCN-NOHSA: v_or_b32_e32 {{v[0-9]+}}, {{s[0-9]+}}, {{v[0-9]+}}
|
|
|
|
|
; GCN-NOHSA: v_or_b32_e32 {{v[0-9]+}}, {{s[0-9]+}}, {{v[0-9]+}}
|
|
|
|
|
; GCN-NOHSA: v_or_b32_e32 {{v[0-9]+}}, {{s[0-9]+}}, {{v[0-9]+}}
|
|
|
|
|
; GCN-NOHSA: buffer_store_dwordx4
|
|
|
|
|
; GCN-NOHSA: buffer_store_dwordx4
|
|
|
|
|
; GCN-HSA: flat_load_dwordx4
|
|
|
|
|
; GCN-HSA: flat_load_dwordx4
|
2015-09-29 04:54:46 +08:00
|
|
|
define void @smrd_valu_ci_offset_x8(<8 x i32> addrspace(1)* %out, <8 x i32> addrspace(2)* %in, <8 x i32> %c) #1 {
|
|
|
|
|
entry:
|
2016-02-11 14:02:01 +08:00
|
|
|
%tmp = call i32 @llvm.amdgcn.workitem.id.x()
|
2015-09-29 04:54:46 +08:00
|
|
|
%tmp2 = getelementptr <8 x i32>, <8 x i32> addrspace(2)* %in, i32 %tmp
|
|
|
|
|
%tmp3 = getelementptr <8 x i32>, <8 x i32> addrspace(2)* %tmp2, i32 1234
|
|
|
|
|
%tmp4 = load <8 x i32>, <8 x i32> addrspace(2)* %tmp3
|
|
|
|
|
%tmp5 = or <8 x i32> %tmp4, %c
|
|
|
|
|
store <8 x i32> %tmp5, <8 x i32> addrspace(1)* %out
|
|
|
|
|
ret void
|
|
|
|
|
}
|
|
|
|
|
|
2015-09-29 04:54:52 +08:00
|
|
|
; GCN-LABEL: {{^}}smrd_valu_ci_offset_x16:
|
|
|
|
|
|
2016-04-14 00:18:41 +08:00
|
|
|
; GCN-NOHSA-DAG: s_mov_b32 [[OFFSET0:s[0-9]+]], 0x13480{{$}}
|
|
|
|
|
; GCN-NOHSA-DAG: buffer_load_dwordx4 v{{\[[0-9]+:[0-9]+\]}}, v{{\[[0-9]+:[0-9]+\]}}, s[{{[0-9]+:[0-9]+}}], [[OFFSET0]] addr64{{$}}
|
|
|
|
|
; GCN-NOHSA-DAG: s_mov_b32 [[OFFSET1:s[0-9]+]], 0x13490{{$}}
|
|
|
|
|
; GCN-NOHSA-DAG: buffer_load_dwordx4 v{{\[[0-9]+:[0-9]+\]}}, v{{\[[0-9]+:[0-9]+\]}}, s[{{[0-9]+:[0-9]+}}], [[OFFSET1]] addr64{{$}}
|
|
|
|
|
; GCN-NOHSA-DAG: s_mov_b32 [[OFFSET2:s[0-9]+]], 0x134a0{{$}}
|
|
|
|
|
; GCN-NOHSA-DAG: buffer_load_dwordx4 v{{\[[0-9]+:[0-9]+\]}}, v{{\[[0-9]+:[0-9]+\]}}, s[{{[0-9]+:[0-9]+}}], [[OFFSET2]] addr64{{$}}
|
|
|
|
|
; GCN-NOHSA-DAG: s_mov_b32 [[OFFSET3:s[0-9]+]], 0x134b0{{$}}
|
|
|
|
|
; GCN-NOHSA-DAG: buffer_load_dwordx4 v{{\[[0-9]+:[0-9]+\]}}, v{{\[[0-9]+:[0-9]+\]}}, s[{{[0-9]+:[0-9]+}}], [[OFFSET3]] addr64{{$}}
|
2016-01-05 11:40:16 +08:00
|
|
|
|
|
|
|
|
; GCN-NOHSA: v_or_b32_e32 {{v[0-9]+}}, {{s[0-9]+}}, {{v[0-9]+}}
|
|
|
|
|
; GCN-NOHSA: v_or_b32_e32 {{v[0-9]+}}, {{s[0-9]+}}, {{v[0-9]+}}
|
|
|
|
|
; GCN-NOHSA: v_or_b32_e32 {{v[0-9]+}}, {{s[0-9]+}}, {{v[0-9]+}}
|
|
|
|
|
; GCN-NOHSA: v_or_b32_e32 {{v[0-9]+}}, {{s[0-9]+}}, {{v[0-9]+}}
|
|
|
|
|
; GCN-NOHSA: v_or_b32_e32 {{v[0-9]+}}, {{s[0-9]+}}, {{v[0-9]+}}
|
|
|
|
|
; GCN-NOHSA: v_or_b32_e32 {{v[0-9]+}}, {{s[0-9]+}}, {{v[0-9]+}}
|
|
|
|
|
; GCN-NOHSA: v_or_b32_e32 {{v[0-9]+}}, {{s[0-9]+}}, {{v[0-9]+}}
|
|
|
|
|
; GCN-NOHSA: v_or_b32_e32 {{v[0-9]+}}, {{s[0-9]+}}, {{v[0-9]+}}
|
|
|
|
|
; GCN-NOHSA: buffer_store_dwordx4
|
|
|
|
|
; GCN-NOHSA: buffer_store_dwordx4
|
|
|
|
|
; GCN-NOHSA: buffer_store_dwordx4
|
|
|
|
|
; GCN-NOHSA: buffer_store_dwordx4
|
|
|
|
|
|
|
|
|
|
; GCN-HSA: flat_load_dwordx4
|
|
|
|
|
; GCN-HSA: flat_load_dwordx4
|
|
|
|
|
; GCN-HSA: flat_load_dwordx4
|
|
|
|
|
; GCN-HSA: flat_load_dwordx4
|
2015-11-24 20:05:03 +08:00
|
|
|
|
|
|
|
|
; GCN: s_endpgm
|
2015-09-29 04:54:52 +08:00
|
|
|
define void @smrd_valu_ci_offset_x16(<16 x i32> addrspace(1)* %out, <16 x i32> addrspace(2)* %in, <16 x i32> %c) #1 {
|
|
|
|
|
entry:
|
2016-02-11 14:02:01 +08:00
|
|
|
%tmp = call i32 @llvm.amdgcn.workitem.id.x()
|
2015-09-29 04:54:52 +08:00
|
|
|
%tmp2 = getelementptr <16 x i32>, <16 x i32> addrspace(2)* %in, i32 %tmp
|
|
|
|
|
%tmp3 = getelementptr <16 x i32>, <16 x i32> addrspace(2)* %tmp2, i32 1234
|
|
|
|
|
%tmp4 = load <16 x i32>, <16 x i32> addrspace(2)* %tmp3
|
|
|
|
|
%tmp5 = or <16 x i32> %tmp4, %c
|
|
|
|
|
store <16 x i32> %tmp5, <16 x i32> addrspace(1)* %out
|
|
|
|
|
ret void
|
|
|
|
|
}
|
|
|
|
|
|
2015-09-29 04:54:38 +08:00
|
|
|
; GCN-LABEL: {{^}}smrd_valu2_salu_user:
|
2016-01-05 11:40:16 +08:00
|
|
|
; GCN-NOHSA: buffer_load_dword [[MOVED:v[0-9]+]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:16{{$}}
|
|
|
|
|
; GCN-HSA: flat_load_dword [[MOVED:v[0-9]+]], v[{{[0-9+:[0-9]+}}]
|
2015-09-29 04:54:38 +08:00
|
|
|
; GCN: v_add_i32_e32 [[ADD:v[0-9]+]], vcc, s{{[0-9]+}}, [[MOVED]]
|
2016-01-05 11:40:16 +08:00
|
|
|
; GCN-NOHSA: buffer_store_dword [[ADD]]
|
2016-02-13 01:57:54 +08:00
|
|
|
; GCN-HSA: flat_store_dword {{.*}}, [[ADD]]
|
2015-09-29 04:54:38 +08:00
|
|
|
define void @smrd_valu2_salu_user(i32 addrspace(1)* %out, [8 x i32] addrspace(2)* %in, i32 %a) #1 {
|
|
|
|
|
entry:
|
2016-02-11 14:02:01 +08:00
|
|
|
%tmp = call i32 @llvm.amdgcn.workitem.id.x()
|
2015-09-29 04:54:38 +08:00
|
|
|
%tmp1 = add i32 %tmp, 4
|
|
|
|
|
%tmp2 = getelementptr [8 x i32], [8 x i32] addrspace(2)* %in, i32 %tmp, i32 4
|
|
|
|
|
%tmp3 = load i32, i32 addrspace(2)* %tmp2
|
|
|
|
|
%tmp4 = add i32 %tmp3, %a
|
|
|
|
|
store i32 %tmp4, i32 addrspace(1)* %out
|
|
|
|
|
ret void
|
|
|
|
|
}
|
|
|
|
|
|
2015-09-29 04:54:32 +08:00
|
|
|
; GCN-LABEL: {{^}}smrd_valu2_max_smrd_offset:
|
2016-01-05 11:40:16 +08:00
|
|
|
; GCN-NOHSA: buffer_load_dword v{{[0-9]+}}, v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:1020{{$}}
|
|
|
|
|
; GCN-HSA flat_load_dword v{{[0-9]}}, v{{[0-9]+:[0-9]+}}
|
2015-09-29 04:54:32 +08:00
|
|
|
define void @smrd_valu2_max_smrd_offset(i32 addrspace(1)* %out, [1024 x i32] addrspace(2)* %in) #1 {
|
2015-08-08 04:18:34 +08:00
|
|
|
entry:
|
2016-02-11 14:02:01 +08:00
|
|
|
%tmp = call i32 @llvm.amdgcn.workitem.id.x()
|
2015-09-29 04:54:32 +08:00
|
|
|
%tmp1 = add i32 %tmp, 4
|
|
|
|
|
%tmp2 = getelementptr [1024 x i32], [1024 x i32] addrspace(2)* %in, i32 %tmp, i32 255
|
|
|
|
|
%tmp3 = load i32, i32 addrspace(2)* %tmp2
|
|
|
|
|
store i32 %tmp3, i32 addrspace(1)* %out
|
2015-08-08 04:18:34 +08:00
|
|
|
ret void
|
|
|
|
|
}
|
|
|
|
|
|
2015-09-29 04:54:32 +08:00
|
|
|
; GCN-LABEL: {{^}}smrd_valu2_mubuf_offset:
|
2016-01-05 11:40:16 +08:00
|
|
|
; GCN-NOHSA-NOT: v_add
|
|
|
|
|
; GCN-NOHSA: buffer_load_dword v{{[0-9]+}}, v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:1024{{$}}
|
|
|
|
|
; GCN-HSA: flat_load_dword v{{[0-9]}}, v[{{[0-9]+:[0-9]+}}]
|
2015-09-29 04:54:32 +08:00
|
|
|
define void @smrd_valu2_mubuf_offset(i32 addrspace(1)* %out, [1024 x i32] addrspace(2)* %in) #1 {
|
2015-08-08 04:18:34 +08:00
|
|
|
entry:
|
2016-02-11 14:02:01 +08:00
|
|
|
%tmp = call i32 @llvm.amdgcn.workitem.id.x()
|
2015-09-29 04:54:32 +08:00
|
|
|
%tmp1 = add i32 %tmp, 4
|
|
|
|
|
%tmp2 = getelementptr [1024 x i32], [1024 x i32] addrspace(2)* %in, i32 %tmp, i32 256
|
|
|
|
|
%tmp3 = load i32, i32 addrspace(2)* %tmp2
|
|
|
|
|
store i32 %tmp3, i32 addrspace(1)* %out
|
2015-08-08 04:18:34 +08:00
|
|
|
ret void
|
|
|
|
|
}
|
|
|
|
|
|
2015-09-29 04:54:32 +08:00
|
|
|
; GCN-LABEL: {{^}}s_load_imm_v8i32:
|
2016-01-05 11:40:16 +08:00
|
|
|
; GCN-NOHSA: buffer_load_dwordx4
|
|
|
|
|
; GCN-NOHSA: buffer_load_dwordx4
|
|
|
|
|
; GCN-HSA: flat_load_dwordx4
|
|
|
|
|
; GCN-HSA: flat_load_dwordx4
|
2015-09-29 04:54:32 +08:00
|
|
|
define void @s_load_imm_v8i32(<8 x i32> addrspace(1)* %out, i32 addrspace(2)* nocapture readonly %in) #1 {
|
2014-08-22 04:41:00 +08:00
|
|
|
entry:
|
2016-02-11 14:02:01 +08:00
|
|
|
%tmp0 = tail call i32 @llvm.amdgcn.workitem.id.x()
|
[opaque pointer type] Add textual IR support for explicit type parameter to getelementptr instruction
One of several parallel first steps to remove the target type of pointers,
replacing them with a single opaque pointer type.
This adds an explicit type parameter to the gep instruction so that when the
first parameter becomes an opaque pointer type, the type to gep through is
still available to the instructions.
* This doesn't modify gep operators, only instructions (operators will be
handled separately)
* Textual IR changes only. Bitcode (including upgrade) and changing the
in-memory representation will be in separate changes.
* geps of vectors are transformed as:
getelementptr <4 x float*> %x, ...
->getelementptr float, <4 x float*> %x, ...
Then, once the opaque pointer type is introduced, this will ultimately look
like:
getelementptr float, <4 x ptr> %x
with the unambiguous interpretation that it is a vector of pointers to float.
* address spaces remain on the pointer, not the type:
getelementptr float addrspace(1)* %x
->getelementptr float, float addrspace(1)* %x
Then, eventually:
getelementptr float, ptr addrspace(1) %x
Importantly, the massive amount of test case churn has been automated by
same crappy python code. I had to manually update a few test cases that
wouldn't fit the script's model (r228970,r229196,r229197,r229198). The
python script just massages stdin and writes the result to stdout, I
then wrapped that in a shell script to handle replacing files, then
using the usual find+xargs to migrate all the files.
update.py:
import fileinput
import sys
import re
ibrep = re.compile(r"(^.*?[^%\w]getelementptr inbounds )(((?:<\d* x )?)(.*?)(| addrspace\(\d\)) *\*(|>)(?:$| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$))")
normrep = re.compile( r"(^.*?[^%\w]getelementptr )(((?:<\d* x )?)(.*?)(| addrspace\(\d\)) *\*(|>)(?:$| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$))")
def conv(match, line):
if not match:
return line
line = match.groups()[0]
if len(match.groups()[5]) == 0:
line += match.groups()[2]
line += match.groups()[3]
line += ", "
line += match.groups()[1]
line += "\n"
return line
for line in sys.stdin:
if line.find("getelementptr ") == line.find("getelementptr inbounds"):
if line.find("getelementptr inbounds") != line.find("getelementptr inbounds ("):
line = conv(re.match(ibrep, line), line)
elif line.find("getelementptr ") != line.find("getelementptr ("):
line = conv(re.match(normrep, line), line)
sys.stdout.write(line)
apply.sh:
for name in "$@"
do
python3 `dirname "$0"`/update.py < "$name" > "$name.tmp" && mv "$name.tmp" "$name"
rm -f "$name.tmp"
done
The actual commands:
From llvm/src:
find test/ -name *.ll | xargs ./apply.sh
From llvm/src/tools/clang:
find test/ -name *.mm -o -name *.m -o -name *.cpp -o -name *.c | xargs -I '{}' ../../apply.sh "{}"
From llvm/src/tools/polly:
find test/ -name *.ll | xargs ./apply.sh
After that, check-all (with llvm, clang, clang-tools-extra, lld,
compiler-rt, and polly all checked out).
The extra 'rm' in the apply.sh script is due to a few files in clang's test
suite using interesting unicode stuff that my python script was throwing
exceptions on. None of those files needed to be migrated, so it seemed
sufficient to ignore those cases.
Reviewers: rafael, dexonsmith, grosser
Differential Revision: http://reviews.llvm.org/D7636
llvm-svn: 230786
2015-02-28 03:29:02 +08:00
|
|
|
%tmp1 = getelementptr inbounds i32, i32 addrspace(2)* %in, i32 %tmp0
|
2014-08-22 04:41:00 +08:00
|
|
|
%tmp2 = bitcast i32 addrspace(2)* %tmp1 to <8 x i32> addrspace(2)*
|
2015-02-28 05:17:42 +08:00
|
|
|
%tmp3 = load <8 x i32>, <8 x i32> addrspace(2)* %tmp2, align 4
|
2014-08-22 04:41:00 +08:00
|
|
|
store <8 x i32> %tmp3, <8 x i32> addrspace(1)* %out, align 32
|
|
|
|
|
ret void
|
|
|
|
|
}
|
|
|
|
|
|
2015-09-29 04:54:38 +08:00
|
|
|
; GCN-LABEL: {{^}}s_load_imm_v8i32_salu_user:
|
2016-01-05 11:40:16 +08:00
|
|
|
; GCN-NOHSA: buffer_load_dwordx4
|
|
|
|
|
; GCN-NOHSA: buffer_load_dwordx4
|
|
|
|
|
; GCN-NOHSA: v_add_i32_e32
|
|
|
|
|
; GCN-NOHSA: v_add_i32_e32
|
|
|
|
|
; GCN-NOHSA: v_add_i32_e32
|
|
|
|
|
; GCN-NOHSA: v_add_i32_e32
|
|
|
|
|
; GCN-NOHSA: v_add_i32_e32
|
|
|
|
|
; GCN-NOHSA: v_add_i32_e32
|
|
|
|
|
; GCN-NOHSA: v_add_i32_e32
|
|
|
|
|
; GCN-NOHSA: buffer_store_dword
|
|
|
|
|
; GCN-HSA: flat_load_dwordx4
|
|
|
|
|
; GCN-HSA: flat_load_dwordx4
|
2015-09-29 04:54:38 +08:00
|
|
|
define void @s_load_imm_v8i32_salu_user(i32 addrspace(1)* %out, i32 addrspace(2)* nocapture readonly %in) #1 {
|
|
|
|
|
entry:
|
2016-02-11 14:02:01 +08:00
|
|
|
%tmp0 = tail call i32 @llvm.amdgcn.workitem.id.x()
|
2015-09-29 04:54:38 +08:00
|
|
|
%tmp1 = getelementptr inbounds i32, i32 addrspace(2)* %in, i32 %tmp0
|
|
|
|
|
%tmp2 = bitcast i32 addrspace(2)* %tmp1 to <8 x i32> addrspace(2)*
|
|
|
|
|
%tmp3 = load <8 x i32>, <8 x i32> addrspace(2)* %tmp2, align 4
|
|
|
|
|
|
|
|
|
|
%elt0 = extractelement <8 x i32> %tmp3, i32 0
|
|
|
|
|
%elt1 = extractelement <8 x i32> %tmp3, i32 1
|
|
|
|
|
%elt2 = extractelement <8 x i32> %tmp3, i32 2
|
|
|
|
|
%elt3 = extractelement <8 x i32> %tmp3, i32 3
|
|
|
|
|
%elt4 = extractelement <8 x i32> %tmp3, i32 4
|
|
|
|
|
%elt5 = extractelement <8 x i32> %tmp3, i32 5
|
|
|
|
|
%elt6 = extractelement <8 x i32> %tmp3, i32 6
|
|
|
|
|
%elt7 = extractelement <8 x i32> %tmp3, i32 7
|
|
|
|
|
|
|
|
|
|
%add0 = add i32 %elt0, %elt1
|
|
|
|
|
%add1 = add i32 %add0, %elt2
|
|
|
|
|
%add2 = add i32 %add1, %elt3
|
|
|
|
|
%add3 = add i32 %add2, %elt4
|
|
|
|
|
%add4 = add i32 %add3, %elt5
|
|
|
|
|
%add5 = add i32 %add4, %elt6
|
|
|
|
|
%add6 = add i32 %add5, %elt7
|
|
|
|
|
|
|
|
|
|
store i32 %add6, i32 addrspace(1)* %out
|
|
|
|
|
ret void
|
|
|
|
|
}
|
|
|
|
|
|
2015-09-29 04:54:32 +08:00
|
|
|
; GCN-LABEL: {{^}}s_load_imm_v16i32:
|
2016-01-05 11:40:16 +08:00
|
|
|
; GCN-NOHSA: buffer_load_dwordx4
|
|
|
|
|
; GCN-NOHSA: buffer_load_dwordx4
|
|
|
|
|
; GCN-NOHSA: buffer_load_dwordx4
|
|
|
|
|
; GCN-NOHSA: buffer_load_dwordx4
|
|
|
|
|
; GCN-HSA: flat_load_dwordx4
|
|
|
|
|
; GCN-HSA: flat_load_dwordx4
|
|
|
|
|
; GCN-HSA: flat_load_dwordx4
|
|
|
|
|
; GCN-HSA: flat_load_dwordx4
|
2015-09-29 04:54:32 +08:00
|
|
|
define void @s_load_imm_v16i32(<16 x i32> addrspace(1)* %out, i32 addrspace(2)* nocapture readonly %in) #1 {
|
2014-08-22 04:41:00 +08:00
|
|
|
entry:
|
2016-02-11 14:02:01 +08:00
|
|
|
%tmp0 = tail call i32 @llvm.amdgcn.workitem.id.x()
|
[opaque pointer type] Add textual IR support for explicit type parameter to getelementptr instruction
One of several parallel first steps to remove the target type of pointers,
replacing them with a single opaque pointer type.
This adds an explicit type parameter to the gep instruction so that when the
first parameter becomes an opaque pointer type, the type to gep through is
still available to the instructions.
* This doesn't modify gep operators, only instructions (operators will be
handled separately)
* Textual IR changes only. Bitcode (including upgrade) and changing the
in-memory representation will be in separate changes.
* geps of vectors are transformed as:
getelementptr <4 x float*> %x, ...
->getelementptr float, <4 x float*> %x, ...
Then, once the opaque pointer type is introduced, this will ultimately look
like:
getelementptr float, <4 x ptr> %x
with the unambiguous interpretation that it is a vector of pointers to float.
* address spaces remain on the pointer, not the type:
getelementptr float addrspace(1)* %x
->getelementptr float, float addrspace(1)* %x
Then, eventually:
getelementptr float, ptr addrspace(1) %x
Importantly, the massive amount of test case churn has been automated by
same crappy python code. I had to manually update a few test cases that
wouldn't fit the script's model (r228970,r229196,r229197,r229198). The
python script just massages stdin and writes the result to stdout, I
then wrapped that in a shell script to handle replacing files, then
using the usual find+xargs to migrate all the files.
update.py:
import fileinput
import sys
import re
ibrep = re.compile(r"(^.*?[^%\w]getelementptr inbounds )(((?:<\d* x )?)(.*?)(| addrspace\(\d\)) *\*(|>)(?:$| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$))")
normrep = re.compile( r"(^.*?[^%\w]getelementptr )(((?:<\d* x )?)(.*?)(| addrspace\(\d\)) *\*(|>)(?:$| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$))")
def conv(match, line):
if not match:
return line
line = match.groups()[0]
if len(match.groups()[5]) == 0:
line += match.groups()[2]
line += match.groups()[3]
line += ", "
line += match.groups()[1]
line += "\n"
return line
for line in sys.stdin:
if line.find("getelementptr ") == line.find("getelementptr inbounds"):
if line.find("getelementptr inbounds") != line.find("getelementptr inbounds ("):
line = conv(re.match(ibrep, line), line)
elif line.find("getelementptr ") != line.find("getelementptr ("):
line = conv(re.match(normrep, line), line)
sys.stdout.write(line)
apply.sh:
for name in "$@"
do
python3 `dirname "$0"`/update.py < "$name" > "$name.tmp" && mv "$name.tmp" "$name"
rm -f "$name.tmp"
done
The actual commands:
From llvm/src:
find test/ -name *.ll | xargs ./apply.sh
From llvm/src/tools/clang:
find test/ -name *.mm -o -name *.m -o -name *.cpp -o -name *.c | xargs -I '{}' ../../apply.sh "{}"
From llvm/src/tools/polly:
find test/ -name *.ll | xargs ./apply.sh
After that, check-all (with llvm, clang, clang-tools-extra, lld,
compiler-rt, and polly all checked out).
The extra 'rm' in the apply.sh script is due to a few files in clang's test
suite using interesting unicode stuff that my python script was throwing
exceptions on. None of those files needed to be migrated, so it seemed
sufficient to ignore those cases.
Reviewers: rafael, dexonsmith, grosser
Differential Revision: http://reviews.llvm.org/D7636
llvm-svn: 230786
2015-02-28 03:29:02 +08:00
|
|
|
%tmp1 = getelementptr inbounds i32, i32 addrspace(2)* %in, i32 %tmp0
|
2014-08-22 04:41:00 +08:00
|
|
|
%tmp2 = bitcast i32 addrspace(2)* %tmp1 to <16 x i32> addrspace(2)*
|
2015-02-28 05:17:42 +08:00
|
|
|
%tmp3 = load <16 x i32>, <16 x i32> addrspace(2)* %tmp2, align 4
|
2014-08-22 04:41:00 +08:00
|
|
|
store <16 x i32> %tmp3, <16 x i32> addrspace(1)* %out, align 32
|
|
|
|
|
ret void
|
|
|
|
|
}
|
2015-09-29 04:54:32 +08:00
|
|
|
|
2015-09-29 04:54:38 +08:00
|
|
|
; GCN-LABEL: {{^}}s_load_imm_v16i32_salu_user:
|
2016-01-05 11:40:16 +08:00
|
|
|
; GCN-NOHSA: buffer_load_dwordx4
|
|
|
|
|
; GCN-NOHSA: buffer_load_dwordx4
|
|
|
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|
; GCN-NOHSA: buffer_load_dwordx4
|
|
|
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|
; GCN-NOHSA: buffer_load_dwordx4
|
|
|
|
|
; GCN-NOHSA: v_add_i32_e32
|
|
|
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|
; GCN-NOHSA: v_add_i32_e32
|
|
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; GCN-NOHSA: v_add_i32_e32
|
|
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|
; GCN-NOHSA: v_add_i32_e32
|
|
|
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|
; GCN-NOHSA: v_add_i32_e32
|
|
|
|
|
; GCN-NOHSA: v_add_i32_e32
|
|
|
|
|
; GCN-NOHSA: v_add_i32_e32
|
|
|
|
|
; GCN-NOHSA: v_add_i32_e32
|
|
|
|
|
; GCN-NOHSA: v_add_i32_e32
|
|
|
|
|
; GCN-NOHSA: v_add_i32_e32
|
|
|
|
|
; GCN-NOHSA: v_add_i32_e32
|
|
|
|
|
; GCN-NOHSA: v_add_i32_e32
|
|
|
|
|
; GCN-NOHSA: v_add_i32_e32
|
|
|
|
|
; GCN-NOHSA: v_add_i32_e32
|
|
|
|
|
; GCN-NOHSA: v_add_i32_e32
|
|
|
|
|
; GCN-NOHSA: buffer_store_dword
|
|
|
|
|
; GCN-HSA: flat_load_dwordx4
|
|
|
|
|
; GCN-HSA: flat_load_dwordx4
|
|
|
|
|
; GCN-HSA: flat_load_dwordx4
|
|
|
|
|
; GCN-HSA: flat_load_dwordx4
|
2015-09-29 04:54:38 +08:00
|
|
|
define void @s_load_imm_v16i32_salu_user(i32 addrspace(1)* %out, i32 addrspace(2)* nocapture readonly %in) #1 {
|
|
|
|
|
entry:
|
2016-02-11 14:02:01 +08:00
|
|
|
%tmp0 = tail call i32 @llvm.amdgcn.workitem.id.x()
|
2015-09-29 04:54:38 +08:00
|
|
|
%tmp1 = getelementptr inbounds i32, i32 addrspace(2)* %in, i32 %tmp0
|
|
|
|
|
%tmp2 = bitcast i32 addrspace(2)* %tmp1 to <16 x i32> addrspace(2)*
|
|
|
|
|
%tmp3 = load <16 x i32>, <16 x i32> addrspace(2)* %tmp2, align 4
|
|
|
|
|
|
|
|
|
|
%elt0 = extractelement <16 x i32> %tmp3, i32 0
|
|
|
|
|
%elt1 = extractelement <16 x i32> %tmp3, i32 1
|
|
|
|
|
%elt2 = extractelement <16 x i32> %tmp3, i32 2
|
|
|
|
|
%elt3 = extractelement <16 x i32> %tmp3, i32 3
|
|
|
|
|
%elt4 = extractelement <16 x i32> %tmp3, i32 4
|
|
|
|
|
%elt5 = extractelement <16 x i32> %tmp3, i32 5
|
|
|
|
|
%elt6 = extractelement <16 x i32> %tmp3, i32 6
|
|
|
|
|
%elt7 = extractelement <16 x i32> %tmp3, i32 7
|
|
|
|
|
%elt8 = extractelement <16 x i32> %tmp3, i32 8
|
|
|
|
|
%elt9 = extractelement <16 x i32> %tmp3, i32 9
|
|
|
|
|
%elt10 = extractelement <16 x i32> %tmp3, i32 10
|
|
|
|
|
%elt11 = extractelement <16 x i32> %tmp3, i32 11
|
|
|
|
|
%elt12 = extractelement <16 x i32> %tmp3, i32 12
|
|
|
|
|
%elt13 = extractelement <16 x i32> %tmp3, i32 13
|
|
|
|
|
%elt14 = extractelement <16 x i32> %tmp3, i32 14
|
|
|
|
|
%elt15 = extractelement <16 x i32> %tmp3, i32 15
|
|
|
|
|
|
|
|
|
|
%add0 = add i32 %elt0, %elt1
|
|
|
|
|
%add1 = add i32 %add0, %elt2
|
|
|
|
|
%add2 = add i32 %add1, %elt3
|
|
|
|
|
%add3 = add i32 %add2, %elt4
|
|
|
|
|
%add4 = add i32 %add3, %elt5
|
|
|
|
|
%add5 = add i32 %add4, %elt6
|
|
|
|
|
%add6 = add i32 %add5, %elt7
|
|
|
|
|
%add7 = add i32 %add6, %elt8
|
|
|
|
|
%add8 = add i32 %add7, %elt9
|
|
|
|
|
%add9 = add i32 %add8, %elt10
|
|
|
|
|
%add10 = add i32 %add9, %elt11
|
|
|
|
|
%add11 = add i32 %add10, %elt12
|
|
|
|
|
%add12 = add i32 %add11, %elt13
|
|
|
|
|
%add13 = add i32 %add12, %elt14
|
|
|
|
|
%add14 = add i32 %add13, %elt15
|
|
|
|
|
|
|
|
|
|
store i32 %add14, i32 addrspace(1)* %out
|
|
|
|
|
ret void
|
|
|
|
|
}
|
|
|
|
|
|
2016-02-13 07:45:29 +08:00
|
|
|
; Make sure we legalize vopc operands after moving an sopc to the value.
|
|
|
|
|
|
|
|
|
|
; {{^}}sopc_vopc_legalize_bug:
|
|
|
|
|
; GCN: s_load_dword [[SGPR:s[0-9]+]]
|
|
|
|
|
; GCN: v_cmp_le_u32_e32 vcc, [[SGPR]], v{{[0-9]+}}
|
|
|
|
|
; GCN: s_and_b64 vcc, exec, vcc
|
|
|
|
|
; GCN: s_cbranch_vccnz [[EXIT:[A-Z0-9_]+]]
|
|
|
|
|
; GCN: v_mov_b32_e32 [[ONE:v[0-9]+]], 1
|
|
|
|
|
; GCN-NOHSA: buffer_store_dword [[ONE]]
|
|
|
|
|
; GCN-HSA: flat_store_dword v[{{[0-9]+:[0-9]+}}], [[ONE]]
|
|
|
|
|
; GCN; {{^}}[[EXIT]]:
|
|
|
|
|
; GCN: s_endpgm
|
|
|
|
|
define void @sopc_vopc_legalize_bug(i32 %cond, i32 addrspace(1)* %out, i32 addrspace(1)* %in) {
|
|
|
|
|
bb3: ; preds = %bb2
|
|
|
|
|
%tmp0 = bitcast i32 %cond to float
|
|
|
|
|
%tmp1 = fadd float %tmp0, 2.500000e-01
|
|
|
|
|
%tmp2 = bitcast float %tmp1 to i32
|
|
|
|
|
%tmp3 = icmp ult i32 %tmp2, %cond
|
|
|
|
|
br i1 %tmp3, label %bb6, label %bb7
|
|
|
|
|
|
|
|
|
|
bb6:
|
|
|
|
|
store i32 1, i32 addrspace(1)* %out
|
|
|
|
|
br label %bb7
|
|
|
|
|
|
|
|
|
|
bb7: ; preds = %bb3
|
|
|
|
|
ret void
|
|
|
|
|
}
|
|
|
|
|
|
2015-09-29 04:54:32 +08:00
|
|
|
attributes #0 = { nounwind readnone }
|
|
|
|
|
attributes #1 = { nounwind }
|