2010-06-09 00:52:24 +08:00
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//===-- ArchSpec.cpp --------------------------------------------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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#include "lldb/Core/ArchSpec.h"
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2010-06-11 12:26:08 +08:00
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#include <stdio.h>
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2012-09-19 07:27:18 +08:00
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#include <errno.h>
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2010-06-09 00:52:24 +08:00
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#include <string>
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2013-08-27 13:04:33 +08:00
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#include "llvm/Support/COFF.h"
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2010-06-11 11:25:34 +08:00
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#include "llvm/Support/ELF.h"
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2011-02-25 03:13:58 +08:00
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#include "llvm/Support/Host.h"
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2010-06-11 11:25:34 +08:00
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#include "llvm/Support/MachO.h"
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2012-08-08 09:19:34 +08:00
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#include "lldb/Core/RegularExpression.h"
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2011-02-16 05:59:32 +08:00
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#include "lldb/Host/Endian.h"
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#include "lldb/Host/Host.h"
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2011-04-08 06:46:35 +08:00
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#include "lldb/Target/Platform.h"
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2010-06-11 11:25:34 +08:00
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2010-06-09 00:52:24 +08:00
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using namespace lldb;
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using namespace lldb_private;
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2011-02-23 08:35:02 +08:00
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#define ARCH_SPEC_SEPARATOR_CHAR '-'
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2010-06-09 00:52:24 +08:00
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2012-11-04 11:20:05 +08:00
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static bool cores_match (const ArchSpec::Core core1, const ArchSpec::Core core2, bool try_inverse, bool enforce_exact_match);
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2011-02-23 08:35:02 +08:00
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namespace lldb_private {
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2010-06-09 00:52:24 +08:00
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2011-02-23 08:35:02 +08:00
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struct CoreDefinition
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{
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ByteOrder default_byte_order;
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uint32_t addr_byte_size;
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Added the ability to get the min and max instruction byte size for
an architecture into ArchSpec:
uint32_t
ArchSpec::GetMinimumOpcodeByteSize() const;
uint32_t
ArchSpec::GetMaximumOpcodeByteSize() const;
Added an AddressClass to the Instruction class in Disassembler.h.
This allows decoded instructions to know know if they are code,
code with alternate ISA (thumb), or even data which can be mixed
into code. The instruction does have an address, but it is a good
idea to cache this value so we don't have to look it up more than
once.
Fixed an issue in Opcode::SetOpcodeBytes() where the length wasn't
getting set.
Changed:
bool
SymbolContextList::AppendIfUnique (const SymbolContext& sc);
To:
bool
SymbolContextList::AppendIfUnique (const SymbolContext& sc,
bool merge_symbol_into_function);
This function was typically being used when looking up functions
and symbols. Now if you lookup a function, then find the symbol,
they can be merged into the same symbol context and not cause
multiple symbol contexts to appear in a symbol context list that
describes the same function.
Fixed the SymbolContext not equal operator which was causing mixed
mode disassembly to not work ("disassembler --mixed --name main").
Modified the disassembler classes to know about the fact we know,
for a given architecture, what the min and max opcode byte sizes
are. The InstructionList class was modified to return the max
opcode byte size for all of the instructions in its list.
These two fixes means when disassemble a list of instructions and dump
them and show the opcode bytes, we can format the output more
intelligently when showing opcode bytes. This affects any architectures
that have varying opcode byte sizes (x86_64 and i386). Knowing the max
opcode byte size also helps us to be able to disassemble N instructions
without having to re-read data if we didn't read enough bytes.
Added the ability to set the architecture for the disassemble command.
This means you can easily cross disassemble data for any supported
architecture. I also added the ability to specify "thumb" as an
architecture so that we can force disassembly into thumb mode when
needed. In GDB this was done using a hack of specifying an odd
address when disassembling. I don't want to repeat this hack in LLDB,
so the auto detection between ARM and thumb is failing, just specify
thumb when disassembling:
(lldb) disassemble --arch thumb --name main
You can also have data in say an x86_64 file executable and disassemble
data as any other supported architecture:
% lldb a.out
Current executable set to 'a.out' (x86_64).
(lldb) b main
(lldb) run
(lldb) disassemble --arch thumb --count 2 --start-address 0x0000000100001080 --bytes
0x100001080: 0xb580 push {r7, lr}
0x100001082: 0xaf00 add r7, sp, #0
Fixed Target::ReadMemory(...) to be able to deal with Address argument object
that isn't section offset. When an address object was supplied that was
out on the heap or stack, target read memory would fail. Disassembly uses
Target::ReadMemory(...), and the example above where we disassembler thumb
opcodes in an x86 binary was failing do to this bug.
llvm-svn: 128347
2011-03-27 03:14:58 +08:00
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uint32_t min_opcode_byte_size;
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uint32_t max_opcode_byte_size;
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2011-02-23 08:35:02 +08:00
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llvm::Triple::ArchType machine;
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ArchSpec::Core core;
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const char *name;
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};
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2010-06-09 00:52:24 +08:00
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2011-02-23 08:35:02 +08:00
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}
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2010-06-11 11:25:34 +08:00
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2011-02-23 08:35:02 +08:00
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// This core information can be looked using the ArchSpec::Core as the index
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static const CoreDefinition g_core_definitions[ArchSpec::kNumCores] =
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2010-06-11 11:25:34 +08:00
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{
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Added the ability to get the min and max instruction byte size for
an architecture into ArchSpec:
uint32_t
ArchSpec::GetMinimumOpcodeByteSize() const;
uint32_t
ArchSpec::GetMaximumOpcodeByteSize() const;
Added an AddressClass to the Instruction class in Disassembler.h.
This allows decoded instructions to know know if they are code,
code with alternate ISA (thumb), or even data which can be mixed
into code. The instruction does have an address, but it is a good
idea to cache this value so we don't have to look it up more than
once.
Fixed an issue in Opcode::SetOpcodeBytes() where the length wasn't
getting set.
Changed:
bool
SymbolContextList::AppendIfUnique (const SymbolContext& sc);
To:
bool
SymbolContextList::AppendIfUnique (const SymbolContext& sc,
bool merge_symbol_into_function);
This function was typically being used when looking up functions
and symbols. Now if you lookup a function, then find the symbol,
they can be merged into the same symbol context and not cause
multiple symbol contexts to appear in a symbol context list that
describes the same function.
Fixed the SymbolContext not equal operator which was causing mixed
mode disassembly to not work ("disassembler --mixed --name main").
Modified the disassembler classes to know about the fact we know,
for a given architecture, what the min and max opcode byte sizes
are. The InstructionList class was modified to return the max
opcode byte size for all of the instructions in its list.
These two fixes means when disassemble a list of instructions and dump
them and show the opcode bytes, we can format the output more
intelligently when showing opcode bytes. This affects any architectures
that have varying opcode byte sizes (x86_64 and i386). Knowing the max
opcode byte size also helps us to be able to disassemble N instructions
without having to re-read data if we didn't read enough bytes.
Added the ability to set the architecture for the disassemble command.
This means you can easily cross disassemble data for any supported
architecture. I also added the ability to specify "thumb" as an
architecture so that we can force disassembly into thumb mode when
needed. In GDB this was done using a hack of specifying an odd
address when disassembling. I don't want to repeat this hack in LLDB,
so the auto detection between ARM and thumb is failing, just specify
thumb when disassembling:
(lldb) disassemble --arch thumb --name main
You can also have data in say an x86_64 file executable and disassemble
data as any other supported architecture:
% lldb a.out
Current executable set to 'a.out' (x86_64).
(lldb) b main
(lldb) run
(lldb) disassemble --arch thumb --count 2 --start-address 0x0000000100001080 --bytes
0x100001080: 0xb580 push {r7, lr}
0x100001082: 0xaf00 add r7, sp, #0
Fixed Target::ReadMemory(...) to be able to deal with Address argument object
that isn't section offset. When an address object was supplied that was
out on the heap or stack, target read memory would fail. Disassembly uses
Target::ReadMemory(...), and the example above where we disassembler thumb
opcodes in an x86 binary was failing do to this bug.
llvm-svn: 128347
2011-03-27 03:14:58 +08:00
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{ eByteOrderLittle, 4, 2, 4, llvm::Triple::arm , ArchSpec::eCore_arm_generic , "arm" },
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{ eByteOrderLittle, 4, 2, 4, llvm::Triple::arm , ArchSpec::eCore_arm_armv4 , "armv4" },
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{ eByteOrderLittle, 4, 2, 4, llvm::Triple::arm , ArchSpec::eCore_arm_armv4t , "armv4t" },
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{ eByteOrderLittle, 4, 2, 4, llvm::Triple::arm , ArchSpec::eCore_arm_armv5 , "armv5" },
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2011-12-17 02:15:52 +08:00
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{ eByteOrderLittle, 4, 2, 4, llvm::Triple::arm , ArchSpec::eCore_arm_armv5e , "armv5e" },
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Added the ability to get the min and max instruction byte size for
an architecture into ArchSpec:
uint32_t
ArchSpec::GetMinimumOpcodeByteSize() const;
uint32_t
ArchSpec::GetMaximumOpcodeByteSize() const;
Added an AddressClass to the Instruction class in Disassembler.h.
This allows decoded instructions to know know if they are code,
code with alternate ISA (thumb), or even data which can be mixed
into code. The instruction does have an address, but it is a good
idea to cache this value so we don't have to look it up more than
once.
Fixed an issue in Opcode::SetOpcodeBytes() where the length wasn't
getting set.
Changed:
bool
SymbolContextList::AppendIfUnique (const SymbolContext& sc);
To:
bool
SymbolContextList::AppendIfUnique (const SymbolContext& sc,
bool merge_symbol_into_function);
This function was typically being used when looking up functions
and symbols. Now if you lookup a function, then find the symbol,
they can be merged into the same symbol context and not cause
multiple symbol contexts to appear in a symbol context list that
describes the same function.
Fixed the SymbolContext not equal operator which was causing mixed
mode disassembly to not work ("disassembler --mixed --name main").
Modified the disassembler classes to know about the fact we know,
for a given architecture, what the min and max opcode byte sizes
are. The InstructionList class was modified to return the max
opcode byte size for all of the instructions in its list.
These two fixes means when disassemble a list of instructions and dump
them and show the opcode bytes, we can format the output more
intelligently when showing opcode bytes. This affects any architectures
that have varying opcode byte sizes (x86_64 and i386). Knowing the max
opcode byte size also helps us to be able to disassemble N instructions
without having to re-read data if we didn't read enough bytes.
Added the ability to set the architecture for the disassemble command.
This means you can easily cross disassemble data for any supported
architecture. I also added the ability to specify "thumb" as an
architecture so that we can force disassembly into thumb mode when
needed. In GDB this was done using a hack of specifying an odd
address when disassembling. I don't want to repeat this hack in LLDB,
so the auto detection between ARM and thumb is failing, just specify
thumb when disassembling:
(lldb) disassemble --arch thumb --name main
You can also have data in say an x86_64 file executable and disassemble
data as any other supported architecture:
% lldb a.out
Current executable set to 'a.out' (x86_64).
(lldb) b main
(lldb) run
(lldb) disassemble --arch thumb --count 2 --start-address 0x0000000100001080 --bytes
0x100001080: 0xb580 push {r7, lr}
0x100001082: 0xaf00 add r7, sp, #0
Fixed Target::ReadMemory(...) to be able to deal with Address argument object
that isn't section offset. When an address object was supplied that was
out on the heap or stack, target read memory would fail. Disassembly uses
Target::ReadMemory(...), and the example above where we disassembler thumb
opcodes in an x86 binary was failing do to this bug.
llvm-svn: 128347
2011-03-27 03:14:58 +08:00
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{ eByteOrderLittle, 4, 2, 4, llvm::Triple::arm , ArchSpec::eCore_arm_armv5t , "armv5t" },
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{ eByteOrderLittle, 4, 2, 4, llvm::Triple::arm , ArchSpec::eCore_arm_armv6 , "armv6" },
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2013-09-28 07:21:54 +08:00
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{ eByteOrderLittle, 4, 2, 4, llvm::Triple::arm , ArchSpec::eCore_arm_armv6m , "armv6m" },
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Added the ability to get the min and max instruction byte size for
an architecture into ArchSpec:
uint32_t
ArchSpec::GetMinimumOpcodeByteSize() const;
uint32_t
ArchSpec::GetMaximumOpcodeByteSize() const;
Added an AddressClass to the Instruction class in Disassembler.h.
This allows decoded instructions to know know if they are code,
code with alternate ISA (thumb), or even data which can be mixed
into code. The instruction does have an address, but it is a good
idea to cache this value so we don't have to look it up more than
once.
Fixed an issue in Opcode::SetOpcodeBytes() where the length wasn't
getting set.
Changed:
bool
SymbolContextList::AppendIfUnique (const SymbolContext& sc);
To:
bool
SymbolContextList::AppendIfUnique (const SymbolContext& sc,
bool merge_symbol_into_function);
This function was typically being used when looking up functions
and symbols. Now if you lookup a function, then find the symbol,
they can be merged into the same symbol context and not cause
multiple symbol contexts to appear in a symbol context list that
describes the same function.
Fixed the SymbolContext not equal operator which was causing mixed
mode disassembly to not work ("disassembler --mixed --name main").
Modified the disassembler classes to know about the fact we know,
for a given architecture, what the min and max opcode byte sizes
are. The InstructionList class was modified to return the max
opcode byte size for all of the instructions in its list.
These two fixes means when disassemble a list of instructions and dump
them and show the opcode bytes, we can format the output more
intelligently when showing opcode bytes. This affects any architectures
that have varying opcode byte sizes (x86_64 and i386). Knowing the max
opcode byte size also helps us to be able to disassemble N instructions
without having to re-read data if we didn't read enough bytes.
Added the ability to set the architecture for the disassemble command.
This means you can easily cross disassemble data for any supported
architecture. I also added the ability to specify "thumb" as an
architecture so that we can force disassembly into thumb mode when
needed. In GDB this was done using a hack of specifying an odd
address when disassembling. I don't want to repeat this hack in LLDB,
so the auto detection between ARM and thumb is failing, just specify
thumb when disassembling:
(lldb) disassemble --arch thumb --name main
You can also have data in say an x86_64 file executable and disassemble
data as any other supported architecture:
% lldb a.out
Current executable set to 'a.out' (x86_64).
(lldb) b main
(lldb) run
(lldb) disassemble --arch thumb --count 2 --start-address 0x0000000100001080 --bytes
0x100001080: 0xb580 push {r7, lr}
0x100001082: 0xaf00 add r7, sp, #0
Fixed Target::ReadMemory(...) to be able to deal with Address argument object
that isn't section offset. When an address object was supplied that was
out on the heap or stack, target read memory would fail. Disassembly uses
Target::ReadMemory(...), and the example above where we disassembler thumb
opcodes in an x86 binary was failing do to this bug.
llvm-svn: 128347
2011-03-27 03:14:58 +08:00
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{ eByteOrderLittle, 4, 2, 4, llvm::Triple::arm , ArchSpec::eCore_arm_armv7 , "armv7" },
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{ eByteOrderLittle, 4, 2, 4, llvm::Triple::arm , ArchSpec::eCore_arm_armv7f , "armv7f" },
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{ eByteOrderLittle, 4, 2, 4, llvm::Triple::arm , ArchSpec::eCore_arm_armv7s , "armv7s" },
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2013-03-08 09:20:17 +08:00
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{ eByteOrderLittle, 4, 2, 4, llvm::Triple::arm , ArchSpec::eCore_arm_armv7k , "armv7k" },
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{ eByteOrderLittle, 4, 2, 4, llvm::Triple::arm , ArchSpec::eCore_arm_armv7m , "armv7m" },
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{ eByteOrderLittle, 4, 2, 4, llvm::Triple::arm , ArchSpec::eCore_arm_armv7em , "armv7em" },
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Added the ability to get the min and max instruction byte size for
an architecture into ArchSpec:
uint32_t
ArchSpec::GetMinimumOpcodeByteSize() const;
uint32_t
ArchSpec::GetMaximumOpcodeByteSize() const;
Added an AddressClass to the Instruction class in Disassembler.h.
This allows decoded instructions to know know if they are code,
code with alternate ISA (thumb), or even data which can be mixed
into code. The instruction does have an address, but it is a good
idea to cache this value so we don't have to look it up more than
once.
Fixed an issue in Opcode::SetOpcodeBytes() where the length wasn't
getting set.
Changed:
bool
SymbolContextList::AppendIfUnique (const SymbolContext& sc);
To:
bool
SymbolContextList::AppendIfUnique (const SymbolContext& sc,
bool merge_symbol_into_function);
This function was typically being used when looking up functions
and symbols. Now if you lookup a function, then find the symbol,
they can be merged into the same symbol context and not cause
multiple symbol contexts to appear in a symbol context list that
describes the same function.
Fixed the SymbolContext not equal operator which was causing mixed
mode disassembly to not work ("disassembler --mixed --name main").
Modified the disassembler classes to know about the fact we know,
for a given architecture, what the min and max opcode byte sizes
are. The InstructionList class was modified to return the max
opcode byte size for all of the instructions in its list.
These two fixes means when disassemble a list of instructions and dump
them and show the opcode bytes, we can format the output more
intelligently when showing opcode bytes. This affects any architectures
that have varying opcode byte sizes (x86_64 and i386). Knowing the max
opcode byte size also helps us to be able to disassemble N instructions
without having to re-read data if we didn't read enough bytes.
Added the ability to set the architecture for the disassemble command.
This means you can easily cross disassemble data for any supported
architecture. I also added the ability to specify "thumb" as an
architecture so that we can force disassembly into thumb mode when
needed. In GDB this was done using a hack of specifying an odd
address when disassembling. I don't want to repeat this hack in LLDB,
so the auto detection between ARM and thumb is failing, just specify
thumb when disassembling:
(lldb) disassemble --arch thumb --name main
You can also have data in say an x86_64 file executable and disassemble
data as any other supported architecture:
% lldb a.out
Current executable set to 'a.out' (x86_64).
(lldb) b main
(lldb) run
(lldb) disassemble --arch thumb --count 2 --start-address 0x0000000100001080 --bytes
0x100001080: 0xb580 push {r7, lr}
0x100001082: 0xaf00 add r7, sp, #0
Fixed Target::ReadMemory(...) to be able to deal with Address argument object
that isn't section offset. When an address object was supplied that was
out on the heap or stack, target read memory would fail. Disassembly uses
Target::ReadMemory(...), and the example above where we disassembler thumb
opcodes in an x86 binary was failing do to this bug.
llvm-svn: 128347
2011-03-27 03:14:58 +08:00
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{ eByteOrderLittle, 4, 2, 4, llvm::Triple::arm , ArchSpec::eCore_arm_xscale , "xscale" },
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2011-12-17 02:15:52 +08:00
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{ eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb , ArchSpec::eCore_thumb , "thumb" },
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{ eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb , ArchSpec::eCore_thumbv4t , "thumbv4t" },
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{ eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb , ArchSpec::eCore_thumbv5 , "thumbv5" },
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{ eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb , ArchSpec::eCore_thumbv5e , "thumbv5e" },
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{ eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb , ArchSpec::eCore_thumbv6 , "thumbv6" },
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2013-09-28 07:21:54 +08:00
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{ eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb , ArchSpec::eCore_thumbv6m , "thumbv6m" },
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2011-12-17 02:15:52 +08:00
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{ eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb , ArchSpec::eCore_thumbv7 , "thumbv7" },
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{ eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb , ArchSpec::eCore_thumbv7f , "thumbv7f" },
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{ eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb , ArchSpec::eCore_thumbv7s , "thumbv7s" },
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2013-03-08 09:20:17 +08:00
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{ eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb , ArchSpec::eCore_thumbv7k , "thumbv7k" },
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{ eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb , ArchSpec::eCore_thumbv7m , "thumbv7m" },
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{ eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb , ArchSpec::eCore_thumbv7em , "thumbv7em" },
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2013-10-10 08:59:47 +08:00
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{ eByteOrderBig , 8, 4, 4, llvm::Triple::mips64 , ArchSpec::eCore_mips64 , "mips64" },
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2011-02-23 08:35:02 +08:00
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2013-08-13 02:34:04 +08:00
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{ eByteOrderBig , 4, 4, 4, llvm::Triple::ppc , ArchSpec::eCore_ppc_generic , "ppc" },
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{ eByteOrderBig , 4, 4, 4, llvm::Triple::ppc , ArchSpec::eCore_ppc_ppc601 , "ppc601" },
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{ eByteOrderBig , 4, 4, 4, llvm::Triple::ppc , ArchSpec::eCore_ppc_ppc602 , "ppc602" },
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{ eByteOrderBig , 4, 4, 4, llvm::Triple::ppc , ArchSpec::eCore_ppc_ppc603 , "ppc603" },
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{ eByteOrderBig , 4, 4, 4, llvm::Triple::ppc , ArchSpec::eCore_ppc_ppc603e , "ppc603e" },
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{ eByteOrderBig , 4, 4, 4, llvm::Triple::ppc , ArchSpec::eCore_ppc_ppc603ev , "ppc603ev" },
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{ eByteOrderBig , 4, 4, 4, llvm::Triple::ppc , ArchSpec::eCore_ppc_ppc604 , "ppc604" },
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{ eByteOrderBig , 4, 4, 4, llvm::Triple::ppc , ArchSpec::eCore_ppc_ppc604e , "ppc604e" },
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{ eByteOrderBig , 4, 4, 4, llvm::Triple::ppc , ArchSpec::eCore_ppc_ppc620 , "ppc620" },
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|
|
{ eByteOrderBig , 4, 4, 4, llvm::Triple::ppc , ArchSpec::eCore_ppc_ppc750 , "ppc750" },
|
|
|
|
|
{ eByteOrderBig , 4, 4, 4, llvm::Triple::ppc , ArchSpec::eCore_ppc_ppc7400 , "ppc7400" },
|
|
|
|
|
{ eByteOrderBig , 4, 4, 4, llvm::Triple::ppc , ArchSpec::eCore_ppc_ppc7450 , "ppc7450" },
|
|
|
|
|
{ eByteOrderBig , 4, 4, 4, llvm::Triple::ppc , ArchSpec::eCore_ppc_ppc970 , "ppc970" },
|
2011-02-23 08:35:02 +08:00
|
|
|
|
2013-08-13 02:34:04 +08:00
|
|
|
{ eByteOrderBig , 8, 4, 4, llvm::Triple::ppc64 , ArchSpec::eCore_ppc64_generic , "ppc64" },
|
|
|
|
|
{ eByteOrderBig , 8, 4, 4, llvm::Triple::ppc64 , ArchSpec::eCore_ppc64_ppc970_64 , "ppc970-64" },
|
2011-02-23 08:35:02 +08:00
|
|
|
|
Added the ability to get the min and max instruction byte size for
an architecture into ArchSpec:
uint32_t
ArchSpec::GetMinimumOpcodeByteSize() const;
uint32_t
ArchSpec::GetMaximumOpcodeByteSize() const;
Added an AddressClass to the Instruction class in Disassembler.h.
This allows decoded instructions to know know if they are code,
code with alternate ISA (thumb), or even data which can be mixed
into code. The instruction does have an address, but it is a good
idea to cache this value so we don't have to look it up more than
once.
Fixed an issue in Opcode::SetOpcodeBytes() where the length wasn't
getting set.
Changed:
bool
SymbolContextList::AppendIfUnique (const SymbolContext& sc);
To:
bool
SymbolContextList::AppendIfUnique (const SymbolContext& sc,
bool merge_symbol_into_function);
This function was typically being used when looking up functions
and symbols. Now if you lookup a function, then find the symbol,
they can be merged into the same symbol context and not cause
multiple symbol contexts to appear in a symbol context list that
describes the same function.
Fixed the SymbolContext not equal operator which was causing mixed
mode disassembly to not work ("disassembler --mixed --name main").
Modified the disassembler classes to know about the fact we know,
for a given architecture, what the min and max opcode byte sizes
are. The InstructionList class was modified to return the max
opcode byte size for all of the instructions in its list.
These two fixes means when disassemble a list of instructions and dump
them and show the opcode bytes, we can format the output more
intelligently when showing opcode bytes. This affects any architectures
that have varying opcode byte sizes (x86_64 and i386). Knowing the max
opcode byte size also helps us to be able to disassemble N instructions
without having to re-read data if we didn't read enough bytes.
Added the ability to set the architecture for the disassemble command.
This means you can easily cross disassemble data for any supported
architecture. I also added the ability to specify "thumb" as an
architecture so that we can force disassembly into thumb mode when
needed. In GDB this was done using a hack of specifying an odd
address when disassembling. I don't want to repeat this hack in LLDB,
so the auto detection between ARM and thumb is failing, just specify
thumb when disassembling:
(lldb) disassemble --arch thumb --name main
You can also have data in say an x86_64 file executable and disassemble
data as any other supported architecture:
% lldb a.out
Current executable set to 'a.out' (x86_64).
(lldb) b main
(lldb) run
(lldb) disassemble --arch thumb --count 2 --start-address 0x0000000100001080 --bytes
0x100001080: 0xb580 push {r7, lr}
0x100001082: 0xaf00 add r7, sp, #0
Fixed Target::ReadMemory(...) to be able to deal with Address argument object
that isn't section offset. When an address object was supplied that was
out on the heap or stack, target read memory would fail. Disassembly uses
Target::ReadMemory(...), and the example above where we disassembler thumb
opcodes in an x86 binary was failing do to this bug.
llvm-svn: 128347
2011-03-27 03:14:58 +08:00
|
|
|
{ eByteOrderLittle, 4, 4, 4, llvm::Triple::sparc , ArchSpec::eCore_sparc_generic , "sparc" },
|
|
|
|
|
{ eByteOrderLittle, 8, 4, 4, llvm::Triple::sparcv9, ArchSpec::eCore_sparc9_generic , "sparcv9" },
|
2011-02-23 08:35:02 +08:00
|
|
|
|
2011-04-14 06:47:15 +08:00
|
|
|
{ eByteOrderLittle, 4, 1, 15, llvm::Triple::x86 , ArchSpec::eCore_x86_32_i386 , "i386" },
|
|
|
|
|
{ eByteOrderLittle, 4, 1, 15, llvm::Triple::x86 , ArchSpec::eCore_x86_32_i486 , "i486" },
|
|
|
|
|
{ eByteOrderLittle, 4, 1, 15, llvm::Triple::x86 , ArchSpec::eCore_x86_32_i486sx , "i486sx" },
|
2011-02-23 08:35:02 +08:00
|
|
|
|
2012-09-20 06:25:17 +08:00
|
|
|
{ eByteOrderLittle, 8, 1, 15, llvm::Triple::x86_64 , ArchSpec::eCore_x86_64_x86_64 , "x86_64" },
|
2014-01-23 07:42:03 +08:00
|
|
|
{ eByteOrderLittle, 8, 1, 15, llvm::Triple::x86_64 , ArchSpec::eCore_x86_64_x86_64h , "x86_64h" },
|
2014-02-19 19:16:46 +08:00
|
|
|
{ eByteOrderLittle, 4, 4, 4, llvm::Triple::hexagon , ArchSpec::eCore_hexagon_generic, "hexagon" },
|
|
|
|
|
{ eByteOrderLittle, 4, 4, 4, llvm::Triple::hexagon , ArchSpec::eCore_hexagon_hexagonv4, "hexagonv4" },
|
|
|
|
|
{ eByteOrderLittle, 4, 4, 4, llvm::Triple::hexagon , ArchSpec::eCore_hexagon_hexagonv5, "hexagonv5" },
|
|
|
|
|
|
2012-09-20 06:25:17 +08:00
|
|
|
{ eByteOrderLittle, 4, 4, 4 , llvm::Triple::UnknownArch , ArchSpec::eCore_uknownMach32 , "unknown-mach-32" },
|
|
|
|
|
{ eByteOrderLittle, 8, 4, 4 , llvm::Triple::UnknownArch , ArchSpec::eCore_uknownMach64 , "unknown-mach-64" }
|
2010-06-11 11:25:34 +08:00
|
|
|
};
|
|
|
|
|
|
2011-02-23 08:35:02 +08:00
|
|
|
struct ArchDefinitionEntry
|
|
|
|
|
{
|
|
|
|
|
ArchSpec::Core core;
|
|
|
|
|
uint32_t cpu;
|
|
|
|
|
uint32_t sub;
|
2012-09-20 06:25:17 +08:00
|
|
|
uint32_t cpu_mask;
|
|
|
|
|
uint32_t sub_mask;
|
2011-02-23 08:35:02 +08:00
|
|
|
};
|
2010-06-11 11:25:34 +08:00
|
|
|
|
2011-02-23 08:35:02 +08:00
|
|
|
struct ArchDefinition
|
2010-06-09 00:52:24 +08:00
|
|
|
{
|
2011-02-23 08:35:02 +08:00
|
|
|
ArchitectureType type;
|
|
|
|
|
size_t num_entries;
|
|
|
|
|
const ArchDefinitionEntry *entries;
|
|
|
|
|
const char *name;
|
2010-06-09 00:52:24 +08:00
|
|
|
};
|
|
|
|
|
|
|
|
|
|
|
2013-01-26 02:06:21 +08:00
|
|
|
size_t
|
2011-04-14 06:47:15 +08:00
|
|
|
ArchSpec::AutoComplete (const char *name, StringList &matches)
|
|
|
|
|
{
|
|
|
|
|
uint32_t i;
|
|
|
|
|
if (name && name[0])
|
|
|
|
|
{
|
|
|
|
|
for (i = 0; i < ArchSpec::kNumCores; ++i)
|
|
|
|
|
{
|
|
|
|
|
if (NameMatches(g_core_definitions[i].name, eNameMatchStartsWith, name))
|
|
|
|
|
matches.AppendString (g_core_definitions[i].name);
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
else
|
|
|
|
|
{
|
|
|
|
|
for (i = 0; i < ArchSpec::kNumCores; ++i)
|
|
|
|
|
matches.AppendString (g_core_definitions[i].name);
|
|
|
|
|
}
|
|
|
|
|
return matches.GetSize();
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
2011-02-23 08:35:02 +08:00
|
|
|
#define CPU_ANY (UINT32_MAX)
|
2010-06-09 00:52:24 +08:00
|
|
|
|
2011-02-23 08:35:02 +08:00
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
|
// A table that gets searched linearly for matches. This table is used to
|
|
|
|
|
// convert cpu type and subtypes to architecture names, and to convert
|
|
|
|
|
// architecture names to cpu types and subtypes. The ordering is important and
|
|
|
|
|
// allows the precedence to be set when the table is built.
|
2012-09-20 06:25:17 +08:00
|
|
|
#define SUBTYPE_MASK 0x00FFFFFFu
|
2011-02-23 08:35:02 +08:00
|
|
|
static const ArchDefinitionEntry g_macho_arch_entries[] =
|
|
|
|
|
{
|
2013-08-27 13:04:57 +08:00
|
|
|
{ ArchSpec::eCore_arm_generic , llvm::MachO::CPU_TYPE_ARM , CPU_ANY, UINT32_MAX , UINT32_MAX },
|
|
|
|
|
{ ArchSpec::eCore_arm_generic , llvm::MachO::CPU_TYPE_ARM , 0 , UINT32_MAX , SUBTYPE_MASK },
|
|
|
|
|
{ ArchSpec::eCore_arm_armv4 , llvm::MachO::CPU_TYPE_ARM , 5 , UINT32_MAX , SUBTYPE_MASK },
|
|
|
|
|
{ ArchSpec::eCore_arm_armv4t , llvm::MachO::CPU_TYPE_ARM , 5 , UINT32_MAX , SUBTYPE_MASK },
|
|
|
|
|
{ ArchSpec::eCore_arm_armv6 , llvm::MachO::CPU_TYPE_ARM , 6 , UINT32_MAX , SUBTYPE_MASK },
|
2013-10-08 11:01:08 +08:00
|
|
|
{ ArchSpec::eCore_arm_armv6m , llvm::MachO::CPU_TYPE_ARM , 14 , UINT32_MAX , SUBTYPE_MASK },
|
2013-08-27 13:04:57 +08:00
|
|
|
{ ArchSpec::eCore_arm_armv5 , llvm::MachO::CPU_TYPE_ARM , 7 , UINT32_MAX , SUBTYPE_MASK },
|
|
|
|
|
{ ArchSpec::eCore_arm_armv5e , llvm::MachO::CPU_TYPE_ARM , 7 , UINT32_MAX , SUBTYPE_MASK },
|
|
|
|
|
{ ArchSpec::eCore_arm_armv5t , llvm::MachO::CPU_TYPE_ARM , 7 , UINT32_MAX , SUBTYPE_MASK },
|
|
|
|
|
{ ArchSpec::eCore_arm_xscale , llvm::MachO::CPU_TYPE_ARM , 8 , UINT32_MAX , SUBTYPE_MASK },
|
|
|
|
|
{ ArchSpec::eCore_arm_armv7 , llvm::MachO::CPU_TYPE_ARM , 9 , UINT32_MAX , SUBTYPE_MASK },
|
|
|
|
|
{ ArchSpec::eCore_arm_armv7f , llvm::MachO::CPU_TYPE_ARM , 10 , UINT32_MAX , SUBTYPE_MASK },
|
|
|
|
|
{ ArchSpec::eCore_arm_armv7s , llvm::MachO::CPU_TYPE_ARM , 11 , UINT32_MAX , SUBTYPE_MASK },
|
|
|
|
|
{ ArchSpec::eCore_arm_armv7k , llvm::MachO::CPU_TYPE_ARM , 12 , UINT32_MAX , SUBTYPE_MASK },
|
|
|
|
|
{ ArchSpec::eCore_arm_armv7m , llvm::MachO::CPU_TYPE_ARM , 15 , UINT32_MAX , SUBTYPE_MASK },
|
|
|
|
|
{ ArchSpec::eCore_arm_armv7em , llvm::MachO::CPU_TYPE_ARM , 16 , UINT32_MAX , SUBTYPE_MASK },
|
|
|
|
|
{ ArchSpec::eCore_thumb , llvm::MachO::CPU_TYPE_ARM , 0 , UINT32_MAX , SUBTYPE_MASK },
|
|
|
|
|
{ ArchSpec::eCore_thumbv4t , llvm::MachO::CPU_TYPE_ARM , 5 , UINT32_MAX , SUBTYPE_MASK },
|
|
|
|
|
{ ArchSpec::eCore_thumbv5 , llvm::MachO::CPU_TYPE_ARM , 7 , UINT32_MAX , SUBTYPE_MASK },
|
|
|
|
|
{ ArchSpec::eCore_thumbv5e , llvm::MachO::CPU_TYPE_ARM , 7 , UINT32_MAX , SUBTYPE_MASK },
|
|
|
|
|
{ ArchSpec::eCore_thumbv6 , llvm::MachO::CPU_TYPE_ARM , 6 , UINT32_MAX , SUBTYPE_MASK },
|
2013-10-08 11:01:08 +08:00
|
|
|
{ ArchSpec::eCore_thumbv6m , llvm::MachO::CPU_TYPE_ARM , 14 , UINT32_MAX , SUBTYPE_MASK },
|
2013-08-27 13:04:57 +08:00
|
|
|
{ ArchSpec::eCore_thumbv7 , llvm::MachO::CPU_TYPE_ARM , 9 , UINT32_MAX , SUBTYPE_MASK },
|
|
|
|
|
{ ArchSpec::eCore_thumbv7f , llvm::MachO::CPU_TYPE_ARM , 10 , UINT32_MAX , SUBTYPE_MASK },
|
|
|
|
|
{ ArchSpec::eCore_thumbv7s , llvm::MachO::CPU_TYPE_ARM , 11 , UINT32_MAX , SUBTYPE_MASK },
|
|
|
|
|
{ ArchSpec::eCore_thumbv7k , llvm::MachO::CPU_TYPE_ARM , 12 , UINT32_MAX , SUBTYPE_MASK },
|
|
|
|
|
{ ArchSpec::eCore_thumbv7m , llvm::MachO::CPU_TYPE_ARM , 15 , UINT32_MAX , SUBTYPE_MASK },
|
|
|
|
|
{ ArchSpec::eCore_thumbv7em , llvm::MachO::CPU_TYPE_ARM , 16 , UINT32_MAX , SUBTYPE_MASK },
|
|
|
|
|
{ ArchSpec::eCore_ppc_generic , llvm::MachO::CPU_TYPE_POWERPC , CPU_ANY, UINT32_MAX , UINT32_MAX },
|
|
|
|
|
{ ArchSpec::eCore_ppc_generic , llvm::MachO::CPU_TYPE_POWERPC , 0 , UINT32_MAX , SUBTYPE_MASK },
|
|
|
|
|
{ ArchSpec::eCore_ppc_ppc601 , llvm::MachO::CPU_TYPE_POWERPC , 1 , UINT32_MAX , SUBTYPE_MASK },
|
|
|
|
|
{ ArchSpec::eCore_ppc_ppc602 , llvm::MachO::CPU_TYPE_POWERPC , 2 , UINT32_MAX , SUBTYPE_MASK },
|
|
|
|
|
{ ArchSpec::eCore_ppc_ppc603 , llvm::MachO::CPU_TYPE_POWERPC , 3 , UINT32_MAX , SUBTYPE_MASK },
|
|
|
|
|
{ ArchSpec::eCore_ppc_ppc603e , llvm::MachO::CPU_TYPE_POWERPC , 4 , UINT32_MAX , SUBTYPE_MASK },
|
|
|
|
|
{ ArchSpec::eCore_ppc_ppc603ev , llvm::MachO::CPU_TYPE_POWERPC , 5 , UINT32_MAX , SUBTYPE_MASK },
|
|
|
|
|
{ ArchSpec::eCore_ppc_ppc604 , llvm::MachO::CPU_TYPE_POWERPC , 6 , UINT32_MAX , SUBTYPE_MASK },
|
|
|
|
|
{ ArchSpec::eCore_ppc_ppc604e , llvm::MachO::CPU_TYPE_POWERPC , 7 , UINT32_MAX , SUBTYPE_MASK },
|
|
|
|
|
{ ArchSpec::eCore_ppc_ppc620 , llvm::MachO::CPU_TYPE_POWERPC , 8 , UINT32_MAX , SUBTYPE_MASK },
|
|
|
|
|
{ ArchSpec::eCore_ppc_ppc750 , llvm::MachO::CPU_TYPE_POWERPC , 9 , UINT32_MAX , SUBTYPE_MASK },
|
|
|
|
|
{ ArchSpec::eCore_ppc_ppc7400 , llvm::MachO::CPU_TYPE_POWERPC , 10 , UINT32_MAX , SUBTYPE_MASK },
|
|
|
|
|
{ ArchSpec::eCore_ppc_ppc7450 , llvm::MachO::CPU_TYPE_POWERPC , 11 , UINT32_MAX , SUBTYPE_MASK },
|
|
|
|
|
{ ArchSpec::eCore_ppc_ppc970 , llvm::MachO::CPU_TYPE_POWERPC , 100 , UINT32_MAX , SUBTYPE_MASK },
|
|
|
|
|
{ ArchSpec::eCore_ppc64_generic , llvm::MachO::CPU_TYPE_POWERPC64 , 0 , UINT32_MAX , SUBTYPE_MASK },
|
|
|
|
|
{ ArchSpec::eCore_ppc64_ppc970_64 , llvm::MachO::CPU_TYPE_POWERPC64 , 100 , UINT32_MAX , SUBTYPE_MASK },
|
|
|
|
|
{ ArchSpec::eCore_x86_32_i386 , llvm::MachO::CPU_TYPE_I386 , 3 , UINT32_MAX , SUBTYPE_MASK },
|
|
|
|
|
{ ArchSpec::eCore_x86_32_i486 , llvm::MachO::CPU_TYPE_I386 , 4 , UINT32_MAX , SUBTYPE_MASK },
|
|
|
|
|
{ ArchSpec::eCore_x86_32_i486sx , llvm::MachO::CPU_TYPE_I386 , 0x84 , UINT32_MAX , SUBTYPE_MASK },
|
2014-01-23 07:42:03 +08:00
|
|
|
{ ArchSpec::eCore_x86_32_i386 , llvm::MachO::CPU_TYPE_I386 , CPU_ANY, UINT32_MAX , UINT32_MAX },
|
2013-08-27 13:04:57 +08:00
|
|
|
{ ArchSpec::eCore_x86_64_x86_64 , llvm::MachO::CPU_TYPE_X86_64 , 3 , UINT32_MAX , SUBTYPE_MASK },
|
|
|
|
|
{ ArchSpec::eCore_x86_64_x86_64 , llvm::MachO::CPU_TYPE_X86_64 , 4 , UINT32_MAX , SUBTYPE_MASK },
|
2014-01-23 07:42:03 +08:00
|
|
|
{ ArchSpec::eCore_x86_64_x86_64h , llvm::MachO::CPU_TYPE_X86_64 , 8 , UINT32_MAX , SUBTYPE_MASK },
|
|
|
|
|
{ ArchSpec::eCore_x86_64_x86_64 , llvm::MachO::CPU_TYPE_X86_64 , CPU_ANY, UINT32_MAX , UINT32_MAX },
|
2012-09-20 06:25:17 +08:00
|
|
|
// Catch any unknown mach architectures so we can always use the object and symbol mach-o files
|
2013-08-27 13:04:57 +08:00
|
|
|
{ ArchSpec::eCore_uknownMach32 , 0 , 0 , 0xFF000000u, 0x00000000u },
|
|
|
|
|
{ ArchSpec::eCore_uknownMach64 , llvm::MachO::CPU_ARCH_ABI64 , 0 , 0xFF000000u, 0x00000000u }
|
2011-02-23 08:35:02 +08:00
|
|
|
};
|
|
|
|
|
static const ArchDefinition g_macho_arch_def = {
|
|
|
|
|
eArchTypeMachO,
|
|
|
|
|
sizeof(g_macho_arch_entries)/sizeof(g_macho_arch_entries[0]),
|
|
|
|
|
g_macho_arch_entries,
|
|
|
|
|
"mach-o"
|
|
|
|
|
};
|
2010-06-11 11:25:34 +08:00
|
|
|
|
2011-02-23 08:35:02 +08:00
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
|
// A table that gets searched linearly for matches. This table is used to
|
|
|
|
|
// convert cpu type and subtypes to architecture names, and to convert
|
|
|
|
|
// architecture names to cpu types and subtypes. The ordering is important and
|
|
|
|
|
// allows the precedence to be set when the table is built.
|
|
|
|
|
static const ArchDefinitionEntry g_elf_arch_entries[] =
|
|
|
|
|
{
|
2012-09-20 06:25:17 +08:00
|
|
|
{ ArchSpec::eCore_sparc_generic , llvm::ELF::EM_SPARC , LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu }, // Sparc
|
|
|
|
|
{ ArchSpec::eCore_x86_32_i386 , llvm::ELF::EM_386 , LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu }, // Intel 80386
|
|
|
|
|
{ ArchSpec::eCore_x86_32_i486 , llvm::ELF::EM_486 , LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu }, // Intel 486 (deprecated)
|
|
|
|
|
{ ArchSpec::eCore_ppc_generic , llvm::ELF::EM_PPC , LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu }, // PowerPC
|
|
|
|
|
{ ArchSpec::eCore_ppc64_generic , llvm::ELF::EM_PPC64 , LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu }, // PowerPC64
|
|
|
|
|
{ ArchSpec::eCore_arm_generic , llvm::ELF::EM_ARM , LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu }, // ARM
|
|
|
|
|
{ ArchSpec::eCore_sparc9_generic , llvm::ELF::EM_SPARCV9, LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu }, // SPARC V9
|
2013-10-10 08:59:47 +08:00
|
|
|
{ ArchSpec::eCore_x86_64_x86_64 , llvm::ELF::EM_X86_64 , LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu }, // AMD64
|
2014-02-19 19:16:46 +08:00
|
|
|
{ ArchSpec::eCore_mips64 , llvm::ELF::EM_MIPS , LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu }, // MIPS
|
|
|
|
|
{ ArchSpec::eCore_hexagon_generic , llvm::ELF::EM_HEXAGON, LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu } // HEXAGON
|
2010-06-11 11:25:34 +08:00
|
|
|
};
|
|
|
|
|
|
2011-02-23 08:35:02 +08:00
|
|
|
static const ArchDefinition g_elf_arch_def = {
|
|
|
|
|
eArchTypeELF,
|
|
|
|
|
sizeof(g_elf_arch_entries)/sizeof(g_elf_arch_entries[0]),
|
|
|
|
|
g_elf_arch_entries,
|
|
|
|
|
"elf",
|
|
|
|
|
};
|
2010-06-11 11:25:34 +08:00
|
|
|
|
2013-08-27 13:04:33 +08:00
|
|
|
static const ArchDefinitionEntry g_coff_arch_entries[] =
|
|
|
|
|
{
|
|
|
|
|
{ ArchSpec::eCore_x86_32_i386 , llvm::COFF::IMAGE_FILE_MACHINE_I386 , LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu }, // Intel 80386
|
|
|
|
|
{ ArchSpec::eCore_ppc_generic , llvm::COFF::IMAGE_FILE_MACHINE_POWERPC , LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu }, // PowerPC
|
|
|
|
|
{ ArchSpec::eCore_ppc_generic , llvm::COFF::IMAGE_FILE_MACHINE_POWERPCFP, LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu }, // PowerPC (with FPU)
|
|
|
|
|
{ ArchSpec::eCore_arm_generic , llvm::COFF::IMAGE_FILE_MACHINE_ARM , LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu }, // ARM
|
|
|
|
|
{ ArchSpec::eCore_arm_armv7 , llvm::COFF::IMAGE_FILE_MACHINE_ARMV7 , LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu }, // ARMv7
|
|
|
|
|
{ ArchSpec::eCore_thumb , llvm::COFF::IMAGE_FILE_MACHINE_THUMB , LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu }, // ARMv7
|
|
|
|
|
{ ArchSpec::eCore_x86_64_x86_64, llvm::COFF::IMAGE_FILE_MACHINE_AMD64 , LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu } // AMD64
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
static const ArchDefinition g_coff_arch_def = {
|
|
|
|
|
eArchTypeCOFF,
|
|
|
|
|
sizeof(g_coff_arch_entries)/sizeof(g_coff_arch_entries[0]),
|
|
|
|
|
g_coff_arch_entries,
|
|
|
|
|
"pe-coff",
|
|
|
|
|
};
|
|
|
|
|
|
2011-02-23 08:35:02 +08:00
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
|
// Table of all ArchDefinitions
|
|
|
|
|
static const ArchDefinition *g_arch_definitions[] = {
|
|
|
|
|
&g_macho_arch_def,
|
2013-08-27 13:04:33 +08:00
|
|
|
&g_elf_arch_def,
|
|
|
|
|
&g_coff_arch_def
|
2011-02-23 08:35:02 +08:00
|
|
|
};
|
2010-06-09 00:52:24 +08:00
|
|
|
|
2011-02-23 08:35:02 +08:00
|
|
|
static const size_t k_num_arch_definitions =
|
|
|
|
|
sizeof(g_arch_definitions) / sizeof(g_arch_definitions[0]);
|
2010-06-09 00:52:24 +08:00
|
|
|
|
2011-02-23 08:35:02 +08:00
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
|
// Static helper functions.
|
2010-06-09 00:52:24 +08:00
|
|
|
|
2011-02-23 08:35:02 +08:00
|
|
|
|
|
|
|
|
// Get the architecture definition for a given object type.
|
|
|
|
|
static const ArchDefinition *
|
|
|
|
|
FindArchDefinition (ArchitectureType arch_type)
|
2010-06-09 00:52:24 +08:00
|
|
|
{
|
2011-02-23 08:35:02 +08:00
|
|
|
for (unsigned int i = 0; i < k_num_arch_definitions; ++i)
|
|
|
|
|
{
|
|
|
|
|
const ArchDefinition *def = g_arch_definitions[i];
|
|
|
|
|
if (def->type == arch_type)
|
|
|
|
|
return def;
|
|
|
|
|
}
|
|
|
|
|
return NULL;
|
2010-06-09 00:52:24 +08:00
|
|
|
}
|
|
|
|
|
|
2011-02-23 08:35:02 +08:00
|
|
|
// Get an architecture definition by name.
|
|
|
|
|
static const CoreDefinition *
|
|
|
|
|
FindCoreDefinition (llvm::StringRef name)
|
2010-06-09 00:52:24 +08:00
|
|
|
{
|
2011-02-23 08:35:02 +08:00
|
|
|
for (unsigned int i = 0; i < ArchSpec::kNumCores; ++i)
|
2010-06-09 00:52:24 +08:00
|
|
|
{
|
2011-02-23 08:35:02 +08:00
|
|
|
if (name.equals_lower(g_core_definitions[i].name))
|
|
|
|
|
return &g_core_definitions[i];
|
2010-06-09 00:52:24 +08:00
|
|
|
}
|
2011-02-23 08:35:02 +08:00
|
|
|
return NULL;
|
2010-06-09 00:52:24 +08:00
|
|
|
}
|
|
|
|
|
|
2011-02-23 08:35:02 +08:00
|
|
|
static inline const CoreDefinition *
|
|
|
|
|
FindCoreDefinition (ArchSpec::Core core)
|
2010-06-09 00:52:24 +08:00
|
|
|
{
|
2011-02-23 08:35:02 +08:00
|
|
|
if (core >= 0 && core < ArchSpec::kNumCores)
|
|
|
|
|
return &g_core_definitions[core];
|
|
|
|
|
return NULL;
|
2010-06-09 00:52:24 +08:00
|
|
|
}
|
|
|
|
|
|
2011-02-23 08:35:02 +08:00
|
|
|
// Get a definition entry by cpu type and subtype.
|
|
|
|
|
static const ArchDefinitionEntry *
|
|
|
|
|
FindArchDefinitionEntry (const ArchDefinition *def, uint32_t cpu, uint32_t sub)
|
2010-06-09 00:52:24 +08:00
|
|
|
{
|
2011-02-23 08:35:02 +08:00
|
|
|
if (def == NULL)
|
2010-06-11 11:25:34 +08:00
|
|
|
return NULL;
|
|
|
|
|
|
2011-02-23 08:35:02 +08:00
|
|
|
const ArchDefinitionEntry *entries = def->entries;
|
|
|
|
|
for (size_t i = 0; i < def->num_entries; ++i)
|
2010-06-09 00:52:24 +08:00
|
|
|
{
|
2012-09-20 06:25:17 +08:00
|
|
|
if (entries[i].cpu == (cpu & entries[i].cpu_mask))
|
|
|
|
|
if (entries[i].sub == (sub & entries[i].sub_mask))
|
|
|
|
|
return &entries[i];
|
2010-06-09 00:52:24 +08:00
|
|
|
}
|
2011-02-23 08:35:02 +08:00
|
|
|
return NULL;
|
2010-06-09 00:52:24 +08:00
|
|
|
}
|
|
|
|
|
|
2011-02-23 08:35:02 +08:00
|
|
|
static const ArchDefinitionEntry *
|
|
|
|
|
FindArchDefinitionEntry (const ArchDefinition *def, ArchSpec::Core core)
|
2010-06-09 00:52:24 +08:00
|
|
|
{
|
2011-02-23 08:35:02 +08:00
|
|
|
if (def == NULL)
|
|
|
|
|
return NULL;
|
|
|
|
|
|
|
|
|
|
const ArchDefinitionEntry *entries = def->entries;
|
|
|
|
|
for (size_t i = 0; i < def->num_entries; ++i)
|
2010-06-11 11:25:34 +08:00
|
|
|
{
|
2011-02-23 08:35:02 +08:00
|
|
|
if (entries[i].core == core)
|
|
|
|
|
return &entries[i];
|
2010-06-11 11:25:34 +08:00
|
|
|
}
|
2011-02-23 08:35:02 +08:00
|
|
|
return NULL;
|
2010-06-09 00:52:24 +08:00
|
|
|
}
|
|
|
|
|
|
2011-02-23 08:35:02 +08:00
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
|
// Constructors and destructors.
|
2010-06-09 00:52:24 +08:00
|
|
|
|
2011-02-23 08:35:02 +08:00
|
|
|
ArchSpec::ArchSpec() :
|
|
|
|
|
m_triple (),
|
|
|
|
|
m_core (kCore_invalid),
|
2014-01-18 11:02:39 +08:00
|
|
|
m_byte_order (eByteOrderInvalid),
|
|
|
|
|
m_distribution_id ()
|
2010-06-09 00:52:24 +08:00
|
|
|
{
|
|
|
|
|
}
|
|
|
|
|
|
2011-04-08 06:46:35 +08:00
|
|
|
ArchSpec::ArchSpec (const char *triple_cstr, Platform *platform) :
|
2011-02-23 08:35:02 +08:00
|
|
|
m_triple (),
|
|
|
|
|
m_core (kCore_invalid),
|
2014-01-18 11:02:39 +08:00
|
|
|
m_byte_order (eByteOrderInvalid),
|
|
|
|
|
m_distribution_id ()
|
2010-06-11 11:25:34 +08:00
|
|
|
{
|
2011-02-23 08:35:02 +08:00
|
|
|
if (triple_cstr)
|
2011-04-08 06:46:35 +08:00
|
|
|
SetTriple(triple_cstr, platform);
|
2010-06-11 11:25:34 +08:00
|
|
|
}
|
|
|
|
|
|
2012-05-08 09:45:38 +08:00
|
|
|
|
|
|
|
|
ArchSpec::ArchSpec (const char *triple_cstr) :
|
|
|
|
|
m_triple (),
|
|
|
|
|
m_core (kCore_invalid),
|
2014-01-18 11:02:39 +08:00
|
|
|
m_byte_order (eByteOrderInvalid),
|
|
|
|
|
m_distribution_id ()
|
2012-05-08 09:45:38 +08:00
|
|
|
{
|
|
|
|
|
if (triple_cstr)
|
|
|
|
|
SetTriple(triple_cstr);
|
|
|
|
|
}
|
|
|
|
|
|
2011-02-23 08:35:02 +08:00
|
|
|
ArchSpec::ArchSpec(const llvm::Triple &triple) :
|
|
|
|
|
m_triple (),
|
|
|
|
|
m_core (kCore_invalid),
|
2014-01-18 11:02:39 +08:00
|
|
|
m_byte_order (eByteOrderInvalid),
|
|
|
|
|
m_distribution_id ()
|
2010-06-09 00:52:24 +08:00
|
|
|
{
|
2011-02-23 08:35:02 +08:00
|
|
|
SetTriple(triple);
|
2010-06-09 00:52:24 +08:00
|
|
|
}
|
|
|
|
|
|
2011-03-25 05:19:54 +08:00
|
|
|
ArchSpec::ArchSpec (ArchitectureType arch_type, uint32_t cpu, uint32_t subtype) :
|
2011-02-23 08:35:02 +08:00
|
|
|
m_triple (),
|
|
|
|
|
m_core (kCore_invalid),
|
2014-01-18 11:02:39 +08:00
|
|
|
m_byte_order (eByteOrderInvalid),
|
|
|
|
|
m_distribution_id ()
|
2010-06-09 00:52:24 +08:00
|
|
|
{
|
2011-02-23 08:35:02 +08:00
|
|
|
SetArchitecture (arch_type, cpu, subtype);
|
|
|
|
|
}
|
2010-06-09 00:52:24 +08:00
|
|
|
|
2011-02-23 08:35:02 +08:00
|
|
|
ArchSpec::~ArchSpec()
|
2010-06-09 00:52:24 +08:00
|
|
|
{
|
2011-02-23 08:35:02 +08:00
|
|
|
}
|
2010-06-09 00:52:24 +08:00
|
|
|
|
2011-02-23 08:35:02 +08:00
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
|
// Assignment and initialization.
|
2010-06-09 00:52:24 +08:00
|
|
|
|
2011-02-23 08:35:02 +08:00
|
|
|
const ArchSpec&
|
|
|
|
|
ArchSpec::operator= (const ArchSpec& rhs)
|
2010-06-09 00:52:24 +08:00
|
|
|
{
|
2011-02-23 08:35:02 +08:00
|
|
|
if (this != &rhs)
|
|
|
|
|
{
|
|
|
|
|
m_triple = rhs.m_triple;
|
|
|
|
|
m_core = rhs.m_core;
|
|
|
|
|
m_byte_order = rhs.m_byte_order;
|
2014-01-18 11:02:39 +08:00
|
|
|
m_distribution_id = rhs.m_distribution_id;
|
2011-02-23 08:35:02 +08:00
|
|
|
}
|
|
|
|
|
return *this;
|
|
|
|
|
}
|
2010-06-09 00:52:24 +08:00
|
|
|
|
2011-02-23 08:35:02 +08:00
|
|
|
void
|
|
|
|
|
ArchSpec::Clear()
|
2010-06-09 00:52:24 +08:00
|
|
|
{
|
2011-02-23 08:35:02 +08:00
|
|
|
m_triple = llvm::Triple();
|
|
|
|
|
m_core = kCore_invalid;
|
|
|
|
|
m_byte_order = eByteOrderInvalid;
|
2014-01-18 11:02:39 +08:00
|
|
|
m_distribution_id.Clear ();
|
2011-02-23 08:35:02 +08:00
|
|
|
}
|
2010-06-09 00:52:24 +08:00
|
|
|
|
2011-02-23 08:35:02 +08:00
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
|
// Predicates.
|
2010-06-09 00:52:24 +08:00
|
|
|
|
|
|
|
|
|
|
|
|
|
const char *
|
2011-02-23 08:35:02 +08:00
|
|
|
ArchSpec::GetArchitectureName () const
|
2010-06-09 00:52:24 +08:00
|
|
|
{
|
2011-02-23 08:35:02 +08:00
|
|
|
const CoreDefinition *core_def = FindCoreDefinition (m_core);
|
|
|
|
|
if (core_def)
|
|
|
|
|
return core_def->name;
|
|
|
|
|
return "unknown";
|
2010-06-09 00:52:24 +08:00
|
|
|
}
|
|
|
|
|
|
2011-02-23 08:35:02 +08:00
|
|
|
uint32_t
|
|
|
|
|
ArchSpec::GetMachOCPUType () const
|
2010-06-09 00:52:24 +08:00
|
|
|
{
|
2011-02-23 08:35:02 +08:00
|
|
|
const CoreDefinition *core_def = FindCoreDefinition (m_core);
|
|
|
|
|
if (core_def)
|
2010-06-09 00:52:24 +08:00
|
|
|
{
|
2011-02-23 08:35:02 +08:00
|
|
|
const ArchDefinitionEntry *arch_def = FindArchDefinitionEntry (&g_macho_arch_def, core_def->core);
|
|
|
|
|
if (arch_def)
|
2010-06-09 00:52:24 +08:00
|
|
|
{
|
2011-02-23 08:35:02 +08:00
|
|
|
return arch_def->cpu;
|
2010-06-09 00:52:24 +08:00
|
|
|
}
|
|
|
|
|
}
|
2011-02-23 08:35:02 +08:00
|
|
|
return LLDB_INVALID_CPUTYPE;
|
|
|
|
|
}
|
2010-06-09 00:52:24 +08:00
|
|
|
|
2011-02-23 08:35:02 +08:00
|
|
|
uint32_t
|
|
|
|
|
ArchSpec::GetMachOCPUSubType () const
|
|
|
|
|
{
|
|
|
|
|
const CoreDefinition *core_def = FindCoreDefinition (m_core);
|
|
|
|
|
if (core_def)
|
2010-06-09 00:52:24 +08:00
|
|
|
{
|
2011-02-23 08:35:02 +08:00
|
|
|
const ArchDefinitionEntry *arch_def = FindArchDefinitionEntry (&g_macho_arch_def, core_def->core);
|
|
|
|
|
if (arch_def)
|
2010-06-09 00:52:24 +08:00
|
|
|
{
|
2011-03-24 12:28:38 +08:00
|
|
|
return arch_def->sub;
|
2010-06-09 00:52:24 +08:00
|
|
|
}
|
|
|
|
|
}
|
2011-02-23 08:35:02 +08:00
|
|
|
return LLDB_INVALID_CPUTYPE;
|
2010-06-09 00:52:24 +08:00
|
|
|
}
|
|
|
|
|
|
2011-02-23 08:35:02 +08:00
|
|
|
llvm::Triple::ArchType
|
|
|
|
|
ArchSpec::GetMachine () const
|
2010-06-09 00:52:24 +08:00
|
|
|
{
|
2011-02-23 08:35:02 +08:00
|
|
|
const CoreDefinition *core_def = FindCoreDefinition (m_core);
|
|
|
|
|
if (core_def)
|
|
|
|
|
return core_def->machine;
|
|
|
|
|
|
|
|
|
|
return llvm::Triple::UnknownArch;
|
2010-06-09 00:52:24 +08:00
|
|
|
}
|
|
|
|
|
|
2014-01-18 11:02:39 +08:00
|
|
|
const ConstString&
|
|
|
|
|
ArchSpec::GetDistributionId () const
|
|
|
|
|
{
|
|
|
|
|
return m_distribution_id;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
void
|
|
|
|
|
ArchSpec::SetDistributionId (const char* distribution_id)
|
|
|
|
|
{
|
|
|
|
|
m_distribution_id.SetCString (distribution_id);
|
|
|
|
|
}
|
|
|
|
|
|
2010-06-09 00:52:24 +08:00
|
|
|
uint32_t
|
|
|
|
|
ArchSpec::GetAddressByteSize() const
|
|
|
|
|
{
|
2011-02-23 08:35:02 +08:00
|
|
|
const CoreDefinition *core_def = FindCoreDefinition (m_core);
|
|
|
|
|
if (core_def)
|
|
|
|
|
return core_def->addr_byte_size;
|
2010-06-11 11:25:34 +08:00
|
|
|
return 0;
|
2010-06-09 00:52:24 +08:00
|
|
|
}
|
|
|
|
|
|
2011-02-23 08:35:02 +08:00
|
|
|
ByteOrder
|
|
|
|
|
ArchSpec::GetDefaultEndian () const
|
2010-06-09 00:52:24 +08:00
|
|
|
{
|
2011-02-23 08:35:02 +08:00
|
|
|
const CoreDefinition *core_def = FindCoreDefinition (m_core);
|
|
|
|
|
if (core_def)
|
|
|
|
|
return core_def->default_byte_order;
|
|
|
|
|
return eByteOrderInvalid;
|
2010-06-09 00:52:24 +08:00
|
|
|
}
|
|
|
|
|
|
2011-02-23 08:35:02 +08:00
|
|
|
lldb::ByteOrder
|
|
|
|
|
ArchSpec::GetByteOrder () const
|
2011-02-16 05:59:32 +08:00
|
|
|
{
|
2011-02-23 08:35:02 +08:00
|
|
|
if (m_byte_order == eByteOrderInvalid)
|
|
|
|
|
return GetDefaultEndian();
|
|
|
|
|
return m_byte_order;
|
2011-02-16 05:59:32 +08:00
|
|
|
}
|
|
|
|
|
|
2011-02-23 08:35:02 +08:00
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
|
// Mutators.
|
|
|
|
|
|
|
|
|
|
bool
|
|
|
|
|
ArchSpec::SetTriple (const llvm::Triple &triple)
|
2011-02-16 05:59:32 +08:00
|
|
|
{
|
2011-02-23 08:35:02 +08:00
|
|
|
m_triple = triple;
|
2011-02-16 05:59:32 +08:00
|
|
|
|
2011-02-23 08:35:02 +08:00
|
|
|
llvm::StringRef arch_name (m_triple.getArchName());
|
|
|
|
|
const CoreDefinition *core_def = FindCoreDefinition (arch_name);
|
|
|
|
|
if (core_def)
|
2011-02-16 05:59:32 +08:00
|
|
|
{
|
2011-02-23 08:35:02 +08:00
|
|
|
m_core = core_def->core;
|
2011-04-08 06:46:35 +08:00
|
|
|
// Set the byte order to the default byte order for an architecture.
|
|
|
|
|
// This can be modified if needed for cases when cores handle both
|
|
|
|
|
// big and little endian
|
|
|
|
|
m_byte_order = core_def->default_byte_order;
|
2011-02-16 05:59:32 +08:00
|
|
|
}
|
|
|
|
|
else
|
|
|
|
|
{
|
2011-02-23 08:35:02 +08:00
|
|
|
Clear();
|
2011-02-16 05:59:32 +08:00
|
|
|
}
|
|
|
|
|
|
2011-02-23 08:35:02 +08:00
|
|
|
|
|
|
|
|
return IsValid();
|
2011-02-16 05:59:32 +08:00
|
|
|
}
|
2010-06-09 00:52:24 +08:00
|
|
|
|
2012-09-20 06:25:17 +08:00
|
|
|
static bool
|
|
|
|
|
ParseMachCPUDashSubtypeTriple (const char *triple_cstr, ArchSpec &arch)
|
2012-05-08 09:45:38 +08:00
|
|
|
{
|
2012-09-20 06:25:17 +08:00
|
|
|
// Accept "12-10" or "12.10" as cpu type/subtype
|
|
|
|
|
if (isdigit(triple_cstr[0]))
|
2012-05-08 09:45:38 +08:00
|
|
|
{
|
2012-09-20 06:25:17 +08:00
|
|
|
char *end = NULL;
|
|
|
|
|
errno = 0;
|
2013-01-26 02:06:21 +08:00
|
|
|
uint32_t cpu = (uint32_t)::strtoul (triple_cstr, &end, 0);
|
2012-09-20 06:25:17 +08:00
|
|
|
if (errno == 0 && cpu != 0 && end && ((*end == '-') || (*end == '.')))
|
2012-08-08 09:19:34 +08:00
|
|
|
{
|
2012-09-19 07:27:18 +08:00
|
|
|
errno = 0;
|
2013-01-26 02:06:21 +08:00
|
|
|
uint32_t sub = (uint32_t)::strtoul (end + 1, &end, 0);
|
2012-09-20 06:25:17 +08:00
|
|
|
if (errno == 0 && end && ((*end == '-') || (*end == '.') || (*end == '\0')))
|
2012-08-08 09:19:34 +08:00
|
|
|
{
|
2012-09-20 06:25:17 +08:00
|
|
|
if (arch.SetArchitecture (eArchTypeMachO, cpu, sub))
|
2012-08-08 09:19:34 +08:00
|
|
|
{
|
2012-09-20 06:25:17 +08:00
|
|
|
if (*end == '-')
|
2012-08-08 09:19:34 +08:00
|
|
|
{
|
2012-09-20 06:25:17 +08:00
|
|
|
llvm::StringRef vendor_os (end + 1);
|
|
|
|
|
size_t dash_pos = vendor_os.find('-');
|
|
|
|
|
if (dash_pos != llvm::StringRef::npos)
|
2012-08-08 09:19:34 +08:00
|
|
|
{
|
2012-09-20 06:25:17 +08:00
|
|
|
llvm::StringRef vendor_str(vendor_os.substr(0, dash_pos));
|
|
|
|
|
arch.GetTriple().setVendorName(vendor_str);
|
|
|
|
|
const size_t vendor_start_pos = dash_pos+1;
|
2013-01-26 02:06:21 +08:00
|
|
|
dash_pos = vendor_os.find('-', vendor_start_pos);
|
2012-09-20 06:25:17 +08:00
|
|
|
if (dash_pos == llvm::StringRef::npos)
|
2012-08-08 09:19:34 +08:00
|
|
|
{
|
2012-09-20 06:25:17 +08:00
|
|
|
if (vendor_start_pos < vendor_os.size())
|
|
|
|
|
arch.GetTriple().setOSName(vendor_os.substr(vendor_start_pos));
|
|
|
|
|
}
|
|
|
|
|
else
|
|
|
|
|
{
|
|
|
|
|
arch.GetTriple().setOSName(vendor_os.substr(vendor_start_pos, dash_pos - vendor_start_pos));
|
2012-08-08 09:19:34 +08:00
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
}
|
2012-09-20 06:25:17 +08:00
|
|
|
return true;
|
2012-08-08 09:19:34 +08:00
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
}
|
2012-09-20 06:25:17 +08:00
|
|
|
}
|
|
|
|
|
return false;
|
|
|
|
|
}
|
|
|
|
|
bool
|
|
|
|
|
ArchSpec::SetTriple (const char *triple_cstr)
|
|
|
|
|
{
|
|
|
|
|
if (triple_cstr && triple_cstr[0])
|
|
|
|
|
{
|
|
|
|
|
if (ParseMachCPUDashSubtypeTriple (triple_cstr, *this))
|
|
|
|
|
return true;
|
|
|
|
|
|
2012-05-08 09:45:38 +08:00
|
|
|
llvm::StringRef triple_stref (triple_cstr);
|
|
|
|
|
if (triple_stref.startswith (LLDB_ARCH_DEFAULT))
|
|
|
|
|
{
|
|
|
|
|
// Special case for the current host default architectures...
|
|
|
|
|
if (triple_stref.equals (LLDB_ARCH_DEFAULT_32BIT))
|
|
|
|
|
*this = Host::GetArchitecture (Host::eSystemDefaultArchitecture32);
|
|
|
|
|
else if (triple_stref.equals (LLDB_ARCH_DEFAULT_64BIT))
|
|
|
|
|
*this = Host::GetArchitecture (Host::eSystemDefaultArchitecture64);
|
|
|
|
|
else if (triple_stref.equals (LLDB_ARCH_DEFAULT))
|
|
|
|
|
*this = Host::GetArchitecture (Host::eSystemDefaultArchitecture);
|
|
|
|
|
}
|
|
|
|
|
else
|
|
|
|
|
{
|
|
|
|
|
std::string normalized_triple_sstr (llvm::Triple::normalize(triple_stref));
|
|
|
|
|
triple_stref = normalized_triple_sstr;
|
|
|
|
|
SetTriple (llvm::Triple (triple_stref));
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
else
|
|
|
|
|
Clear();
|
|
|
|
|
return IsValid();
|
|
|
|
|
}
|
|
|
|
|
|
2010-06-09 00:52:24 +08:00
|
|
|
bool
|
2011-04-08 06:46:35 +08:00
|
|
|
ArchSpec::SetTriple (const char *triple_cstr, Platform *platform)
|
2010-06-09 00:52:24 +08:00
|
|
|
{
|
2011-08-13 07:32:52 +08:00
|
|
|
if (triple_cstr && triple_cstr[0])
|
2010-06-09 00:52:24 +08:00
|
|
|
{
|
2012-09-20 06:25:17 +08:00
|
|
|
if (ParseMachCPUDashSubtypeTriple (triple_cstr, *this))
|
|
|
|
|
return true;
|
|
|
|
|
|
2011-02-23 08:35:02 +08:00
|
|
|
llvm::StringRef triple_stref (triple_cstr);
|
|
|
|
|
if (triple_stref.startswith (LLDB_ARCH_DEFAULT))
|
2011-02-16 05:59:32 +08:00
|
|
|
{
|
|
|
|
|
// Special case for the current host default architectures...
|
2011-02-23 08:35:02 +08:00
|
|
|
if (triple_stref.equals (LLDB_ARCH_DEFAULT_32BIT))
|
2011-02-16 05:59:32 +08:00
|
|
|
*this = Host::GetArchitecture (Host::eSystemDefaultArchitecture32);
|
2011-02-23 08:35:02 +08:00
|
|
|
else if (triple_stref.equals (LLDB_ARCH_DEFAULT_64BIT))
|
2011-02-16 05:59:32 +08:00
|
|
|
*this = Host::GetArchitecture (Host::eSystemDefaultArchitecture64);
|
2011-02-23 08:35:02 +08:00
|
|
|
else if (triple_stref.equals (LLDB_ARCH_DEFAULT))
|
2011-02-16 05:59:32 +08:00
|
|
|
*this = Host::GetArchitecture (Host::eSystemDefaultArchitecture);
|
|
|
|
|
}
|
2011-02-23 08:35:02 +08:00
|
|
|
else
|
2010-06-09 00:52:24 +08:00
|
|
|
{
|
2012-05-08 09:45:38 +08:00
|
|
|
ArchSpec raw_arch (triple_cstr);
|
|
|
|
|
|
2011-02-23 08:35:02 +08:00
|
|
|
std::string normalized_triple_sstr (llvm::Triple::normalize(triple_stref));
|
|
|
|
|
triple_stref = normalized_triple_sstr;
|
2011-04-08 06:46:35 +08:00
|
|
|
llvm::Triple normalized_triple (triple_stref);
|
|
|
|
|
|
|
|
|
|
const bool os_specified = normalized_triple.getOSName().size() > 0;
|
|
|
|
|
const bool vendor_specified = normalized_triple.getVendorName().size() > 0;
|
|
|
|
|
const bool env_specified = normalized_triple.getEnvironmentName().size() > 0;
|
|
|
|
|
|
|
|
|
|
// If we got an arch only, then default the vendor, os, environment
|
|
|
|
|
// to match the platform if one is supplied
|
|
|
|
|
if (!(os_specified || vendor_specified || env_specified))
|
|
|
|
|
{
|
|
|
|
|
if (platform)
|
|
|
|
|
{
|
|
|
|
|
// If we were given a platform, use the platform's system
|
|
|
|
|
// architecture. If this is not available (might not be
|
|
|
|
|
// connected) use the first supported architecture.
|
2012-05-08 09:45:38 +08:00
|
|
|
ArchSpec compatible_arch;
|
2013-01-12 04:49:54 +08:00
|
|
|
if (platform->IsCompatibleArchitecture (raw_arch, false, &compatible_arch))
|
2011-04-08 06:46:35 +08:00
|
|
|
{
|
2012-05-08 09:45:38 +08:00
|
|
|
if (compatible_arch.IsValid())
|
|
|
|
|
{
|
|
|
|
|
const llvm::Triple &compatible_triple = compatible_arch.GetTriple();
|
|
|
|
|
if (!vendor_specified)
|
|
|
|
|
normalized_triple.setVendor(compatible_triple.getVendor());
|
|
|
|
|
if (!os_specified)
|
|
|
|
|
normalized_triple.setOS(compatible_triple.getOS());
|
|
|
|
|
if (!env_specified && compatible_triple.getEnvironmentName().size())
|
|
|
|
|
normalized_triple.setEnvironment(compatible_triple.getEnvironment());
|
|
|
|
|
}
|
2011-04-08 06:46:35 +08:00
|
|
|
}
|
2012-05-08 09:45:38 +08:00
|
|
|
else
|
2011-04-08 06:46:35 +08:00
|
|
|
{
|
2012-05-08 09:45:38 +08:00
|
|
|
*this = raw_arch;
|
|
|
|
|
return IsValid();
|
2011-04-08 06:46:35 +08:00
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
else
|
|
|
|
|
{
|
|
|
|
|
// No platform specified, fall back to the host system for
|
|
|
|
|
// the default vendor, os, and environment.
|
2011-11-05 06:46:46 +08:00
|
|
|
llvm::Triple host_triple(llvm::sys::getDefaultTargetTriple());
|
2012-05-08 09:45:38 +08:00
|
|
|
if (!vendor_specified)
|
|
|
|
|
normalized_triple.setVendor(host_triple.getVendor());
|
|
|
|
|
if (!vendor_specified)
|
|
|
|
|
normalized_triple.setOS(host_triple.getOS());
|
|
|
|
|
if (!env_specified && host_triple.getEnvironmentName().size())
|
|
|
|
|
normalized_triple.setEnvironment(host_triple.getEnvironment());
|
2011-04-08 06:46:35 +08:00
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
SetTriple (normalized_triple);
|
2010-06-09 00:52:24 +08:00
|
|
|
}
|
2011-02-23 08:35:02 +08:00
|
|
|
}
|
|
|
|
|
else
|
|
|
|
|
Clear();
|
|
|
|
|
return IsValid();
|
|
|
|
|
}
|
2010-06-09 00:52:24 +08:00
|
|
|
|
2011-02-23 08:35:02 +08:00
|
|
|
bool
|
2011-03-25 05:19:54 +08:00
|
|
|
ArchSpec::SetArchitecture (ArchitectureType arch_type, uint32_t cpu, uint32_t sub)
|
2011-02-23 08:35:02 +08:00
|
|
|
{
|
|
|
|
|
m_core = kCore_invalid;
|
|
|
|
|
bool update_triple = true;
|
|
|
|
|
const ArchDefinition *arch_def = FindArchDefinition(arch_type);
|
|
|
|
|
if (arch_def)
|
|
|
|
|
{
|
|
|
|
|
const ArchDefinitionEntry *arch_def_entry = FindArchDefinitionEntry (arch_def, cpu, sub);
|
|
|
|
|
if (arch_def_entry)
|
2010-06-09 00:52:24 +08:00
|
|
|
{
|
2011-02-23 08:35:02 +08:00
|
|
|
const CoreDefinition *core_def = FindCoreDefinition (arch_def_entry->core);
|
|
|
|
|
if (core_def)
|
2010-06-09 00:52:24 +08:00
|
|
|
{
|
2011-02-23 08:35:02 +08:00
|
|
|
m_core = core_def->core;
|
|
|
|
|
update_triple = false;
|
2011-09-21 11:57:31 +08:00
|
|
|
// Always use the architecture name because it might be more descriptive
|
|
|
|
|
// than the architecture enum ("armv7" -> llvm::Triple::arm).
|
|
|
|
|
m_triple.setArchName(llvm::StringRef(core_def->name));
|
2011-02-23 08:35:02 +08:00
|
|
|
if (arch_type == eArchTypeMachO)
|
2010-06-09 00:52:24 +08:00
|
|
|
{
|
2011-02-23 08:35:02 +08:00
|
|
|
m_triple.setVendor (llvm::Triple::Apple);
|
2012-05-08 09:45:38 +08:00
|
|
|
|
|
|
|
|
switch (core_def->machine)
|
|
|
|
|
{
|
|
|
|
|
case llvm::Triple::arm:
|
|
|
|
|
case llvm::Triple::thumb:
|
|
|
|
|
m_triple.setOS (llvm::Triple::IOS);
|
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
case llvm::Triple::x86:
|
|
|
|
|
case llvm::Triple::x86_64:
|
|
|
|
|
default:
|
|
|
|
|
m_triple.setOS (llvm::Triple::MacOSX);
|
|
|
|
|
break;
|
|
|
|
|
}
|
2010-06-09 00:52:24 +08:00
|
|
|
}
|
2011-02-23 08:35:02 +08:00
|
|
|
else
|
2010-06-09 00:52:24 +08:00
|
|
|
{
|
2011-02-23 08:35:02 +08:00
|
|
|
m_triple.setVendor (llvm::Triple::UnknownVendor);
|
|
|
|
|
m_triple.setOS (llvm::Triple::UnknownOS);
|
2010-06-09 00:52:24 +08:00
|
|
|
}
|
2011-09-21 11:57:31 +08:00
|
|
|
// Fall back onto setting the machine type if the arch by name failed...
|
|
|
|
|
if (m_triple.getArch () == llvm::Triple::UnknownArch)
|
|
|
|
|
m_triple.setArch (core_def->machine);
|
2010-06-11 11:25:34 +08:00
|
|
|
}
|
2010-06-09 00:52:24 +08:00
|
|
|
}
|
|
|
|
|
}
|
2011-02-23 08:35:02 +08:00
|
|
|
CoreUpdated(update_triple);
|
|
|
|
|
return IsValid();
|
2010-06-09 00:52:24 +08:00
|
|
|
}
|
|
|
|
|
|
Added the ability to get the min and max instruction byte size for
an architecture into ArchSpec:
uint32_t
ArchSpec::GetMinimumOpcodeByteSize() const;
uint32_t
ArchSpec::GetMaximumOpcodeByteSize() const;
Added an AddressClass to the Instruction class in Disassembler.h.
This allows decoded instructions to know know if they are code,
code with alternate ISA (thumb), or even data which can be mixed
into code. The instruction does have an address, but it is a good
idea to cache this value so we don't have to look it up more than
once.
Fixed an issue in Opcode::SetOpcodeBytes() where the length wasn't
getting set.
Changed:
bool
SymbolContextList::AppendIfUnique (const SymbolContext& sc);
To:
bool
SymbolContextList::AppendIfUnique (const SymbolContext& sc,
bool merge_symbol_into_function);
This function was typically being used when looking up functions
and symbols. Now if you lookup a function, then find the symbol,
they can be merged into the same symbol context and not cause
multiple symbol contexts to appear in a symbol context list that
describes the same function.
Fixed the SymbolContext not equal operator which was causing mixed
mode disassembly to not work ("disassembler --mixed --name main").
Modified the disassembler classes to know about the fact we know,
for a given architecture, what the min and max opcode byte sizes
are. The InstructionList class was modified to return the max
opcode byte size for all of the instructions in its list.
These two fixes means when disassemble a list of instructions and dump
them and show the opcode bytes, we can format the output more
intelligently when showing opcode bytes. This affects any architectures
that have varying opcode byte sizes (x86_64 and i386). Knowing the max
opcode byte size also helps us to be able to disassemble N instructions
without having to re-read data if we didn't read enough bytes.
Added the ability to set the architecture for the disassemble command.
This means you can easily cross disassemble data for any supported
architecture. I also added the ability to specify "thumb" as an
architecture so that we can force disassembly into thumb mode when
needed. In GDB this was done using a hack of specifying an odd
address when disassembling. I don't want to repeat this hack in LLDB,
so the auto detection between ARM and thumb is failing, just specify
thumb when disassembling:
(lldb) disassemble --arch thumb --name main
You can also have data in say an x86_64 file executable and disassemble
data as any other supported architecture:
% lldb a.out
Current executable set to 'a.out' (x86_64).
(lldb) b main
(lldb) run
(lldb) disassemble --arch thumb --count 2 --start-address 0x0000000100001080 --bytes
0x100001080: 0xb580 push {r7, lr}
0x100001082: 0xaf00 add r7, sp, #0
Fixed Target::ReadMemory(...) to be able to deal with Address argument object
that isn't section offset. When an address object was supplied that was
out on the heap or stack, target read memory would fail. Disassembly uses
Target::ReadMemory(...), and the example above where we disassembler thumb
opcodes in an x86 binary was failing do to this bug.
llvm-svn: 128347
2011-03-27 03:14:58 +08:00
|
|
|
uint32_t
|
|
|
|
|
ArchSpec::GetMinimumOpcodeByteSize() const
|
|
|
|
|
{
|
|
|
|
|
const CoreDefinition *core_def = FindCoreDefinition (m_core);
|
|
|
|
|
if (core_def)
|
|
|
|
|
return core_def->min_opcode_byte_size;
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
uint32_t
|
|
|
|
|
ArchSpec::GetMaximumOpcodeByteSize() const
|
2010-06-09 00:52:24 +08:00
|
|
|
{
|
Added the ability to get the min and max instruction byte size for
an architecture into ArchSpec:
uint32_t
ArchSpec::GetMinimumOpcodeByteSize() const;
uint32_t
ArchSpec::GetMaximumOpcodeByteSize() const;
Added an AddressClass to the Instruction class in Disassembler.h.
This allows decoded instructions to know know if they are code,
code with alternate ISA (thumb), or even data which can be mixed
into code. The instruction does have an address, but it is a good
idea to cache this value so we don't have to look it up more than
once.
Fixed an issue in Opcode::SetOpcodeBytes() where the length wasn't
getting set.
Changed:
bool
SymbolContextList::AppendIfUnique (const SymbolContext& sc);
To:
bool
SymbolContextList::AppendIfUnique (const SymbolContext& sc,
bool merge_symbol_into_function);
This function was typically being used when looking up functions
and symbols. Now if you lookup a function, then find the symbol,
they can be merged into the same symbol context and not cause
multiple symbol contexts to appear in a symbol context list that
describes the same function.
Fixed the SymbolContext not equal operator which was causing mixed
mode disassembly to not work ("disassembler --mixed --name main").
Modified the disassembler classes to know about the fact we know,
for a given architecture, what the min and max opcode byte sizes
are. The InstructionList class was modified to return the max
opcode byte size for all of the instructions in its list.
These two fixes means when disassemble a list of instructions and dump
them and show the opcode bytes, we can format the output more
intelligently when showing opcode bytes. This affects any architectures
that have varying opcode byte sizes (x86_64 and i386). Knowing the max
opcode byte size also helps us to be able to disassemble N instructions
without having to re-read data if we didn't read enough bytes.
Added the ability to set the architecture for the disassemble command.
This means you can easily cross disassemble data for any supported
architecture. I also added the ability to specify "thumb" as an
architecture so that we can force disassembly into thumb mode when
needed. In GDB this was done using a hack of specifying an odd
address when disassembling. I don't want to repeat this hack in LLDB,
so the auto detection between ARM and thumb is failing, just specify
thumb when disassembling:
(lldb) disassemble --arch thumb --name main
You can also have data in say an x86_64 file executable and disassemble
data as any other supported architecture:
% lldb a.out
Current executable set to 'a.out' (x86_64).
(lldb) b main
(lldb) run
(lldb) disassemble --arch thumb --count 2 --start-address 0x0000000100001080 --bytes
0x100001080: 0xb580 push {r7, lr}
0x100001082: 0xaf00 add r7, sp, #0
Fixed Target::ReadMemory(...) to be able to deal with Address argument object
that isn't section offset. When an address object was supplied that was
out on the heap or stack, target read memory would fail. Disassembly uses
Target::ReadMemory(...), and the example above where we disassembler thumb
opcodes in an x86 binary was failing do to this bug.
llvm-svn: 128347
2011-03-27 03:14:58 +08:00
|
|
|
const CoreDefinition *core_def = FindCoreDefinition (m_core);
|
|
|
|
|
if (core_def)
|
|
|
|
|
return core_def->max_opcode_byte_size;
|
|
|
|
|
return 0;
|
2011-02-23 08:35:02 +08:00
|
|
|
}
|
|
|
|
|
|
2012-11-04 11:20:05 +08:00
|
|
|
bool
|
|
|
|
|
ArchSpec::IsExactMatch (const ArchSpec& rhs) const
|
|
|
|
|
{
|
2012-12-14 06:07:14 +08:00
|
|
|
return IsEqualTo (rhs, true);
|
2012-11-04 11:20:05 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
bool
|
|
|
|
|
ArchSpec::IsCompatibleMatch (const ArchSpec& rhs) const
|
|
|
|
|
{
|
2012-12-14 06:07:14 +08:00
|
|
|
return IsEqualTo (rhs, false);
|
2012-11-04 11:20:05 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
bool
|
2012-12-14 06:07:14 +08:00
|
|
|
ArchSpec::IsEqualTo (const ArchSpec& rhs, bool exact_match) const
|
2012-11-04 11:20:05 +08:00
|
|
|
{
|
2014-01-18 11:02:39 +08:00
|
|
|
// explicitly ignoring m_distribution_id in this method.
|
|
|
|
|
|
2012-11-04 11:20:05 +08:00
|
|
|
if (GetByteOrder() != rhs.GetByteOrder())
|
|
|
|
|
return false;
|
|
|
|
|
|
|
|
|
|
const ArchSpec::Core lhs_core = GetCore ();
|
|
|
|
|
const ArchSpec::Core rhs_core = rhs.GetCore ();
|
|
|
|
|
|
|
|
|
|
const bool core_match = cores_match (lhs_core, rhs_core, true, exact_match);
|
|
|
|
|
|
|
|
|
|
if (core_match)
|
|
|
|
|
{
|
|
|
|
|
const llvm::Triple &lhs_triple = GetTriple();
|
|
|
|
|
const llvm::Triple &rhs_triple = rhs.GetTriple();
|
|
|
|
|
|
|
|
|
|
const llvm::Triple::VendorType lhs_triple_vendor = lhs_triple.getVendor();
|
|
|
|
|
const llvm::Triple::VendorType rhs_triple_vendor = rhs_triple.getVendor();
|
|
|
|
|
if (lhs_triple_vendor != rhs_triple_vendor)
|
|
|
|
|
{
|
2012-12-14 06:07:14 +08:00
|
|
|
if (exact_match)
|
|
|
|
|
{
|
|
|
|
|
const bool rhs_vendor_specified = rhs.TripleVendorWasSpecified();
|
|
|
|
|
const bool lhs_vendor_specified = TripleVendorWasSpecified();
|
|
|
|
|
// Both architectures had the vendor specified, so if they aren't
|
|
|
|
|
// equal then we return false
|
|
|
|
|
if (rhs_vendor_specified && lhs_vendor_specified)
|
|
|
|
|
return false;
|
|
|
|
|
}
|
2012-11-04 11:20:05 +08:00
|
|
|
|
|
|
|
|
// Only fail if both vendor types are not unknown
|
|
|
|
|
if (lhs_triple_vendor != llvm::Triple::UnknownVendor &&
|
|
|
|
|
rhs_triple_vendor != llvm::Triple::UnknownVendor)
|
|
|
|
|
return false;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
const llvm::Triple::OSType lhs_triple_os = lhs_triple.getOS();
|
|
|
|
|
const llvm::Triple::OSType rhs_triple_os = rhs_triple.getOS();
|
|
|
|
|
if (lhs_triple_os != rhs_triple_os)
|
|
|
|
|
{
|
2012-12-14 06:07:14 +08:00
|
|
|
if (exact_match)
|
|
|
|
|
{
|
|
|
|
|
const bool rhs_os_specified = rhs.TripleOSWasSpecified();
|
|
|
|
|
const bool lhs_os_specified = TripleOSWasSpecified();
|
|
|
|
|
// Both architectures had the OS specified, so if they aren't
|
|
|
|
|
// equal then we return false
|
|
|
|
|
if (rhs_os_specified && lhs_os_specified)
|
|
|
|
|
return false;
|
|
|
|
|
}
|
2012-11-04 11:20:05 +08:00
|
|
|
// Only fail if both os types are not unknown
|
|
|
|
|
if (lhs_triple_os != llvm::Triple::UnknownOS &&
|
|
|
|
|
rhs_triple_os != llvm::Triple::UnknownOS)
|
|
|
|
|
return false;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
const llvm::Triple::EnvironmentType lhs_triple_env = lhs_triple.getEnvironment();
|
|
|
|
|
const llvm::Triple::EnvironmentType rhs_triple_env = rhs_triple.getEnvironment();
|
|
|
|
|
|
|
|
|
|
if (lhs_triple_env != rhs_triple_env)
|
|
|
|
|
{
|
|
|
|
|
// Only fail if both environment types are not unknown
|
|
|
|
|
if (lhs_triple_env != llvm::Triple::UnknownEnvironment &&
|
|
|
|
|
rhs_triple_env != llvm::Triple::UnknownEnvironment)
|
|
|
|
|
return false;
|
|
|
|
|
}
|
|
|
|
|
return true;
|
|
|
|
|
}
|
|
|
|
|
return false;
|
|
|
|
|
}
|
|
|
|
|
|
2011-02-23 08:35:02 +08:00
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
|
// Helper methods.
|
|
|
|
|
|
|
|
|
|
void
|
|
|
|
|
ArchSpec::CoreUpdated (bool update_triple)
|
|
|
|
|
{
|
|
|
|
|
const CoreDefinition *core_def = FindCoreDefinition (m_core);
|
|
|
|
|
if (core_def)
|
2010-06-09 00:52:24 +08:00
|
|
|
{
|
2011-02-23 08:35:02 +08:00
|
|
|
if (update_triple)
|
|
|
|
|
m_triple = llvm::Triple(core_def->name, "unknown", "unknown");
|
|
|
|
|
m_byte_order = core_def->default_byte_order;
|
|
|
|
|
}
|
|
|
|
|
else
|
|
|
|
|
{
|
|
|
|
|
if (update_triple)
|
|
|
|
|
m_triple = llvm::Triple();
|
|
|
|
|
m_byte_order = eByteOrderInvalid;
|
2010-06-09 00:52:24 +08:00
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
2011-02-23 08:35:02 +08:00
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
|
// Operators.
|
|
|
|
|
|
2012-05-08 09:45:38 +08:00
|
|
|
static bool
|
2012-11-04 11:20:05 +08:00
|
|
|
cores_match (const ArchSpec::Core core1, const ArchSpec::Core core2, bool try_inverse, bool enforce_exact_match)
|
2012-05-08 09:45:38 +08:00
|
|
|
{
|
2012-11-04 11:20:05 +08:00
|
|
|
if (core1 == core2)
|
|
|
|
|
return true;
|
|
|
|
|
|
2012-05-08 09:45:38 +08:00
|
|
|
switch (core1)
|
|
|
|
|
{
|
|
|
|
|
case ArchSpec::kCore_any:
|
|
|
|
|
return true;
|
|
|
|
|
|
|
|
|
|
case ArchSpec::kCore_arm_any:
|
|
|
|
|
if (core2 >= ArchSpec::kCore_arm_first && core2 <= ArchSpec::kCore_arm_last)
|
|
|
|
|
return true;
|
|
|
|
|
if (core2 >= ArchSpec::kCore_thumb_first && core2 <= ArchSpec::kCore_thumb_last)
|
|
|
|
|
return true;
|
|
|
|
|
if (core2 == ArchSpec::kCore_arm_any)
|
|
|
|
|
return true;
|
|
|
|
|
break;
|
2014-01-23 07:42:03 +08:00
|
|
|
|
2012-05-08 09:45:38 +08:00
|
|
|
case ArchSpec::kCore_x86_32_any:
|
|
|
|
|
if ((core2 >= ArchSpec::kCore_x86_32_first && core2 <= ArchSpec::kCore_x86_32_last) || (core2 == ArchSpec::kCore_x86_32_any))
|
|
|
|
|
return true;
|
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
case ArchSpec::kCore_ppc_any:
|
|
|
|
|
if ((core2 >= ArchSpec::kCore_ppc_first && core2 <= ArchSpec::kCore_ppc_last) || (core2 == ArchSpec::kCore_ppc_any))
|
|
|
|
|
return true;
|
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
case ArchSpec::kCore_ppc64_any:
|
|
|
|
|
if ((core2 >= ArchSpec::kCore_ppc64_first && core2 <= ArchSpec::kCore_ppc64_last) || (core2 == ArchSpec::kCore_ppc64_any))
|
|
|
|
|
return true;
|
|
|
|
|
break;
|
|
|
|
|
|
2013-09-28 07:21:54 +08:00
|
|
|
case ArchSpec::eCore_arm_armv6m:
|
|
|
|
|
if (!enforce_exact_match)
|
|
|
|
|
{
|
|
|
|
|
try_inverse = false;
|
2013-09-28 07:29:10 +08:00
|
|
|
if (core2 == ArchSpec::eCore_arm_armv7)
|
2013-09-28 07:21:54 +08:00
|
|
|
return true;
|
|
|
|
|
}
|
2014-02-19 19:16:46 +08:00
|
|
|
|
|
|
|
|
case ArchSpec::kCore_hexagon_any:
|
|
|
|
|
if ((core2 >= ArchSpec::kCore_hexagon_first && core2 <= ArchSpec::kCore_hexagon_last) || (core2 == ArchSpec::kCore_hexagon_any))
|
|
|
|
|
return true;
|
2013-09-28 07:21:54 +08:00
|
|
|
break;
|
|
|
|
|
|
2013-03-08 09:20:17 +08:00
|
|
|
case ArchSpec::eCore_arm_armv7m:
|
|
|
|
|
case ArchSpec::eCore_arm_armv7em:
|
2012-08-29 06:53:40 +08:00
|
|
|
case ArchSpec::eCore_arm_armv7f:
|
|
|
|
|
case ArchSpec::eCore_arm_armv7k:
|
|
|
|
|
case ArchSpec::eCore_arm_armv7s:
|
2012-11-04 11:20:05 +08:00
|
|
|
if (!enforce_exact_match)
|
|
|
|
|
{
|
|
|
|
|
try_inverse = false;
|
|
|
|
|
if (core2 == ArchSpec::eCore_arm_armv7)
|
|
|
|
|
return true;
|
|
|
|
|
}
|
2012-08-29 06:53:40 +08:00
|
|
|
break;
|
|
|
|
|
|
2012-05-08 09:45:38 +08:00
|
|
|
default:
|
|
|
|
|
break;
|
|
|
|
|
}
|
|
|
|
|
if (try_inverse)
|
2012-11-04 11:20:05 +08:00
|
|
|
return cores_match (core2, core1, false, enforce_exact_match);
|
2012-05-08 09:45:38 +08:00
|
|
|
return false;
|
|
|
|
|
}
|
|
|
|
|
|
2010-06-09 00:52:24 +08:00
|
|
|
bool
|
|
|
|
|
lldb_private::operator<(const ArchSpec& lhs, const ArchSpec& rhs)
|
|
|
|
|
{
|
2011-02-23 08:35:02 +08:00
|
|
|
const ArchSpec::Core lhs_core = lhs.GetCore ();
|
|
|
|
|
const ArchSpec::Core rhs_core = rhs.GetCore ();
|
|
|
|
|
return lhs_core < rhs_core;
|
2010-06-09 00:52:24 +08:00
|
|
|
}
|