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llvm-project/llvm/test/MC/Disassembler/X86/prefixes.txt

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Fixed a bug where diassembling an instruction that had a prefix would cause LLVM to identify a 1-byte instruction, but then upon querying it for that 1-byte instruction would cause an undefined opcode. llvm-svn: 189698
2013-08-31 05:19:48 +08:00
# RUN: llvm-mc --disassemble %s -triple=x86_64 | FileCheck %s
This patch is a result of D37262: The issues with X86 prefixes. It closes PR7709, PR17697, PR19251, PR32809 and PR21640. There could be other bugs closed by this patch. llvm-svn: 315899
2017-10-16 19:14:29 +08:00
# CHECK: rep
# CHECK-NEXT: insb %dx, %es:(%rdi)
0xf3 0x6c #rep ins
# CHECK: rep
# CHECK-NEXT: insl %dx, %es:(%rdi)
0xf3 0x6d #rep ins
# CHECK: rep
# CHECK-NEXT: movsb (%rsi), %es:(%rdi)
0xf3 0xa4 #rep movs
# CHECK: rep
# CHECK-NEXT: movsl (%rsi), %es:(%rdi)
0xf3 0xa5 #rep movs
# CHECK: rep
# CHECK-NEXT: outsb (%rsi), %dx
0xf3 0x6e #rep outs
# CHECK: rep
# CHECK-NEXT: outsl (%rsi), %dx
0xf3 0x6f #rep outs
# CHECK: rep
# CHECK-NEXT: lodsb (%rsi), %al
0xf3 0xac #rep lods
# CHECK: rep
# CHECK-NEXT: lodsl (%rsi), %eax
0xf3 0xad #rep lods
# CHECK: rep
# CHECK-NEXT: stosb %al, %es:(%rdi)
0xf3 0xaa #rep stos
# CHECK: rep
# CHECK-NEXT: stosl %eax, %es:(%rdi)
0xf3 0xab #rep stos
# CHECK: rep
# CHECK-NEXT: cmpsb %es:(%rdi), (%rsi)
0xf3 0xa6 #rep cmps
# CHECK: rep
# CHECK-NEXT: cmpsl %es:(%rdi), (%rsi)
0xf3 0xa7 #repe cmps
# CHECK: rep
# CHECK-NEXT: scasb %es:(%rdi), %al
0xf3 0xae #repe scas
# CHECK: rep
# CHECK-NEXT: scasl %es:(%rdi), %eax
0xf3 0xaf #repe scas
# CHECK: repne
# CHECK-NEXT: cmpsb %es:(%rdi), (%rsi)
0xf2 0xa6 #repne cmps
# CHECK: repne
# CHECK-NEXT: cmpsl %es:(%rdi), (%rsi)
0xf2 0xa7 #repne cmps
# CHECK: repne
# CHECK-NEXT: scasb %es:(%rdi), %al
0xf2 0xae #repne scas
# CHECK: repne
# CHECK-NEXT: scasl %es:(%rdi), %eax
0xf2 0xaf #repne scas
Fixed a bug where diassembling an instruction that had a prefix would cause LLVM to identify a 1-byte instruction, but then upon querying it for that 1-byte instruction would cause an undefined opcode. llvm-svn: 189698
2013-08-31 05:19:48 +08:00
# CHECK: lock
# CHECK-NEXT: orl $16, %fs:776
0xf0 0x64 0x83 0x0c 0x25 0x08 0x03 0x00 0x00 0x10
# CHECK: movq %fs:768, %rdi
0x64 0x48 0x8b 0x3c 0x25 0x00 0x03 0x00 0x00
# CHECK: rep
[X86] Disassembler support for move to/from %rax with a 32-bit memory offset is REX.W and AdSize prefix are both present. llvm-svn: 225099
2015-01-03 08:00:20 +08:00
# CHECK-NEXT: stosq %rax, %es:(%rdi)
Fixed a bug where diassembling an instruction that had a prefix would cause LLVM to identify a 1-byte instruction, but then upon querying it for that 1-byte instruction would cause an undefined opcode. llvm-svn: 189698
2013-08-31 05:19:48 +08:00
0xf3 0x48 0xab
# CHECK: rep
[X86] Disassembler support for move to/from %rax with a 32-bit memory offset is REX.W and AdSize prefix are both present. llvm-svn: 225099
2015-01-03 08:00:20 +08:00
# CHECK-NEXT: stosq %rax, %es:(%edi)
Fixed a bug where diassembling an instruction that had a prefix would cause LLVM to identify a 1-byte instruction, but then upon querying it for that 1-byte instruction would cause an undefined opcode. llvm-svn: 189698
2013-08-31 05:19:48 +08:00
0xf3 0x67 0x48 0xab
# CHECK: movl 32(%rbp), %eax
0x8b 0x45 0x20
# CHECK: movl %es:32(%rbp), %eax
0x26 0x8b 0x45 0x20
# CHECK: movl %es:32(%rbp), %eax
0x2e 0x26 0x8b 0x45 0x20
# Test that multiple prefixes stack.
# (todo- the correct disassembly is actually more like "es movl %cs:32(%rbp), %eax"
# but we don't support that)
# CHECK: movl %cs:32(%rbp), %eax
0x26 0x2e 0x8b 0x45 0x20
# Test that 0xf3 as part of the opcode works.
# CHECK: cvtdq2pd (%rax), %xmm0
0xf3 0x0f 0xe6 0x00
# CHECK: pause
0xf3 0x90
# CHECK: nop
0x90
# CHECK: lock
# CHECK-NEXT: nop
0xf0 0x90
X86Disassembler - fixed a bug in immediate print llvm-svn: 206953
2014-04-23 15:21:04 +08:00
# Test that immediate is printed correctly within opsize prefix
# CHECK: addw $-12, %ax
0x66,0x83,0xc0,0xf4
Fixed a bug where diassembling an instruction that had a prefix would cause LLVM to identify a 1-byte instruction, but then upon querying it for that 1-byte instruction would cause an undefined opcode. llvm-svn: 189698
2013-08-31 05:19:48 +08:00
# Test that multiple redundant prefixes work (redundant, but valid x86).
# CHECK: rep
# CHECK-NEXT: stosq
0xf3 0xf3 0x48 0xab
[X86] Don't fail disassembly if REX.R/REX.B is used on an MMX register. Similar fix to not fail to disassembler CR9-CR15 references. llvm-svn: 224861
2014-12-27 02:19:44 +08:00
# Test that we can disassembler control registers above CR8
# CHECK: movq %cr15, %rax
0x44 0x0f 0x20 0xf8
[X86] Add the debug registers DR8-DR15 so we can assemble and disassemble references to them. llvm-svn: 224862
2014-12-27 02:20:05 +08:00
# CHECK: movq %dr15, %rax
0x44 0x0f 0x21 0xf8
[X86] Don't fail disassembly if REX.R/REX.B is used on an MMX register. Similar fix to not fail to disassembler CR9-CR15 references. llvm-svn: 224861
2014-12-27 02:19:44 +08:00
# Test that MMX ignore REX.R and REX.B.
# CHECK: movq %mm0, %mm1
0x46 0x0f 0x7f 0xc1
Fixed a bug where diassembling an instruction that had a prefix would cause LLVM to identify a 1-byte instruction, but then upon querying it for that 1-byte instruction would cause an undefined opcode. llvm-svn: 189698
2013-08-31 05:19:48 +08:00
# Test that a prefix on it's own works. It's debatable as to if this is
# something that is considered valid, but however as LLVM's own disassembler
# has decided to disassemble prefixes as being separate opcodes, it therefore
# should be capable of re-consuming it's own output.
# CHECK: rep
0xf3
# ***IMPORTANT ^-- this must be at the end of the file to be a valid test ***