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llvm-project/llvm/test/MC/AMDGPU/sopk-err.s

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[AMDGPU][llvm-mc] s_getreg/setreg* - Add hwreg(...) syntax. Added hwreg(reg[,offset,width]) syntax. Default offset = 0, default width = 32. Possibility to specify 16-bit immediate kept. Added out-of-range checks. Disassembling is always to hwreg(...) format. Tests updated/added. Differential Revision: http://reviews.llvm.org/D19329 llvm-svn: 267410
2016-04-25 22:13:51 +08:00
// RUN: not llvm-mc -arch=amdgcn %s 2>&1 | FileCheck -check-prefix=GCN %s
// RUN: not llvm-mc -arch=amdgcn -mcpu=tahiti %s 2>&1 | FileCheck -check-prefix=GCN -check-prefix=SI %s
// RUN: not llvm-mc -arch=amdgcn -mcpu=tonga %s 2>&1 | FileCheck -check-prefix=GCN -check-prefix=VI %s
s_setreg_b32 0x1f803, s2
// GCN: error: invalid immediate: only 16-bit values are legal
s_setreg_b32 hwreg(0x40), s2
// GCN: error: invalid code of hardware register: only 6-bit values are legal
s_setreg_b32 hwreg(3,32,32), s2
// GCN: error: invalid bit offset: only 5-bit values are legal
s_setreg_b32 hwreg(3,0,33), s2
// GCN: error: invalid bitfield width: only values from 1 to 32 are legal
s_setreg_imm32_b32 0x1f803, 0xff
// GCN: error: invalid immediate: only 16-bit values are legal
s_setreg_imm32_b32 hwreg(3,0,33), 0xff
// GCN: error: invalid bitfield width: only values from 1 to 32 are legal
s_getreg_b32 s2, hwreg(3,32,32)
// GCN: error: invalid bit offset: only 5-bit values are legal