2013-12-26 07:43:39 +08:00
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//===-- SparcInstPrinter.cpp - Convert Sparc MCInst to assembly syntax -----==//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This class prints an Sparc MCInst to a .s file.
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//
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//===----------------------------------------------------------------------===//
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#include "SparcInstPrinter.h"
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2014-01-07 19:48:04 +08:00
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#include "Sparc.h"
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2013-12-26 07:43:39 +08:00
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#include "llvm/MC/MCExpr.h"
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#include "llvm/MC/MCInst.h"
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TableGen: fix operand counting for aliases
TableGen has a fairly dubious heuristic to decide whether an alias should be
printed: does the alias have lest operands than the real instruction. This is
bad enough (particularly with no way to override it), but it should at least be
calculated consistently for both strings.
This patch implements that logic: first get the *correct* string for the
variant, in the same way as the Matcher, without guessing; then count the
number of whitespace chars.
There are basically 4 changes this brings about after the previous
commits; all of these appear to be good, so I have changed the tests:
+ ARM64: we print "neg X, Y" instead of "sub X, xzr, Y".
+ ARM64: we skip implicit "uxtx" and "uxtw" modifiers.
+ Sparc: we print "mov A, B" instead of "or %g0, A, B".
+ Sparc: we print "fcmpX A, B" instead of "fcmpX %fcc0, A, B"
llvm-svn: 208969
2014-05-16 17:42:04 +08:00
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#include "llvm/MC/MCRegisterInfo.h"
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2013-12-26 07:43:39 +08:00
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#include "llvm/MC/MCSymbol.h"
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#include "llvm/Support/raw_ostream.h"
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using namespace llvm;
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2014-04-22 10:41:26 +08:00
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#define DEBUG_TYPE "asm-printer"
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2014-03-01 09:04:26 +08:00
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// The generated AsmMatcher SparcGenAsmWriter uses "Sparc" as the target
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// namespace. But SPARC backend uses "SP" as its namespace.
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namespace llvm {
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namespace Sparc {
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using namespace SP;
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}
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}
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2013-12-26 07:43:39 +08:00
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#define GET_INSTRUCTION_NAME
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2014-01-10 09:48:17 +08:00
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#define PRINT_ALIAS_INSTR
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2013-12-26 09:49:59 +08:00
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#include "SparcGenAsmWriter.inc"
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2013-12-26 07:43:39 +08:00
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2015-03-28 12:03:51 +08:00
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bool SparcInstPrinter::isV9(const MCSubtargetInfo &STI) const {
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2015-05-13 18:28:46 +08:00
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return (STI.getFeatureBits() & Sparc::FeatureV9) != 0;
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2014-03-02 11:39:39 +08:00
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}
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2013-12-26 07:43:39 +08:00
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void SparcInstPrinter::printRegName(raw_ostream &OS, unsigned RegNo) const
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{
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OS << '%' << StringRef(getRegisterName(RegNo)).lower();
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}
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void SparcInstPrinter::printInst(const MCInst *MI, raw_ostream &O,
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2015-03-28 04:36:02 +08:00
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StringRef Annot, const MCSubtargetInfo &STI) {
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2015-03-28 12:03:51 +08:00
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if (!printAliasInstr(MI, STI, O) && !printSparcAliasInstr(MI, STI, O))
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printInstruction(MI, STI, O);
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2013-12-26 07:43:39 +08:00
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printAnnotation(O, Annot);
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}
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2015-03-28 12:03:51 +08:00
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bool SparcInstPrinter::printSparcAliasInstr(const MCInst *MI,
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const MCSubtargetInfo &STI,
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raw_ostream &O) {
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2014-01-10 09:48:17 +08:00
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switch (MI->getOpcode()) {
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default: return false;
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case SP::JMPLrr:
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case SP::JMPLri: {
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if (MI->getNumOperands() != 3)
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return false;
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if (!MI->getOperand(0).isReg())
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return false;
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switch (MI->getOperand(0).getReg()) {
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default: return false;
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2014-03-03 05:17:44 +08:00
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case SP::G0: // jmp $addr | ret | retl
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if (MI->getOperand(2).isImm() &&
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MI->getOperand(2).getImm() == 8) {
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switch(MI->getOperand(1).getReg()) {
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default: break;
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case SP::I7: O << "\tret"; return true;
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case SP::O7: O << "\tretl"; return true;
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}
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}
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2015-03-28 12:03:51 +08:00
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O << "\tjmp "; printMemOperand(MI, 1, STI, O);
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2014-01-10 09:48:17 +08:00
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return true;
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case SP::O7: // call $addr
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2015-03-28 12:03:51 +08:00
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O << "\tcall "; printMemOperand(MI, 1, STI, O);
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2014-01-10 09:48:17 +08:00
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return true;
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}
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}
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2014-03-03 03:56:19 +08:00
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case SP::V9FCMPS: case SP::V9FCMPD: case SP::V9FCMPQ:
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case SP::V9FCMPES: case SP::V9FCMPED: case SP::V9FCMPEQ: {
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2015-03-28 12:03:51 +08:00
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if (isV9(STI)
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2014-03-02 11:39:39 +08:00
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|| (MI->getNumOperands() != 3)
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|| (!MI->getOperand(0).isReg())
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|| (MI->getOperand(0).getReg() != SP::FCC0))
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return false;
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// if V8, skip printing %fcc0.
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switch(MI->getOpcode()) {
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default:
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2014-03-03 03:56:19 +08:00
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case SP::V9FCMPS: O << "\tfcmps "; break;
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case SP::V9FCMPD: O << "\tfcmpd "; break;
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case SP::V9FCMPQ: O << "\tfcmpq "; break;
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case SP::V9FCMPES: O << "\tfcmpes "; break;
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case SP::V9FCMPED: O << "\tfcmped "; break;
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case SP::V9FCMPEQ: O << "\tfcmpeq "; break;
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2014-03-02 11:39:39 +08:00
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}
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2015-03-28 12:03:51 +08:00
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printOperand(MI, 1, STI, O);
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2014-03-02 11:39:39 +08:00
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O << ", ";
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2015-03-28 12:03:51 +08:00
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printOperand(MI, 2, STI, O);
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2014-03-02 11:39:39 +08:00
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return true;
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}
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2014-01-10 09:48:17 +08:00
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}
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}
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2013-12-26 07:43:39 +08:00
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void SparcInstPrinter::printOperand(const MCInst *MI, int opNum,
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2015-03-28 12:03:51 +08:00
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const MCSubtargetInfo &STI,
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raw_ostream &O) {
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2013-12-26 07:43:39 +08:00
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const MCOperand &MO = MI->getOperand (opNum);
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if (MO.isReg()) {
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printRegName(O, MO.getReg());
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return ;
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}
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if (MO.isImm()) {
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O << (int)MO.getImm();
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return;
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}
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assert(MO.isExpr() && "Unknown operand kind in printOperand");
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MO.getExpr()->print(O);
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}
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void SparcInstPrinter::printMemOperand(const MCInst *MI, int opNum,
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2015-03-28 12:03:51 +08:00
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const MCSubtargetInfo &STI,
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raw_ostream &O, const char *Modifier) {
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printOperand(MI, opNum, STI, O);
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2013-12-26 07:43:39 +08:00
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// If this is an ADD operand, emit it like normal operands.
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if (Modifier && !strcmp(Modifier, "arith")) {
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O << ", ";
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2015-03-28 12:03:51 +08:00
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printOperand(MI, opNum+1, STI, O);
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2013-12-26 07:43:39 +08:00
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return;
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}
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const MCOperand &MO = MI->getOperand(opNum+1);
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if (MO.isReg() && MO.getReg() == SP::G0)
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return; // don't print "+%g0"
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if (MO.isImm() && MO.getImm() == 0)
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return; // don't print "+0"
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O << "+";
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2015-03-28 12:03:51 +08:00
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printOperand(MI, opNum+1, STI, O);
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2013-12-26 07:43:39 +08:00
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}
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void SparcInstPrinter::printCCOperand(const MCInst *MI, int opNum,
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2015-03-28 12:03:51 +08:00
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const MCSubtargetInfo &STI,
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raw_ostream &O) {
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2013-12-26 07:43:39 +08:00
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int CC = (int)MI->getOperand(opNum).getImm();
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2014-01-08 14:14:52 +08:00
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switch (MI->getOpcode()) {
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default: break;
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case SP::FBCOND:
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2014-03-02 04:08:48 +08:00
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case SP::FBCONDA:
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2014-03-02 06:03:07 +08:00
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case SP::BPFCC:
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case SP::BPFCCA:
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case SP::BPFCCNT:
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case SP::BPFCCANT:
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2014-03-02 14:28:15 +08:00
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case SP::MOVFCCrr: case SP::V9MOVFCCrr:
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case SP::MOVFCCri: case SP::V9MOVFCCri:
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case SP::FMOVS_FCC: case SP::V9FMOVS_FCC:
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case SP::FMOVD_FCC: case SP::V9FMOVD_FCC:
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case SP::FMOVQ_FCC: case SP::V9FMOVQ_FCC:
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// Make sure CC is a fp conditional flag.
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2014-01-08 14:14:52 +08:00
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CC = (CC < 16) ? (CC + 16) : CC;
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break;
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}
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2013-12-26 07:43:39 +08:00
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O << SPARCCondCodeToString((SPCC::CondCodes)CC);
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}
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bool SparcInstPrinter::printGetPCX(const MCInst *MI, unsigned opNum,
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2015-03-28 12:03:51 +08:00
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const MCSubtargetInfo &STI,
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raw_ostream &O) {
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2014-06-19 14:10:58 +08:00
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llvm_unreachable("FIXME: Implement SparcInstPrinter::printGetPCX.");
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2013-12-26 07:43:39 +08:00
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return true;
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}
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