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llvm-project/llvm/test/Analysis/CostModel/X86/cast.ll

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Code Model: Improve the accuracy of the zext/sext/trunc vector cost estimation. llvm-svn: 167412
2012-11-06 06:20:53 +08:00
; RUN: opt < %s -cost-model -analyze -mtriple=x86_64-apple-macosx10.8.0 -mcpu=corei7-avx | FileCheck %s
target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128"
target triple = "x86_64-apple-macosx10.8.0"
define i32 @add(i32 %arg) {
; -- Same size registeres --
;CHECK: cost of 1 {{.*}} zext
%A = zext <4 x i1> undef to <4 x i32>
;CHECK: cost of 2 {{.*}} sext
%B = sext <4 x i1> undef to <4 x i32>
;CHECK: cost of 0 {{.*}} trunc
%C = trunc <4 x i32> undef to <4 x i1>
; -- Different size registers --
;CHECK-NOT: cost of 1 {{.*}} zext
%D = zext <8 x i1> undef to <8 x i32>
;CHECK-NOT: cost of 2 {{.*}} sext
%E = sext <8 x i1> undef to <8 x i32>
;CHECK-NOT: cost of 2 {{.*}} trunc
%F = trunc <8 x i32> undef to <8 x i1>
; -- scalars --
;CHECK: cost of 1 {{.*}} zext
%G = zext i1 undef to i32
;CHECK: cost of 0 {{.*}} trunc
%H = trunc i32 undef to i1
Cost Model: change the default cost of control flow instructions (br / ret / ...) to zero. llvm-svn: 169423
2012-12-06 05:21:26 +08:00
;CHECK: cost of 0 {{.*}} ret
Code Model: Improve the accuracy of the zext/sext/trunc vector cost estimation. llvm-svn: 167412
2012-11-06 06:20:53 +08:00
ret i32 undef
}
Cost Model: add tables for some avx type-conversion hacks. llvm-svn: 167480
2012-11-07 03:33:53 +08:00
define i32 @zext_sext(<8 x i1> %in) {
;CHECK: cost of 6 {{.*}} zext
%Z = zext <8 x i1> %in to <8 x i32>
;CHECK: cost of 9 {{.*}} sext
%S = sext <8 x i1> %in to <8 x i32>
;CHECK: cost of 1 {{.*}} sext
%A = sext <8 x i16> undef to <8 x i32>
;CHECK: cost of 1 {{.*}} zext
%B = zext <8 x i16> undef to <8 x i32>
;CHECK: cost of 1 {{.*}} sext
%C = sext <4 x i32> undef to <4 x i64>
Optimize sext <4 x i8> and <4 x i16> to <4 x i64>. Patch by Ahmad, Muhammad T <muhammad.t.ahmad@intel.com> llvm-svn: 177421
2013-03-20 02:38:27 +08:00
;CHECK: cost of 6 {{.*}} sext
I optimized the following patterns: sext <4 x i1> to <4 x i64> sext <4 x i8> to <4 x i64> sext <4 x i16> to <4 x i64> I'm running Combine on SIGN_EXTEND_IN_REG and revert SEXT patterns: (sext_in_reg (v4i64 anyext (v4i32 x )), ExtraVT) -> (v4i64 sext (v4i32 sext_in_reg (v4i32 x , ExtraVT))) The sext_in_reg (v4i32 x) may be lowered to shl+sar operations. The "sar" does not exist on 64-bit operation, so lowering sext_in_reg (v4i64 x) has no vector solution. I also added a cost of this operations to the AVX costs table. llvm-svn: 175619
2013-02-20 20:42:54 +08:00
%C1 = sext <4 x i8> undef to <4 x i64>
Optimize sext <4 x i8> and <4 x i16> to <4 x i64>. Patch by Ahmad, Muhammad T <muhammad.t.ahmad@intel.com> llvm-svn: 177421
2013-03-20 02:38:27 +08:00
;CHECK: cost of 6 {{.*}} sext
I optimized the following patterns: sext <4 x i1> to <4 x i64> sext <4 x i8> to <4 x i64> sext <4 x i16> to <4 x i64> I'm running Combine on SIGN_EXTEND_IN_REG and revert SEXT patterns: (sext_in_reg (v4i64 anyext (v4i32 x )), ExtraVT) -> (v4i64 sext (v4i32 sext_in_reg (v4i32 x , ExtraVT))) The sext_in_reg (v4i32 x) may be lowered to shl+sar operations. The "sar" does not exist on 64-bit operation, so lowering sext_in_reg (v4i64 x) has no vector solution. I also added a cost of this operations to the AVX costs table. llvm-svn: 175619
2013-02-20 20:42:54 +08:00
%C2 = sext <4 x i16> undef to <4 x i64>
Cost Model: add tables for some avx type-conversion hacks. llvm-svn: 167480
2012-11-07 03:33:53 +08:00
;CHECK: cost of 1 {{.*}} zext
%D = zext <4 x i32> undef to <4 x i64>
;CHECK: cost of 1 {{.*}} trunc
%E = trunc <4 x i64> undef to <4 x i32>
;CHECK: cost of 1 {{.*}} trunc
%F = trunc <8 x i32> undef to <8 x i16>
CostModel: add another known vector trunc optimization. llvm-svn: 167488
2012-11-07 05:17:17 +08:00
;CHECK: cost of 3 {{.*}} trunc
%G = trunc <8 x i64> undef to <8 x i32>
Cost Model: add tables for some avx type-conversion hacks. llvm-svn: 167480
2012-11-07 03:33:53 +08:00
ret i32 undef
}
I optimized the following patterns: sext <4 x i1> to <4 x i64> sext <4 x i8> to <4 x i64> sext <4 x i16> to <4 x i64> I'm running Combine on SIGN_EXTEND_IN_REG and revert SEXT patterns: (sext_in_reg (v4i64 anyext (v4i32 x )), ExtraVT) -> (v4i64 sext (v4i32 sext_in_reg (v4i32 x , ExtraVT))) The sext_in_reg (v4i32 x) may be lowered to shl+sar operations. The "sar" does not exist on 64-bit operation, so lowering sext_in_reg (v4i64 x) has no vector solution. I also added a cost of this operations to the AVX costs table. llvm-svn: 175619
2013-02-20 20:42:54 +08:00
define i32 @masks8(<8 x i1> %in) {
Cost Model: add tables for some avx type-conversion hacks. llvm-svn: 167480
2012-11-07 03:33:53 +08:00
;CHECK: cost of 6 {{.*}} zext
%Z = zext <8 x i1> %in to <8 x i32>
;CHECK: cost of 9 {{.*}} sext
%S = sext <8 x i1> %in to <8 x i32>
ret i32 undef
}
I optimized the following patterns: sext <4 x i1> to <4 x i64> sext <4 x i8> to <4 x i64> sext <4 x i16> to <4 x i64> I'm running Combine on SIGN_EXTEND_IN_REG and revert SEXT patterns: (sext_in_reg (v4i64 anyext (v4i32 x )), ExtraVT) -> (v4i64 sext (v4i32 sext_in_reg (v4i32 x , ExtraVT))) The sext_in_reg (v4i32 x) may be lowered to shl+sar operations. The "sar" does not exist on 64-bit operation, so lowering sext_in_reg (v4i64 x) has no vector solution. I also added a cost of this operations to the AVX costs table. llvm-svn: 175619
2013-02-20 20:42:54 +08:00
define i32 @masks4(<4 x i1> %in) {
;CHECK: cost of 8 {{.*}} sext
%S = sext <4 x i1> %in to <4 x i64>
ret i32 undef
}