forked from OSchip/llvm-project
180 lines
6.2 KiB
LLVM
180 lines
6.2 KiB
LLVM
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=x86_64-unknown -print-schedule -mcpu=x86-64 -mattr=+lwp | FileCheck %s --check-prefix=GENERIC
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; RUN: llc < %s -mtriple=x86_64-unknown -print-schedule -mcpu=bdver1 | FileCheck %s --check-prefix=BDVER --check-prefix=BDVER1
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; RUN: llc < %s -mtriple=x86_64-unknown -print-schedule -mcpu=bdver2 | FileCheck %s --check-prefix=BDVER --check-prefix=BDVER2
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; RUN: llc < %s -mtriple=x86_64-unknown -print-schedule -mcpu=bdver3 | FileCheck %s --check-prefix=BDVER --check-prefix=BDVER3
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; RUN: llc < %s -mtriple=x86_64-unknown -print-schedule -mcpu=bdver4 | FileCheck %s --check-prefix=BDVER --check-prefix=BDVER4
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define void @test_llwpcb(i8 *%a0) nounwind {
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; GENERIC-LABEL: test_llwpcb:
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; GENERIC: # %bb.0:
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; GENERIC-NEXT: llwpcb %rdi # sched: [100:0.33]
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; GENERIC-NEXT: retq # sched: [1:1.00]
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;
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; BDVER-LABEL: test_llwpcb:
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; BDVER: # %bb.0:
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; BDVER-NEXT: llwpcb %rdi
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; BDVER-NEXT: retq
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tail call void @llvm.x86.llwpcb(i8 *%a0)
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ret void
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}
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define i8* @test_slwpcb(i8 *%a0) nounwind {
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; GENERIC-LABEL: test_slwpcb:
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; GENERIC: # %bb.0:
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; GENERIC-NEXT: slwpcb %rax # sched: [100:0.33]
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; GENERIC-NEXT: retq # sched: [1:1.00]
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;
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; BDVER-LABEL: test_slwpcb:
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; BDVER: # %bb.0:
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; BDVER-NEXT: slwpcb %rax
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; BDVER-NEXT: retq
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%1 = tail call i8* @llvm.x86.slwpcb()
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ret i8 *%1
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}
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define i8 @test_lwpins32_rri(i32 %a0, i32 %a1) nounwind {
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; GENERIC-LABEL: test_lwpins32_rri:
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; GENERIC: # %bb.0:
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; GENERIC-NEXT: addl %esi, %esi # sched: [1:0.33]
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; GENERIC-NEXT: lwpins $-1985229329, %esi, %edi # imm = 0x89ABCDEF
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; GENERIC-NEXT: # sched: [100:0.33]
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; GENERIC-NEXT: setb %al # sched: [1:0.50]
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; GENERIC-NEXT: retq # sched: [1:1.00]
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;
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; BDVER-LABEL: test_lwpins32_rri:
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; BDVER: # %bb.0:
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; BDVER-NEXT: addl %esi, %esi
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; BDVER-NEXT: lwpins $-1985229329, %esi, %edi # imm = 0x89ABCDEF
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; BDVER-NEXT: setb %al
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; BDVER-NEXT: retq
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%1 = add i32 %a1, %a1
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%2 = tail call i8 @llvm.x86.lwpins32(i32 %a0, i32 %1, i32 2309737967)
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ret i8 %2
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}
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define i8 @test_lwpins32_rmi(i32 %a0, i32 *%p1) nounwind {
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; GENERIC-LABEL: test_lwpins32_rmi:
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; GENERIC: # %bb.0:
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; GENERIC-NEXT: lwpins $1985229328, (%rsi), %edi # imm = 0x76543210
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; GENERIC-NEXT: # sched: [100:0.33]
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; GENERIC-NEXT: setb %al # sched: [1:0.50]
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; GENERIC-NEXT: retq # sched: [1:1.00]
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;
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; BDVER-LABEL: test_lwpins32_rmi:
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; BDVER: # %bb.0:
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; BDVER-NEXT: lwpins $1985229328, (%rsi), %edi # imm = 0x76543210
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; BDVER-NEXT: setb %al
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; BDVER-NEXT: retq
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%a1 = load i32, i32 *%p1
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%1 = tail call i8 @llvm.x86.lwpins32(i32 %a0, i32 %a1, i32 1985229328)
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ret i8 %1
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}
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define i8 @test_lwpins64_rri(i64 %a0, i32 %a1) nounwind {
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; GENERIC-LABEL: test_lwpins64_rri:
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; GENERIC: # %bb.0:
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; GENERIC-NEXT: lwpins $-1985229329, %esi, %rdi # imm = 0x89ABCDEF
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; GENERIC-NEXT: # sched: [100:0.33]
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; GENERIC-NEXT: setb %al # sched: [1:0.50]
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; GENERIC-NEXT: retq # sched: [1:1.00]
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;
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; BDVER-LABEL: test_lwpins64_rri:
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; BDVER: # %bb.0:
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; BDVER-NEXT: lwpins $-1985229329, %esi, %rdi # imm = 0x89ABCDEF
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; BDVER-NEXT: setb %al
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; BDVER-NEXT: retq
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%1 = tail call i8 @llvm.x86.lwpins64(i64 %a0, i32 %a1, i32 2309737967)
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ret i8 %1
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}
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define i8 @test_lwpins64_rmi(i64 %a0, i32 *%p1) nounwind {
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; GENERIC-LABEL: test_lwpins64_rmi:
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; GENERIC: # %bb.0:
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; GENERIC-NEXT: lwpins $1985229328, (%rsi), %rdi # imm = 0x76543210
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; GENERIC-NEXT: # sched: [100:0.33]
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; GENERIC-NEXT: setb %al # sched: [1:0.50]
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; GENERIC-NEXT: retq # sched: [1:1.00]
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;
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; BDVER-LABEL: test_lwpins64_rmi:
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; BDVER: # %bb.0:
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; BDVER-NEXT: lwpins $1985229328, (%rsi), %rdi # imm = 0x76543210
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; BDVER-NEXT: setb %al
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; BDVER-NEXT: retq
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%a1 = load i32, i32 *%p1
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%1 = tail call i8 @llvm.x86.lwpins64(i64 %a0, i32 %a1, i32 1985229328)
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ret i8 %1
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}
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define void @test_lwpval32_rri(i32 %a0, i32 %a1) nounwind {
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; GENERIC-LABEL: test_lwpval32_rri:
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; GENERIC: # %bb.0:
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; GENERIC-NEXT: addl %esi, %esi # sched: [1:0.33]
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; GENERIC-NEXT: lwpval $-19088744, %esi, %edi # imm = 0xFEDCBA98
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; GENERIC-NEXT: # sched: [100:0.33]
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; GENERIC-NEXT: retq # sched: [1:1.00]
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;
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; BDVER-LABEL: test_lwpval32_rri:
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; BDVER: # %bb.0:
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; BDVER-NEXT: addl %esi, %esi
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; BDVER-NEXT: lwpval $-19088744, %esi, %edi # imm = 0xFEDCBA98
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; BDVER-NEXT: retq
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%1 = add i32 %a1, %a1
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tail call void @llvm.x86.lwpval32(i32 %a0, i32 %1, i32 4275878552)
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ret void
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}
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define void @test_lwpval32_rmi(i32 %a0, i32 *%p1) nounwind {
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; GENERIC-LABEL: test_lwpval32_rmi:
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; GENERIC: # %bb.0:
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; GENERIC-NEXT: lwpval $305419896, (%rsi), %edi # imm = 0x12345678
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; GENERIC-NEXT: # sched: [100:0.33]
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; GENERIC-NEXT: retq # sched: [1:1.00]
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;
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; BDVER-LABEL: test_lwpval32_rmi:
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; BDVER: # %bb.0:
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; BDVER-NEXT: lwpval $305419896, (%rsi), %edi # imm = 0x12345678
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; BDVER-NEXT: retq
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%a1 = load i32, i32 *%p1
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tail call void @llvm.x86.lwpval32(i32 %a0, i32 %a1, i32 305419896)
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ret void
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}
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define void @test_lwpval64_rri(i64 %a0, i32 %a1) nounwind {
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; GENERIC-LABEL: test_lwpval64_rri:
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; GENERIC: # %bb.0:
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; GENERIC-NEXT: lwpval $-19088744, %esi, %rdi # imm = 0xFEDCBA98
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; GENERIC-NEXT: # sched: [100:0.33]
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; GENERIC-NEXT: retq # sched: [1:1.00]
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;
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; BDVER-LABEL: test_lwpval64_rri:
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; BDVER: # %bb.0:
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; BDVER-NEXT: lwpval $-19088744, %esi, %rdi # imm = 0xFEDCBA98
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; BDVER-NEXT: retq
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tail call void @llvm.x86.lwpval64(i64 %a0, i32 %a1, i32 4275878552)
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ret void
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}
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define void @test_lwpval64_rmi(i64 %a0, i32 *%p1) nounwind {
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; GENERIC-LABEL: test_lwpval64_rmi:
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; GENERIC: # %bb.0:
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; GENERIC-NEXT: lwpval $305419896, (%rsi), %rdi # imm = 0x12345678
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; GENERIC-NEXT: # sched: [100:0.33]
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; GENERIC-NEXT: retq # sched: [1:1.00]
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;
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; BDVER-LABEL: test_lwpval64_rmi:
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; BDVER: # %bb.0:
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; BDVER-NEXT: lwpval $305419896, (%rsi), %rdi # imm = 0x12345678
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; BDVER-NEXT: retq
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%a1 = load i32, i32 *%p1
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tail call void @llvm.x86.lwpval64(i64 %a0, i32 %a1, i32 305419896)
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ret void
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}
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declare void @llvm.x86.llwpcb(i8*) nounwind
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declare i8* @llvm.x86.slwpcb() nounwind
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declare i8 @llvm.x86.lwpins32(i32, i32, i32) nounwind
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declare i8 @llvm.x86.lwpins64(i64, i32, i32) nounwind
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declare void @llvm.x86.lwpval32(i32, i32, i32) nounwind
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declare void @llvm.x86.lwpval64(i64, i32, i32) nounwind
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