maxjhandsome
/
llvm-project
forked from OSchip/llvm-project
1
0
Fork 0
Code Issues Pull Requests Packages Releases Wiki Activity
llvm-project/llvm/test/MC/ARM/diagnostics.s

708 lines
29 KiB
ArmAsm
Raw Normal View History

Improve ARM assembly parsing diagnostics a bit. Catch potential cascading errors on a malformed so_reg operand and bail after the first error. Add some tests for the diagnostics we do want. llvm-svn: 135055
2011-07-14 02:49:30 +08:00
@ RUN: not llvm-mc -triple=armv7-apple-darwin < %s 2> %t
[ARM] Allow SP in rGPR, starting from ARMv8 Summary: This patch handles assembly and disassembly, but not codegen, as of yet. Additionally, it fixes a bug whereby SP and PC as shifted-reg operands were treated as predictable in ARMv7 Thumb; and it enables the tests for invalid and unpredictable instructions to run on both ARMv7 and ARMv8. Reviewers: jmolloy, rengolin Subscribers: aemerson, rengolin, llvm-commits Differential Revision: http://reviews.llvm.org/D14141 llvm-svn: 251516
2015-10-28 21:58:36 +08:00
@ RUN: FileCheck --check-prefix=CHECK-ERRORS --check-prefix=CHECK-ERRORS-V7 < %t %s
Add AArch32 DCPS{1,2,3} and HLT instructions. These were pretty straightforward instructions, with some assembly support required for HLT. The ARM assembler is keen to split the instruction mnemonic into a (non-existent) 'H' instruction with the LT condition code. An exception for HLT is needed. HLT follows the same rules as BKPT when in IT blocks, so the special BKPT hadling code has been adapted to handle HLT also. Regression tests added including diagnostic tests for out of range immediates and illegal condition codes, as well as negative tests for pre-ARMv8. llvm-svn: 190053
2013-09-05 22:14:19 +08:00
@ RUN: not llvm-mc -triple=armv8 < %s 2> %t
[ARM] Allow SP in rGPR, starting from ARMv8 Summary: This patch handles assembly and disassembly, but not codegen, as of yet. Additionally, it fixes a bug whereby SP and PC as shifted-reg operands were treated as predictable in ARMv7 Thumb; and it enables the tests for invalid and unpredictable instructions to run on both ARMv7 and ARMv8. Reviewers: jmolloy, rengolin Subscribers: aemerson, rengolin, llvm-commits Differential Revision: http://reviews.llvm.org/D14141 llvm-svn: 251516
2015-10-28 21:58:36 +08:00
@ RUN: FileCheck --check-prefix=CHECK-ERRORS --check-prefix=CHECK-ERRORS-V8 < %t %s
Improve ARM assembly parsing diagnostics a bit. Catch potential cascading errors on a malformed so_reg operand and bail after the first error. Add some tests for the diagnostics we do want. llvm-svn: 135055
2011-07-14 02:49:30 +08:00
@ Check for various assembly diagnostic messages on invalid input.
ARM diagnostic when 's' suffix on mnemonic that can't set flags. For example, "mlss r0, r1, r2, r3". The MLS instruction does not have a flag-setting variant. llvm-svn: 135203
2011-07-15 06:04:21 +08:00
@ 's' bit on an instruction that can't accept it.
mlss r1, r2, r3, r4
@ CHECK-ERRORS: error: instruction 'mls' can not set flags,
@ CHECK-ERRORS: but 's' suffix specified
Improve ARM assembly parsing diagnostics a bit. Catch potential cascading errors on a malformed so_reg operand and bail after the first error. Add some tests for the diagnostics we do want. llvm-svn: 135055
2011-07-14 02:49:30 +08:00
@ Out of range shift immediate values.
adc r1, r2, r3, lsl #invalid
adc r4, r5, r6, lsl #-1
adc r4, r5, r6, lsl #32
adc r4, r5, r6, lsr #-1
adc r4, r5, r6, lsr #33
adc r4, r5, r6, asr #-1
adc r4, r5, r6, asr #33
adc r4, r5, r6, ror #-1
adc r4, r5, r6, ror #32
@ CHECK-ERRORS: error: invalid immediate shift value
@ CHECK-ERRORS: adc r1, r2, r3, lsl #invalid
@ CHECK-ERRORS: ^
@ CHECK-ERRORS: error: immediate shift value out of range
@ CHECK-ERRORS: adc r4, r5, r6, lsl #-1
@ CHECK-ERRORS: ^
@ CHECK-ERRORS: error: immediate shift value out of range
@ CHECK-ERRORS: adc r4, r5, r6, lsl #32
@ CHECK-ERRORS: ^
@ CHECK-ERRORS: error: immediate shift value out of range
@ CHECK-ERRORS: adc r4, r5, r6, lsr #-1
@ CHECK-ERRORS: ^
@ CHECK-ERRORS: error: immediate shift value out of range
@ CHECK-ERRORS: adc r4, r5, r6, lsr #33
@ CHECK-ERRORS: ^
@ CHECK-ERRORS: error: immediate shift value out of range
@ CHECK-ERRORS: adc r4, r5, r6, asr #-1
@ CHECK-ERRORS: ^
@ CHECK-ERRORS: error: immediate shift value out of range
@ CHECK-ERRORS: adc r4, r5, r6, asr #33
@ CHECK-ERRORS: ^
@ CHECK-ERRORS: error: immediate shift value out of range
@ CHECK-ERRORS: adc r4, r5, r6, ror #-1
@ CHECK-ERRORS: ^
@ CHECK-ERRORS: error: immediate shift value out of range
@ CHECK-ERRORS: adc r4, r5, r6, ror #32
Range checking for 16-bit immediates in ARM assembly. llvm-svn: 135071
2011-07-14 04:10:10 +08:00
Fix the handling of edge cases in ARM shifted operands. This patch fixes load/store instructions to handle less common cases like "asr #32", "rrx" properly throughout the MC layer. Patch by Chris Lidbury. llvm-svn: 164455
2012-09-22 19:18:12 +08:00
@ Out of range shift immediate values for load/store.
str r1, [r2, r3, lsl #invalid]
ldr r4, [r5], r6, lsl #-1
pld r4, [r5, r6, lsl #32]
str r4, [r5], r6, lsr #-1
ldr r4, [r5, r6, lsr #33]
pld r4, [r5, r6, asr #-1]
str r4, [r5, r6, asr #33]
ldr r4, [r5, r6, ror #-1]
pld r4, [r5, r6, ror #32]
pld r4, [r5, r6, rrx #0]
Range checking for 16-bit immediates in ARM assembly. llvm-svn: 135071
2011-07-14 04:10:10 +08:00
Fix the handling of edge cases in ARM shifted operands. This patch fixes load/store instructions to handle less common cases like "asr #32", "rrx" properly throughout the MC layer. Patch by Chris Lidbury. llvm-svn: 164455
2012-09-22 19:18:12 +08:00
@ CHECK-ERRORS: error: shift amount must be an immediate
@ CHECK-ERRORS: str r1, [r2, r3, lsl #invalid]
@ CHECK-ERRORS: ^
@ CHECK-ERRORS: error: immediate shift value out of range
@ CHECK-ERRORS: ldr r4, [r5], r6, lsl #-1
@ CHECK-ERRORS: ^
@ CHECK-ERRORS: error: immediate shift value out of range
@ CHECK-ERRORS: pld r4, [r5, r6, lsl #32]
@ CHECK-ERRORS: ^
@ CHECK-ERRORS: error: immediate shift value out of range
@ CHECK-ERRORS: str r4, [r5], r6, lsr #-1
@ CHECK-ERRORS: ^
@ CHECK-ERRORS: error: immediate shift value out of range
@ CHECK-ERRORS: ldr r4, [r5, r6, lsr #33]
@ CHECK-ERRORS: ^
@ CHECK-ERRORS: error: immediate shift value out of range
@ CHECK-ERRORS: pld r4, [r5, r6, asr #-1]
@ CHECK-ERRORS: ^
@ CHECK-ERRORS: error: immediate shift value out of range
@ CHECK-ERRORS: str r4, [r5, r6, asr #33]
@ CHECK-ERRORS: ^
@ CHECK-ERRORS: error: immediate shift value out of range
@ CHECK-ERRORS: ldr r4, [r5, r6, ror #-1]
@ CHECK-ERRORS: ^
@ CHECK-ERRORS: error: immediate shift value out of range
@ CHECK-ERRORS: pld r4, [r5, r6, ror #32]
@ CHECK-ERRORS: error: ']' expected
@ CHECK-ERRORS: pld r4, [r5, r6, rrx #0]
Range checking for 16-bit immediates in ARM assembly. llvm-svn: 135071
2011-07-14 04:10:10 +08:00
@ Out of range 16-bit immediate on BKPT
bkpt #65536
Range checking for CDP[2] immediates. llvm-svn: 135092
2011-07-14 06:01:08 +08:00
@ CHECK-ERRORS: error: invalid operand for instruction
Add AArch32 DCPS{1,2,3} and HLT instructions. These were pretty straightforward instructions, with some assembly support required for HLT. The ARM assembler is keen to split the instruction mnemonic into a (non-existent) 'H' instruction with the LT condition code. An exception for HLT is needed. HLT follows the same rules as BKPT when in IT blocks, so the special BKPT hadling code has been adapted to handle HLT also. Regression tests added including diagnostic tests for out of range immediates and illegal condition codes, as well as negative tests for pre-ARMv8. llvm-svn: 190053
2013-09-05 22:14:19 +08:00
@ Out of range immediates for v8 HLT instruction.
hlt #65536
hlt #-1
[ARM] Allow SP in rGPR, starting from ARMv8 Summary: This patch handles assembly and disassembly, but not codegen, as of yet. Additionally, it fixes a bug whereby SP and PC as shifted-reg operands were treated as predictable in ARMv7 Thumb; and it enables the tests for invalid and unpredictable instructions to run on both ARMv7 and ARMv8. Reviewers: jmolloy, rengolin Subscribers: aemerson, rengolin, llvm-commits Differential Revision: http://reviews.llvm.org/D14141 llvm-svn: 251516
2015-10-28 21:58:36 +08:00
@CHECK-ERRORS: error: invalid operand for instruction
@CHECK-ERRORS: hlt #65536
@CHECK-ERRORS: ^
@CHECK-ERRORS: error: invalid operand for instruction
@CHECK-ERRORS: hlt #-1
@CHECK-ERRORS: ^
Add AArch32 DCPS{1,2,3} and HLT instructions. These were pretty straightforward instructions, with some assembly support required for HLT. The ARM assembler is keen to split the instruction mnemonic into a (non-existent) 'H' instruction with the LT condition code. An exception for HLT is needed. HLT follows the same rules as BKPT when in IT blocks, so the special BKPT hadling code has been adapted to handle HLT also. Regression tests added including diagnostic tests for out of range immediates and illegal condition codes, as well as negative tests for pre-ARMv8. llvm-svn: 190053
2013-09-05 22:14:19 +08:00
@ Illegal condition code for v8 HLT instruction.
hlteq #2
hltlt #23
[ARM] Allow SP in rGPR, starting from ARMv8 Summary: This patch handles assembly and disassembly, but not codegen, as of yet. Additionally, it fixes a bug whereby SP and PC as shifted-reg operands were treated as predictable in ARMv7 Thumb; and it enables the tests for invalid and unpredictable instructions to run on both ARMv7 and ARMv8. Reviewers: jmolloy, rengolin Subscribers: aemerson, rengolin, llvm-commits Differential Revision: http://reviews.llvm.org/D14141 llvm-svn: 251516
2015-10-28 21:58:36 +08:00
@CHECK-ERRORS: error: instruction 'hlt' is not predicable, but condition code specified
@CHECK-ERRORS: hlteq #2
@CHECK-ERRORS: ^
@CHECK-ERRORS: error: instruction 'hlt' is not predicable, but condition code specified
@CHECK-ERRORS: hltlt #23
@CHECK-ERRORS: ^
Add AArch32 DCPS{1,2,3} and HLT instructions. These were pretty straightforward instructions, with some assembly support required for HLT. The ARM assembler is keen to split the instruction mnemonic into a (non-existent) 'H' instruction with the LT condition code. An exception for HLT is needed. HLT follows the same rules as BKPT when in IT blocks, so the special BKPT hadling code has been adapted to handle HLT also. Regression tests added including diagnostic tests for out of range immediates and illegal condition codes, as well as negative tests for pre-ARMv8. llvm-svn: 190053
2013-09-05 22:14:19 +08:00
Range checking for CDP[2] immediates. llvm-svn: 135092
2011-07-14 06:01:08 +08:00
@ Out of range 4 and 3 bit immediates on CDP[2]
@ Out of range immediates for CDP/CDP2
cdp p7, #2, c1, c1, c1, #8
cdp p7, #1, c1, c1, c1, #8
cdp2 p7, #2, c1, c1, c1, #8
cdp2 p7, #1, c1, c1, c1, #8
@ CHECK-ERRORS: error: invalid operand for instruction
@ CHECK-ERRORS: error: invalid operand for instruction
@ CHECK-ERRORS: error: invalid operand for instruction
Range checking for 16-bit immediates in ARM assembly. llvm-svn: 135071
2011-07-14 04:10:10 +08:00
@ CHECK-ERRORS: error: invalid operand for instruction
ARM Assembler support for DBG instruction. Add range checking and testing for parsing and encoding of DBG instruction. llvm-svn: 135102
2011-07-14 06:59:38 +08:00
@ Out of range immediates for DBG
dbg #-1
dbg #16
ARM: Add a better diagnostic for some out of range immediates. As an example of how the custom DiagnosticType can be used to provide better operand-mismatch diagnostics, add a custom diagnostic for the imm0_15 operand class used for several system instructions. Update the tests to expect the improved diagnostic. rdar://8987109 llvm-svn: 159051
2012-06-23 07:56:48 +08:00
@ CHECK-ERRORS: error: immediate operand must be in the range [0,15]
@ CHECK-ERRORS: error: immediate operand must be in the range [0,15]
ARM Assembler support for DBG instruction. Add range checking and testing for parsing and encoding of DBG instruction. llvm-svn: 135102
2011-07-14 06:59:38 +08:00
@ Double-check that we're synced up with the right diagnostics.
@ CHECK-ERRORS: dbg #16
ARM MCR/MCR2 assembly parsing operand constraints. The immediate operands are restricted to 0-7. Enforce that when parsing assembly. llvm-svn: 135189
2011-07-15 05:19:17 +08:00
ARM MCRR/MCRR2 immediate operand range checking. llvm-svn: 135192
2011-07-15 05:26:42 +08:00
@ Out of range immediate for MCR/MCR2/MCRR/MCRR2
ARM MCR/MCR2 assembly parsing operand constraints. The immediate operands are restricted to 0-7. Enforce that when parsing assembly. llvm-svn: 135189
2011-07-15 05:19:17 +08:00
mcr p7, #8, r5, c1, c1, #4
mcr p7, #2, r5, c1, c1, #8
mcr2 p7, #8, r5, c1, c1, #4
mcr2 p7, #1, r5, c1, c1, #8
ARM MCRR/MCRR2 immediate operand range checking. llvm-svn: 135192
2011-07-15 05:26:42 +08:00
mcrr p7, #16, r5, r4, c1
mcrr2 p7, #16, r5, r4, c1
@ CHECK-ERRORS: error: invalid operand for instruction
@ CHECK-ERRORS: error: invalid operand for instruction
ARM MCR/MCR2 assembly parsing operand constraints. The immediate operands are restricted to 0-7. Enforce that when parsing assembly. llvm-svn: 135189
2011-07-15 05:19:17 +08:00
@ CHECK-ERRORS: error: invalid operand for instruction
@ CHECK-ERRORS: error: invalid operand for instruction
ARM: Add a better diagnostic for some out of range immediates. As an example of how the custom DiagnosticType can be used to provide better operand-mismatch diagnostics, add a custom diagnostic for the imm0_15 operand class used for several system instructions. Update the tests to expect the improved diagnostic. rdar://8987109 llvm-svn: 159051
2012-06-23 07:56:48 +08:00
@ CHECK-ERRORS: error: immediate operand must be in the range [0,15]
[ARM] Allow SP in rGPR, starting from ARMv8 Summary: This patch handles assembly and disassembly, but not codegen, as of yet. Additionally, it fixes a bug whereby SP and PC as shifted-reg operands were treated as predictable in ARMv7 Thumb; and it enables the tests for invalid and unpredictable instructions to run on both ARMv7 and ARMv8. Reviewers: jmolloy, rengolin Subscribers: aemerson, rengolin, llvm-commits Differential Revision: http://reviews.llvm.org/D14141 llvm-svn: 251516
2015-10-28 21:58:36 +08:00
@ CHECK-ERRORS-V7: error: immediate operand must be in the range [0,15]
@ CHECK-ERRORS-V8: error: invalid operand for instruction
ARM assembly parsing for MOV (immediate). Add range checking for the immediate operand and handle the "mov" mnemonic choosing between encodings based on the value of the immediate. Add tests for fixups, encoding choice and values, and diagnostic for out of range values. llvm-svn: 135500
2011-07-20 03:13:28 +08:00
[ARM] In ARMAsmParser, MatchCoprocessorOperandName() permitted p10 and p11 as operands for coprocessor instructions, resulting in encodings that clash with FP/NEON instruction encodings llvm-svn: 194253
2013-11-08 17:16:31 +08:00
@ p10 and p11 are reserved for NEON
mcr p10, #2, r5, c1, c1, #4
mcrr p11, #8, r5, r4, c1
@ CHECK-ERRORS: error: invalid operand for instruction
@ CHECK-ERRORS: error: invalid operand for instruction
ARM assembly parsing for MOV (immediate). Add range checking for the immediate operand and handle the "mov" mnemonic choosing between encodings based on the value of the immediate. Add tests for fixups, encoding choice and values, and diagnostic for out of range values. llvm-svn: 135500
2011-07-20 03:13:28 +08:00
@ Out of range immediate for MOV
movw r9, 0x10000
@ CHECK-ERRORS: error: invalid operand for instruction
ARM assembly parsing for MOV (register). Correct the handling of the 's' suffix when parsing ARM mode. It's only a truly separate opcode in Thumb. Add test cases to make sure we handle the s and condition suffices correctly, including diagnostics. llvm-svn: 135513
2011-07-20 04:10:31 +08:00
@ Invalid 's' bit usage for MOVW
movs r6, #0xffff
movwseq r9, #0xffff
@ CHECK-ERRORS: error: invalid operand for instruction
@ CHECK-ERRORS: error: instruction 'movw' can not set flags, but 's' suffix specified
ARM testcases for MOVT. llvm-svn: 135516
2011-07-20 04:23:25 +08:00
@ Out of range immediate for MOVT
movt r9, 0x10000
ARM assembly parsing for MRC/MRC2/MRRC/MRRC2. Add range checking to the immediate operands. Update tests accordingly. llvm-svn: 135521
2011-07-20 04:35:35 +08:00
@ CHECK-ERRORS: error: invalid operand for instruction
@ Out of range immediates for MRC/MRC2/MRRC/MRRC2
mrc p14, #8, r1, c1, c2, #4
mrc p14, #1, r1, c1, c2, #8
mrc2 p14, #8, r1, c1, c2, #4
mrc2 p14, #0, r1, c1, c2, #9
mrrc p7, #16, r5, r4, c1
mrrc2 p7, #17, r5, r4, c1
@ CHECK-ERRORS: error: invalid operand for instruction
@ CHECK-ERRORS: error: invalid operand for instruction
@ CHECK-ERRORS: error: invalid operand for instruction
@ CHECK-ERRORS: error: invalid operand for instruction
ARM: Add a better diagnostic for some out of range immediates. As an example of how the custom DiagnosticType can be used to provide better operand-mismatch diagnostics, add a custom diagnostic for the imm0_15 operand class used for several system instructions. Update the tests to expect the improved diagnostic. rdar://8987109 llvm-svn: 159051
2012-06-23 07:56:48 +08:00
@ CHECK-ERRORS: error: immediate operand must be in the range [0,15]
[ARM] Allow SP in rGPR, starting from ARMv8 Summary: This patch handles assembly and disassembly, but not codegen, as of yet. Additionally, it fixes a bug whereby SP and PC as shifted-reg operands were treated as predictable in ARMv7 Thumb; and it enables the tests for invalid and unpredictable instructions to run on both ARMv7 and ARMv8. Reviewers: jmolloy, rengolin Subscribers: aemerson, rengolin, llvm-commits Differential Revision: http://reviews.llvm.org/D14141 llvm-svn: 251516
2015-10-28 21:58:36 +08:00
@ CHECK-ERRORS-V7: error: immediate operand must be in the range [0,15]
@ CHECK-ERRORS-V8: error: invalid operand for instruction
Add tests for ARM PKH assembly parsing. llvm-svn: 135696
2011-07-22 03:02:03 +08:00
@ Shifter operand validation for PKH instructions.
pkhbt r2, r2, r3, lsl #-1
pkhbt r2, r2, r3, lsl #32
pkhtb r2, r2, r3, asr #0
pkhtb r2, r2, r3, asr #33
pkhbt r2, r2, r3, asr #3
pkhtb r2, r2, r3, lsl #3
Update ARM STM tests. Fix check: prefix for diagnostic tests. llvm-svn: 136088
2011-07-26 23:41:22 +08:00
@ CHECK-ERRORS: error: immediate value out of range
@ CHECK-ERRORS: pkhbt r2, r2, r3, lsl #-1
@ CHECK-ERRORS: ^
@ CHECK-ERRORS: error: immediate value out of range
@ CHECK-ERRORS: pkhbt r2, r2, r3, lsl #32
@ CHECK-ERRORS: ^
@ CHECK-ERRORS: error: immediate value out of range
@ CHECK-ERRORS: pkhtb r2, r2, r3, asr #0
@ CHECK-ERRORS: ^
@ CHECK-ERRORS: error: immediate value out of range
@ CHECK-ERRORS: pkhtb r2, r2, r3, asr #33
@ CHECK-ERRORS: ^
@ CHECK-ERRORS: error: lsl operand expected.
@ CHECK-ERRORS: pkhbt r2, r2, r3, asr #3
@ CHECK-ERRORS: ^
@ CHECK-ERRORS: error: asr operand expected.
@ CHECK-ERRORS: pkhtb r2, r2, r3, lsl #3
@ CHECK-ERRORS: ^
ARM assembly parsing and encoding for SETEND instruction. Add parsing and diagnostics for malformed inputs. Tests for diagnostics and for correct encodings. llvm-svn: 135776
2011-07-23 01:44:50 +08:00
@ bad values for SETEND
setendne be
setend me
setend 1
Update ARM STM tests. Fix check: prefix for diagnostic tests. llvm-svn: 136088
2011-07-26 23:41:22 +08:00
@ CHECK-ERRORS: error: instruction 'setend' is not predicable, but condition code specified
@ CHECK-ERRORS: setendne be
@ CHECK-ERRORS: ^
@ CHECK-ERRORS: error: 'be' or 'le' operand expected
@ CHECK-ERRORS: setend me
@ CHECK-ERRORS: ^
@ CHECK-ERRORS: error: 'be' or 'le' operand expected
@ CHECK-ERRORS: setend 1
@ CHECK-ERRORS: ^
ARM assembly parsing and encoding for SSAT instruction. Fix the Rn register encoding for both SSAT and USAT. Update the parsing of the shift operand to correctly handle the allowed shift types and immediate ranges and issue meaningful diagnostics when an illegal value or shift type is specified. Add aliases to parse an ommitted shift operand (default value of 'lsl #0'). Add tests for diagnostics and proper encoding. llvm-svn: 135990
2011-07-26 06:20:28 +08:00
@ Out of range immediates and bad shift types for SSAT
ssat r8, #0, r10, lsl #8
ssat r8, #33, r10, lsl #8
ssat r8, #1, r10, lsl #-1
ssat r8, #1, r10, lsl #32
ssat r8, #1, r10, asr #0
ssat r8, #1, r10, asr #33
ssat r8, #1, r10, lsr #5
ssat r8, #1, r10, lsl fred
ssat r8, #1, r10, lsl #fred
Update ARM STM tests. Fix check: prefix for diagnostic tests. llvm-svn: 136088
2011-07-26 23:41:22 +08:00
@ CHECK-ERRORS: error: invalid operand for instruction
@ CHECK-ERRORS: ssat r8, #0, r10, lsl #8
@ CHECK-ERRORS: ^
@ CHECK-ERRORS: error: invalid operand for instruction
@ CHECK-ERRORS: ssat r8, #33, r10, lsl #8
@ CHECK-ERRORS: ^
@ CHECK-ERRORS: error: 'lsr' shift amount must be in range [0,31]
@ CHECK-ERRORS: ssat r8, #1, r10, lsl #-1
@ CHECK-ERRORS: ^
@ CHECK-ERRORS: error: 'lsr' shift amount must be in range [0,31]
@ CHECK-ERRORS: ssat r8, #1, r10, lsl #32
@ CHECK-ERRORS: ^
@ CHECK-ERRORS: error: 'asr' shift amount must be in range [1,32]
@ CHECK-ERRORS: ssat r8, #1, r10, asr #0
@ CHECK-ERRORS: ^
@ CHECK-ERRORS: error: 'asr' shift amount must be in range [1,32]
@ CHECK-ERRORS: ssat r8, #1, r10, asr #33
@ CHECK-ERRORS: ^
@ CHECK-ERRORS: error: shift operator 'asr' or 'lsl' expected
@ CHECK-ERRORS: ssat r8, #1, r10, lsr #5
@ CHECK-ERRORS: ^
@ CHECK-ERRORS: error: '#' expected
@ CHECK-ERRORS: ssat r8, #1, r10, lsl fred
@ CHECK-ERRORS: ^
@ CHECK-ERRORS: error: shift amount must be an immediate
@ CHECK-ERRORS: ssat r8, #1, r10, lsl #fred
@ CHECK-ERRORS: ^
ARM assembly parsing and encoding for SSAT16 instruction. llvm-svn: 136006
2011-07-26 07:09:14 +08:00
@ Out of range immediates for SSAT16
ssat16 r2, #0, r7
ssat16 r3, #17, r5
Update ARM STM tests. Fix check: prefix for diagnostic tests. llvm-svn: 136088
2011-07-26 23:41:22 +08:00
@ CHECK-ERRORS: error: invalid operand for instruction
@ CHECK-ERRORS: ssat16 r2, #0, r7
@ CHECK-ERRORS: ^
@ CHECK-ERRORS: error: invalid operand for instruction
@ CHECK-ERRORS: ssat16 r3, #17, r5
@ CHECK-ERRORS: ^
@ Out of order STM registers
stmda sp!, {r5, r2}
ARM ldm/stm register lists can be out of order. It's not a good style idea, as the registers will be laid down in memory in numerical order, not the order they're in the list, but it's legal. vldm/vstm are stricter. rdar://11064740 llvm-svn: 152943
2012-03-17 04:48:38 +08:00
@ CHECK-ERRORS: warning: register list not in ascending order
Update ARM STM tests. Fix check: prefix for diagnostic tests. llvm-svn: 136088
2011-07-26 23:41:22 +08:00
@ CHECK-ERRORS: stmda sp!, {r5, r2}
@ CHECK-ERRORS: ^
ARM parsing and encoding for SVC instruction. llvm-svn: 136090
2011-07-27 00:24:27 +08:00
@ Out of range immediate on SVC
svc #0x1000000
@ CHECK-ERRORS: error: invalid operand for instruction
@ CHECK-ERRORS: svc #0x1000000
@ CHECK-ERRORS: ^
ARM diagnostics for ldrexd/stredx out of order paired register operands. llvm-svn: 136110
2011-07-27 02:25:39 +08:00
@ Out of order Rt/Rt2 operands for ldrexd/strexd
ldrexd r4, r3, [r8]
strexd r6, r5, r3, [r8]
@ CHECK-ERRORS: error: destination operands must be sequential
@ CHECK-ERRORS: ldrexd r4, r3, [r8]
@ CHECK-ERRORS: ^
@ CHECK-ERRORS: error: source operands must be sequential
@ CHECK-ERRORS: strexd r6, r5, r3, [r8]
@ CHECK-ERRORS: ^
ARM assembly parsing and encoding for extend instructions. Assembly parser handling for extend instruction rotate operands. Add tests for the sign extend instructions. llvm-svn: 136252
2011-07-28 04:15:40 +08:00
@ Illegal rotate operators for extend instructions
sxtb r8, r3, #8
sxtb r8, r3, ror 24
sxtb r8, r3, ror #8 -
sxtab r3, r8, r3, ror #(fred - wilma)
sxtab r7, r8, r3, ror #25
sxtah r9, r3, r3, ror #-8
sxtb16ge r2, r3, lsr #24
Thumb2 assembly parsing and encoding for SXTB/SXTB16/SXTH. llvm-svn: 140047
2011-09-20 04:29:33 +08:00
@ CHECK-ERRORS: error: invalid operand for instruction
ARM assembly parsing and encoding for extend instructions. Assembly parser handling for extend instruction rotate operands. Add tests for the sign extend instructions. llvm-svn: 136252
2011-07-28 04:15:40 +08:00
@ CHECK-ERRORS: sxtb r8, r3, #8
@ CHECK-ERRORS: ^
@ CHECK-ERRORS: error: '#' expected
@ CHECK-ERRORS: sxtb r8, r3, ror 24
@ CHECK-ERRORS: ^
@ CHECK-ERRORS: error: unknown token in expression
@ CHECK-ERRORS: sxtb r8, r3, ror #8 -
@ CHECK-ERRORS: ^
@ CHECK-ERRORS: error: malformed rotate expression
@ CHECK-ERRORS: sxtb r8, r3, ror #8 -
@ CHECK-ERRORS: ^
@ CHECK-ERRORS: error: rotate amount must be an immediate
@ CHECK-ERRORS: sxtab r3, r8, r3, ror #(fred - wilma)
@ CHECK-ERRORS: ^
@ CHECK-ERRORS: error: 'ror' rotate amount must be 8, 16, or 24
@ CHECK-ERRORS: sxtab r7, r8, r3, ror #25
@ CHECK-ERRORS: ^
@ CHECK-ERRORS: error: 'ror' rotate amount must be 8, 16, or 24
@ CHECK-ERRORS: sxtah r9, r3, r3, ror #-8
@ CHECK-ERRORS: ^
Thumb2 assembly parsing and encoding for SXTB/SXTB16/SXTH. llvm-svn: 140047
2011-09-20 04:29:33 +08:00
@ CHECK-ERRORS: error: invalid operand for instruction
ARM assembly parsing and encoding for extend instructions. Assembly parser handling for extend instruction rotate operands. Add tests for the sign extend instructions. llvm-svn: 136252
2011-07-28 04:15:40 +08:00
@ CHECK-ERRORS: sxtb16ge r2, r3, lsr #24
@ CHECK-ERRORS: ^
ARM parsing and encoding of SBFX and UBFX. Encode the width operand as it encodes in the instruction, which simplifies the disassembler and the encoder, by using the imm1_32 operand def. Add a diagnostic for the context-sensitive constraint that the width must be in the range [1,32-lsb]. llvm-svn: 136264
2011-07-28 05:09:25 +08:00
@ Out of range width for SBFX/UBFX
sbfx r4, r5, #31, #2
ubfxgt r4, r5, #16, #17
@ CHECK-ERRORS: error: bitfield width must be in range [1,32-lsb]
@ CHECK-ERRORS: sbfx r4, r5, #31, #2
@ CHECK-ERRORS: ^
@ CHECK-ERRORS: error: bitfield width must be in range [1,32-lsb]
@ CHECK-ERRORS: ubfxgt r4, r5, #16, #17
@ CHECK-ERRORS: ^
ARM LDRD(immediate) assembly parsing and encoding support. llvm-svn: 137244
2011-08-11 04:29:19 +08:00
ARM: mark UBFX as not allowing PC. Strictly, it's unpredictable. But we don't quite model that yet and an error is better than ignoring the issue. This one somehow got left out before though. rdar://problem/15997748 llvm-svn: 211490
2014-06-23 17:20:02 +08:00
@ Using pc for SBFX/UBFX
sbfx pc, r2, #1, #3
sbfx sp, pc, #4, #5
ubfx pc, r0, #0, #31
ubfx r14, pc, #1, #2
@ CHECK-ERRORS: error: invalid operand for instruction
@ CHECK-ERRORS: sbfx pc, r2, #1, #3
@ CHECK-ERRORS: ^
@ CHECK-ERRORS: error: invalid operand for instruction
@ CHECK-ERRORS: sbfx sp, pc, #4, #5
@ CHECK-ERRORS: ^
@ CHECK-ERRORS: error: invalid operand for instruction
@ CHECK-ERRORS: ubfx pc, r0, #0, #31
@ CHECK-ERRORS: ^
@ CHECK-ERRORS: error: invalid operand for instruction
@ CHECK-ERRORS: ubfx r14, pc, #1, #2
@ CHECK-ERRORS: ^
ARM LDRD(immediate) assembly parsing and encoding support. llvm-svn: 137244
2011-08-11 04:29:19 +08:00
@ Out of order Rt/Rt2 operands for ldrd
ldrd r4, r3, [r8]
ldrd r4, r3, [r8, #8]!
ldrd r4, r3, [r8], #8
@ CHECK-ERRORS: error: destination operands must be sequential
@ CHECK-ERRORS: ldrd r4, r3, [r8]
@ CHECK-ERRORS: ^
@ CHECK-ERRORS: error: destination operands must be sequential
@ CHECK-ERRORS: ldrd r4, r3, [r8, #8]!
@ CHECK-ERRORS: ^
@ CHECK-ERRORS: error: destination operands must be sequential
@ CHECK-ERRORS: ldrd r4, r3, [r8], #8
@ CHECK-ERRORS: ^
ARM fix assembly parser handling of ranges in register lists. Clean up register list handling in general a bit to explicitly check things like all the registers being from the same register class. rdar://8883573 llvm-svn: 139707
2011-09-15 02:08:35 +08:00
@ Bad register lists for VFP.
vpush {s0, s3}
@ CHECK-ERRORS: error: non-contiguous register range
@ CHECK-ERRORS: vpush {s0, s3}
@ CHECK-ERRORS: ^
ARM parsing and encoding for the <option> form of LDC/STC instructions. llvm-svn: 141786
2011-10-13 01:34:41 +08:00
@ Out of range coprocessor option immediate.
ldc2 p2, c8, [r1], { 256 }
ldc2 p2, c8, [r1], { -1 }
[ARM] Allow SP in rGPR, starting from ARMv8 Summary: This patch handles assembly and disassembly, but not codegen, as of yet. Additionally, it fixes a bug whereby SP and PC as shifted-reg operands were treated as predictable in ARMv7 Thumb; and it enables the tests for invalid and unpredictable instructions to run on both ARMv7 and ARMv8. Reviewers: jmolloy, rengolin Subscribers: aemerson, rengolin, llvm-commits Differential Revision: http://reviews.llvm.org/D14141 llvm-svn: 251516
2015-10-28 21:58:36 +08:00
@ CHECK-ERRORS-V7: error: coprocessor option must be an immediate in range [0, 255]
@ CHECK-ERRORS-V7: ldc2 p2, c8, [r1], { 256 }
@ CHECK-ERRORS-V7: ^
@ CHECK-ERRORS-V8: error: register expected
@ CHECK-ERRORS-V7: error: coprocessor option must be an immediate in range [0, 255]
@ CHECK-ERRORS-V7: ldc2 p2, c8, [r1], { -1 }
@ CHECK-ERRORS-V7: ^
@ CHECK-ERRORS-V8: error: register expected
Replace assertion failure for badly formatted CPS instrution with error message. llvm-svn: 158445
2012-06-14 18:48:04 +08:00
@ Bad CPS instruction format.
cps f,#1
@ CHECK-ERRORS: error: invalid operand for instruction
@ CHECK-ERRORS: cps f,#1
@ CHECK-ERRORS: ^
Test case for r165480. llvm-svn: 165594
2012-10-10 10:54:23 +08:00
@ Bad operands for msr
msr #0, #0
msr foo, #0
@ CHECK-ERRORS: error: invalid operand for instruction
@ CHECK-ERRORS: msr #0, #0
@ CHECK-ERRORS: ^
@ CHECK-ERRORS: error: invalid operand for instruction
@ CHECK-ERRORS: msr foo, #0
@ CHECK-ERRORS: ^
ARM: ISB cannot be passed the same options as DMB ISB should only accepts full system sync, other options are reserved llvm-svn: 183656
2013-06-10 22:17:08 +08:00
isb #-1
isb #16
@ CHECK-ERRORS: error: immediate value out of range
@ CHECK-ERRORS: error: immediate value out of range
Change the arm assembler to support this from the v7c spec: "When assembling to the ARM instruction set, the .N qualifier produces an assembler error and the .W qualifier has no effect." In the pre-matcher handler in the asm parser the ".w" (wide) qualifier when in ARM mode is now discarded. And an error message is now produced when the ".n" (narrow) qualifier is used in ARM mode. Test cases for these were added. rdar://14064574 llvm-svn: 184224
2013-06-19 04:19:24 +08:00
nop.n
@ CHECK-ERRORS: error: instruction with .n (narrow) qualifier not allowed in arm mode
ARM: allow predicated barriers in Thumb mode The barrier instructions are only "always-execute" in ARM mode, they can quite happily sit inside an IT block in Thumb. llvm-svn: 184964
2013-06-27 00:52:32 +08:00
dmbeq #5
dsble #15
isblo #7
@ CHECK-ERRORS: error: instruction 'dmb' is not predicable, but condition code specified
@ CHECK-ERRORS: error: instruction 'dsb' is not predicable, but condition code specified
@ CHECK-ERRORS: error: instruction 'isb' is not predicable, but condition code specified
dmblt
dsbne
isbeq
@ CHECK-ERRORS: error: instruction 'dmb' is not predicable, but condition code specified
@ CHECK-ERRORS: error: instruction 'dsb' is not predicable, but condition code specified
@ CHECK-ERRORS: error: instruction 'isb' is not predicable, but condition code specified
ARM: fix more cases where predication may or may not be allowed Unfortunately this addresses two issues (by the time I'd disentangled the logic it wasn't worth putting it back to half-broken): + Coprocessor instructions should all be predicable in Thumb mode. + BKPT should never be predicable. llvm-svn: 184965
2013-06-27 00:52:40 +08:00
mcr2le p7, #1, r5, c1, c1, #4
mcrr2ne p7, #15, r5, r4, c1
mrc2lo p14, #0, r1, c1, c2, #4
mrrc2lo p7, #1, r5, r4, c1
cdp2hi p10, #0, c6, c12, c0, #7
@ CHECK-ERRORS: error: instruction 'mcr2' is not predicable, but condition code specified
@ CHECK-ERRORS: error: instruction 'mcrr2' is not predicable, but condition code specified
@ CHECK-ERRORS: error: instruction 'mrc2' is not predicable, but condition code specified
@ CHECK-ERRORS: error: instruction 'mrrc2' is not predicable, but condition code specified
@ CHECK-ERRORS: error: instruction 'cdp2' is not predicable, but condition code specified
bkpteq #7
@ CHECK-ERRORS: error: instruction 'bkpt' is not predicable, but condition code specified
ARM: provide diagnostics on more writeback LDM/STM instructions The set of circumstances where the writeback register is allowed to be in the list of registers is rather baroque, but I think this implements them all on the assembly parsing side. For disassembly, we still warn about an ARM-mode LDM even if the architecture revision is < v7 (the required architecture information isn't available). It's a silly instruction anyway, so hopefully no-one will mind. rdar://problem/15223374 llvm-svn: 193185
2013-10-23 03:00:39 +08:00
ldm r2!, {r2, r3}
ldmdb r2!, {r2, r3}
ldmda r2!, {r2, r3}
ARM: fix assert on unpredictable POP instruction. POP instructions are aliased to the ARM LDM variants but have different syntax. This caused two problems: we tried to access a non-existent operand to annotate the '!', and the error message didn't make much sense. With some vigorous hand-waving in the error message both problems can be fixed. llvm-svn: 193322
2013-10-24 17:37:18 +08:00
popeq {sp}
@ CHECK-ERRORS: error: writeback register not allowed in register list
@ CHECK-ERRORS: error: writeback register not allowed in register list
@ CHECK-ERRORS: error: writeback register not allowed in register list
@ CHECK-ERRORS: error: writeback register not allowed in register list
ARM: mark various aliases with their architecture requirements. If an alias inherits directly from InstAlias then it doesn't get any default "Requires" values, so llvm-mc will allow it even on architectures that don't support the underlying instruction. This tidies up the obvious VFP and NEON cases I found. llvm-svn: 193340
2013-10-24 20:22:58 +08:00
vrintz.f32.f32 s0, s1
vrintr.f32 s0, s1
vrintx.f64.f64 d2, d5
vrintz.f64 d10, d9
vrinta.f32.f32 s6, s7
vrintn.f32 s8, s9
vrintp.f64.f64 d10, d11
vrintm.f64 d12, d13
[ARM] Allow SP in rGPR, starting from ARMv8 Summary: This patch handles assembly and disassembly, but not codegen, as of yet. Additionally, it fixes a bug whereby SP and PC as shifted-reg operands were treated as predictable in ARMv7 Thumb; and it enables the tests for invalid and unpredictable instructions to run on both ARMv7 and ARMv8. Reviewers: jmolloy, rengolin Subscribers: aemerson, rengolin, llvm-commits Differential Revision: http://reviews.llvm.org/D14141 llvm-svn: 251516
2015-10-28 21:58:36 +08:00
@ CHECK-ERRORS-V7: error: instruction requires: FPARMv8
@ CHECK-ERRORS-V7: error: instruction requires: FPARMv8
@ CHECK-ERRORS-V7: error: instruction requires: FPARMv8
@ CHECK-ERRORS-V7: error: instruction requires: FPARMv8
@ CHECK-ERRORS-V7: error: instruction requires: FPARMv8
@ CHECK-ERRORS-V7: error: instruction requires: FPARMv8
@ CHECK-ERRORS-V7: error: instruction requires: FPARMv8
@ CHECK-ERRORS-V7: error: instruction requires: FPARMv8
ARM: diagnose invalid system LDM/STM The system LDM and STM instructions can't usually writeback to the base register. The one exception is when an LDM is actually an exception-return (i.e. contains PC in the register list). (There's already a test that "ldm sp!, {r0-r3, pc}^" works, which is why there is no positive test). rdar://problem/15223374 llvm-svn: 194512
2013-11-13 05:32:41 +08:00
stm sp!, {r0, pc}^
ldm sp!, {r0}^
@ CHECK-ERRORS: error: system STM cannot have writeback register
@ CHECK-ERRORS: error: writeback register only allowed on system LDM if PC in register-list
Change the ARM assembler to require a :lower16: or :upper16 on non-constant expressions for mov instructions instead of silently truncating by default. For the ARM assembler, we want to avoid misleadingly allowing something like "mov r0, <symbol>" especially when we turn it into a movw and the expression <symbol> does not have a :lower16: or :upper16" as part of the expression. We don't want the behavior of silently truncating, which can be unexpected and lead to bugs that are difficult to find since this is an easy mistake to make. This does change the previous behavior of llvm but actually matches an older gnu assembler that would not allow this but print less useful errors of like “invalid constant (0x927c0) after fixup” and “unsupported relocation on symbol foo”. The error for llvm is "immediate expression for mov requires :lower16: or :upper16" with correct location information on the operand as shown in the added test cases. rdar://12342160 llvm-svn: 206669
2014-04-19 07:06:39 +08:00
foo2:
mov r0, foo2
movw r0, foo2
@ CHECK-ERRORS: error: immediate expression for mov requires :lower16: or :upper16
@ CHECK-ERRORS: ^
@ CHECK-ERRORS: error: immediate expression for mov requires :lower16: or :upper16
@ CHECK-ERRORS: ^
[ARM] Make the assembler reject unpredictable pre/post-indexed ARM STR instructions. The ARM ARM prohibits STR instructions with writeback into the source register. With this commit this constraint is now enforced and we stop assembling STR instructions with unpredictable behavior. llvm-svn: 213745
2014-07-23 20:38:17 +08:00
str r0, [r0, #4]!
str r0, [r0, r1]!
str r0, [r0], #4
str r0, [r0], r1
[ARM] Make the assembler reject unpredictable pre/post-indexed ARM STRH instructions. The ARM ARM prohibits STRH instructions with writeback into the source register. With this commit this constraint is now enforced and we stop assembling STRH instructions with unpredictable behavior. llvm-svn: 213850
2014-07-24 17:55:46 +08:00
strh r0, [r0, #2]!
strh r0, [r0, r1]!
strh r0, [r0], #2
strh r0, [r0], r1
[ARM] Make the assembler reject unpredictable pre/post-indexed ARM STRB instructions. The ARM ARM prohibits STRB instructions with writeback into the source register. With this commit this constraint is now enforced and we stop assembling STRB instructions with unpredictable behavior. llvm-svn: 213750
2014-07-23 21:03:47 +08:00
strb r0, [r0, #1]!
strb r0, [r0, r1]!
strb r0, [r0], #1
strb r0, [r0], r1
[ARM] Make the assembler reject unpredictable pre/post-indexed ARM STR instructions. The ARM ARM prohibits STR instructions with writeback into the source register. With this commit this constraint is now enforced and we stop assembling STR instructions with unpredictable behavior. llvm-svn: 213745
2014-07-23 20:38:17 +08:00
@ CHECK-ERRORS: error: source register and base register can't be identical
@ CHECK-ERRORS: str r0, [r0, #4]!
@ CHECK-ERRORS: ^
@ CHECK-ERRORS: error: source register and base register can't be identical
@ CHECK-ERRORS: str r0, [r0, r1]!
@ CHECK-ERRORS: ^
@ CHECK-ERRORS: error: source register and base register can't be identical
@ CHECK-ERRORS: str r0, [r0], #4
@ CHECK-ERRORS: ^
@ CHECK-ERRORS: error: source register and base register can't be identical
@ CHECK-ERRORS: str r0, [r0], r1
@ CHECK-ERRORS: ^
[ARM] Make the assembler reject unpredictable pre/post-indexed ARM STRB instructions. The ARM ARM prohibits STRB instructions with writeback into the source register. With this commit this constraint is now enforced and we stop assembling STRB instructions with unpredictable behavior. llvm-svn: 213750
2014-07-23 21:03:47 +08:00
@ CHECK-ERRORS: error: source register and base register can't be identical
[ARM] Make the assembler reject unpredictable pre/post-indexed ARM STRH instructions. The ARM ARM prohibits STRH instructions with writeback into the source register. With this commit this constraint is now enforced and we stop assembling STRH instructions with unpredictable behavior. llvm-svn: 213850
2014-07-24 17:55:46 +08:00
@ CHECK-ERRORS: strh r0, [r0, #2]!
@ CHECK-ERRORS: ^
@ CHECK-ERRORS: error: source register and base register can't be identical
@ CHECK-ERRORS: strh r0, [r0, r1]!
@ CHECK-ERRORS: ^
@ CHECK-ERRORS: error: source register and base register can't be identical
@ CHECK-ERRORS: strh r0, [r0], #2
@ CHECK-ERRORS: ^
@ CHECK-ERRORS: error: source register and base register can't be identical
@ CHECK-ERRORS: strh r0, [r0], r1
@ CHECK-ERRORS: ^
@ CHECK-ERRORS: error: source register and base register can't be identical
[ARM] Make the assembler reject unpredictable pre/post-indexed ARM STRB instructions. The ARM ARM prohibits STRB instructions with writeback into the source register. With this commit this constraint is now enforced and we stop assembling STRB instructions with unpredictable behavior. llvm-svn: 213750
2014-07-23 21:03:47 +08:00
@ CHECK-ERRORS: strb r0, [r0, #1]!
@ CHECK-ERRORS: ^
@ CHECK-ERRORS: error: source register and base register can't be identical
@ CHECK-ERRORS: strb r0, [r0, r1]!
@ CHECK-ERRORS: ^
@ CHECK-ERRORS: error: source register and base register can't be identical
@ CHECK-ERRORS: strb r0, [r0], #1
@ CHECK-ERRORS: ^
@ CHECK-ERRORS: error: source register and base register can't be identical
@ CHECK-ERRORS: strb r0, [r0], r1
@ CHECK-ERRORS: ^
[ARM] Make the assembler reject unpredictable pre/post-indexed ARM LDR instructions. The ARM ARM prohibits LDR instructions with writeback into the destination register. With this commit this constraint is now enforced and we stop assembling LDR instructions with unpredictable behavior. llvm-svn: 214498
2014-08-01 19:08:51 +08:00
ldr r0, [r0, #4]!
ldr r0, [r0, r1]!
ldr r0, [r0], #4
ldr r0, [r0], r1
[ARM] Make the assembler reject unpredictable pre/post-indexed ARM LDRH/LDRSH instructions. The ARM ARM prohibits LDRH/LDRSH instructions with writeback into the source register. With this commit this constraint is now enforced and we stop assembling LDRH/LDRSH instructions with unpredictable behavior. llvm-svn: 214499
2014-08-01 19:33:47 +08:00
ldrh r0, [r0, #2]!
ldrh r0, [r0, r1]!
ldrh r0, [r0], #2
ldrh r0, [r0], r1
ldrsh r0, [r0, #2]!
ldrsh r0, [r0, r1]!
ldrsh r0, [r0], #2
ldrsh r0, [r0], r1
[ARM] Make the assembler reject unpredictable pre/post-indexed ARM LDRB/LDRSB instructions. The ARM ARM prohibits LDRB/LDRSB instructions with writeback into the destination register. With this commit this constraint is now enforced and we stop assembling LDRH/LDRSH instructions with unpredictable behavior. llvm-svn: 214500
2014-08-01 20:08:04 +08:00
ldrb r0, [r0, #1]!
ldrb r0, [r0, r1]!
ldrb r0, [r0], #1
ldrb r0, [r0], r1
ldrsb r0, [r0, #1]!
ldrsb r0, [r0, r1]!
ldrsb r0, [r0], #1
ldrsb r0, [r0], r1
[ARM] Make the assembler reject unpredictable pre/post-indexed ARM LDR instructions. The ARM ARM prohibits LDR instructions with writeback into the destination register. With this commit this constraint is now enforced and we stop assembling LDR instructions with unpredictable behavior. llvm-svn: 214498
2014-08-01 19:08:51 +08:00
@ CHECK-ERRORS: error: destination register and base register can't be identical
@ CHECK-ERRORS: ldr r0, [r0, #4]!
@ CHECK-ERRORS: ^
@ CHECK-ERRORS: error: destination register and base register can't be identical
@ CHECK-ERRORS: ldr r0, [r0, r1]!
@ CHECK-ERRORS: ^
@ CHECK-ERRORS: error: destination register and base register can't be identical
@ CHECK-ERRORS: ldr r0, [r0], #4
@ CHECK-ERRORS: ^
@ CHECK-ERRORS: error: destination register and base register can't be identical
@ CHECK-ERRORS: ldr r0, [r0], r1
@ CHECK-ERRORS: ^
[ARM] Make the assembler reject unpredictable pre/post-indexed ARM LDRH/LDRSH instructions. The ARM ARM prohibits LDRH/LDRSH instructions with writeback into the source register. With this commit this constraint is now enforced and we stop assembling LDRH/LDRSH instructions with unpredictable behavior. llvm-svn: 214499
2014-08-01 19:33:47 +08:00
@ CHECK-ERRORS: error: destination register and base register can't be identical
@ CHECK-ERRORS: ldrh r0, [r0, #2]!
@ CHECK-ERRORS: ^
@ CHECK-ERRORS: error: destination register and base register can't be identical
@ CHECK-ERRORS: ldrh r0, [r0, r1]!
@ CHECK-ERRORS: ^
@ CHECK-ERRORS: error: destination register and base register can't be identical
@ CHECK-ERRORS: ldrh r0, [r0], #2
@ CHECK-ERRORS: ^
@ CHECK-ERRORS: error: destination register and base register can't be identical
@ CHECK-ERRORS: ldrh r0, [r0], r1
@ CHECK-ERRORS: ^
@ CHECK-ERRORS: error: destination register and base register can't be identical
@ CHECK-ERRORS: ldrsh r0, [r0, #2]!
@ CHECK-ERRORS: ^
@ CHECK-ERRORS: error: destination register and base register can't be identical
@ CHECK-ERRORS: ldrsh r0, [r0, r1]!
@ CHECK-ERRORS: ^
@ CHECK-ERRORS: error: destination register and base register can't be identical
@ CHECK-ERRORS: ldrsh r0, [r0], #2
@ CHECK-ERRORS: ^
@ CHECK-ERRORS: error: destination register and base register can't be identical
@ CHECK-ERRORS: ldrsh r0, [r0], r1
@ CHECK-ERRORS: ^
[ARM] Make the assembler reject unpredictable pre/post-indexed ARM LDRB/LDRSB instructions. The ARM ARM prohibits LDRB/LDRSB instructions with writeback into the destination register. With this commit this constraint is now enforced and we stop assembling LDRH/LDRSH instructions with unpredictable behavior. llvm-svn: 214500
2014-08-01 20:08:04 +08:00
@ CHECK-ERRORS: error: destination register and base register can't be identical
@ CHECK-ERRORS: ldrb r0, [r0, #1]!
@ CHECK-ERRORS: ^
@ CHECK-ERRORS: error: destination register and base register can't be identical
@ CHECK-ERRORS: ldrb r0, [r0, r1]!
@ CHECK-ERRORS: ^
@ CHECK-ERRORS: error: destination register and base register can't be identical
@ CHECK-ERRORS: ldrb r0, [r0], #1
@ CHECK-ERRORS: ^
@ CHECK-ERRORS: error: destination register and base register can't be identical
@ CHECK-ERRORS: ldrb r0, [r0], r1
@ CHECK-ERRORS: ^
@ CHECK-ERRORS: error: destination register and base register can't be identical
@ CHECK-ERRORS: ldrsb r0, [r0, #1]!
@ CHECK-ERRORS: ^
@ CHECK-ERRORS: error: destination register and base register can't be identical
@ CHECK-ERRORS: ldrsb r0, [r0, r1]!
@ CHECK-ERRORS: ^
@ CHECK-ERRORS: error: destination register and base register can't be identical
@ CHECK-ERRORS: ldrsb r0, [r0], #1
@ CHECK-ERRORS: ^
@ CHECK-ERRORS: error: destination register and base register can't be identical
@ CHECK-ERRORS: ldrsb r0, [r0], r1
@ CHECK-ERRORS: ^
Add support for ARM modified-immediate assembly syntax. Certain ARM instructions accept 32-bit immediate operands encoded as a 8-bit integer value (0-255) and a 4-bit rotation (0-30, even). Current ARM assembly syntax support in LLVM allows the decoded (32-bit) immediate to be specified as a single immediate operand for such instructions: mov r0, #4278190080 The ARMARM defines an extended assembly syntax allowing the encoding to be made more explicit, as in: mov r0, #255, #8 ; (same 32-bit value as above) The behaviour of the two instructions can be different w.r.t flags, which is documented under "Modified immediate constants" in ARMARM. This patch enables support for this extended syntax at the MC layer. llvm-svn: 223113
2014-12-02 18:53:20 +08:00
@ Out of range modified immediate values
mov r5, #-256, #6
mov r6, #42, #7
mvn r5, #256, #6
mvn r6, #42, #298
cmp r5, #65535, #6
cmp r6, #42, #31
cmn r5, #-1, #6
cmn r6, #42, #32
msr APSR_nzcvq, #-128, #2
msr apsr_nzcvqg, #0, #1
adc r7, r8, #-256, #2
adc r7, r8, #128, #1
sbc r7, r8, #-256, #2
sbc r7, r8, #128, #1
add r7, r8, #-2149, #0
add r7, r8, #100, #1
sub r7, r8, #-2149, #0
sub r7, r8, #100, #1
and r7, r8, #-2149, #0
and r7, r8, #100, #1
orr r7, r8, #-2149, #0
orr r7, r8, #100, #1
eor r7, r8, #-2149, #0
eor r7, r8, #100, #1
bic r7, r8, #-2149, #0
bic r7, r8, #100, #1
rsb r7, r8, #-2149, #0
rsb r7, r8, #100, #1
adds r7, r8, #-2149, #0
adds r7, r8, #100, #1
subs r7, r8, #-2149, #0
subs r7, r8, #100, #1
rsbs r7, r8, #-2149, #0
rsbs r7, r8, #100, #1
rsc r7, r8, #-2149, #0
rsc r7, r8, #100, #1
TST r7, #-2149, #0
TST r7, #100, #1
TEQ r7, #-2149, #0
TEQ r7, #100, #1
@ CHECK-ERRORS: error: immediate operand must a number in the range [0, 255]
@ CHECK-ERRORS: error: immediate operand must an even number in the range [0, 30]
@ CHECK-ERRORS: error: immediate operand must a number in the range [0, 255]
@ CHECK-ERRORS: error: immediate operand must an even number in the range [0, 30]
@ CHECK-ERRORS: error: immediate operand must a number in the range [0, 255]
@ CHECK-ERRORS: error: immediate operand must an even number in the range [0, 30]
@ CHECK-ERRORS: error: immediate operand must a number in the range [0, 255]
@ CHECK-ERRORS: error: immediate operand must an even number in the range [0, 30]
@ CHECK-ERRORS: error: immediate operand must a number in the range [0, 255]
@ CHECK-ERRORS: error: immediate operand must an even number in the range [0, 30]
@ CHECK-ERRORS: error: immediate operand must a number in the range [0, 255]
@ CHECK-ERRORS: error: immediate operand must an even number in the range [0, 30]
@ CHECK-ERRORS: error: immediate operand must a number in the range [0, 255]
@ CHECK-ERRORS: error: immediate operand must an even number in the range [0, 30]
@ CHECK-ERRORS: error: immediate operand must a number in the range [0, 255]
@ CHECK-ERRORS: error: immediate operand must an even number in the range [0, 30]
@ CHECK-ERRORS: error: immediate operand must a number in the range [0, 255]
@ CHECK-ERRORS: error: immediate operand must an even number in the range [0, 30]
@ CHECK-ERRORS: error: immediate operand must a number in the range [0, 255]
@ CHECK-ERRORS: error: immediate operand must an even number in the range [0, 30]
@ CHECK-ERRORS: error: immediate operand must a number in the range [0, 255]
@ CHECK-ERRORS: error: immediate operand must an even number in the range [0, 30]
@ CHECK-ERRORS: error: immediate operand must a number in the range [0, 255]
@ CHECK-ERRORS: error: immediate operand must an even number in the range [0, 30]
@ CHECK-ERRORS: error: immediate operand must a number in the range [0, 255]
@ CHECK-ERRORS: error: immediate operand must an even number in the range [0, 30]
@ CHECK-ERRORS: error: immediate operand must a number in the range [0, 255]
@ CHECK-ERRORS: error: immediate operand must an even number in the range [0, 30]
@ CHECK-ERRORS: error: immediate operand must a number in the range [0, 255]
@ CHECK-ERRORS: error: immediate operand must an even number in the range [0, 30]
@ CHECK-ERRORS: error: immediate operand must a number in the range [0, 255]
@ CHECK-ERRORS: error: immediate operand must an even number in the range [0, 30]
@ CHECK-ERRORS: error: immediate operand must a number in the range [0, 255]
@ CHECK-ERRORS: error: immediate operand must an even number in the range [0, 30]
@ CHECK-ERRORS: error: immediate operand must a number in the range [0, 255]
@ CHECK-ERRORS: error: immediate operand must an even number in the range [0, 30]
@ CHECK-ERRORS: error: immediate operand must a number in the range [0, 255]
@ CHECK-ERRORS: error: immediate operand must an even number in the range [0, 30]