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llvm-project/llvm/test/MC/AArch64/neon-scalar-abs.s

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[AArch64] Add ARMv8.2-A FP16 vector instructions ARMv8.2-A adds 16-bit floating point versions of all existing SIMD floating-point instructions. This is an optional extension, so all of these instructions require the FeatureFullFP16 subtarget feature. Note that VFP without SIMD is not a valid combination for any version of ARMv8-A, but I have ensured that these instructions all depend on both FeatureNEON and FeatureFullFP16 for consistency. The ".2h" vector type specifier is now legal (for the scalar pairwise reduction instructions), so some unrelated tests have been modified as different error messages are emitted. This is not a problem as the invalid operands are still caught. llvm-svn: 255010
2015-12-08 20:16:10 +08:00
// RUN: llvm-mc -triple aarch64-none-linux-gnu -mattr=+neon,+fullfp16 -show-encoding < %s | FileCheck %s
[AArch64] Add support for NEON scalar signed saturating absolute value and scalar signed saturating negate instructions. llvm-svn: 192733
2013-10-16 05:18:44 +08:00
// Check that the assembler can handle the documented syntax for AArch64
//----------------------------------------------------------------------
// Scalar Absolute Value
[AArch64] Add support for NEON scalar absolute value instruction. llvm-svn: 192842
2013-10-17 05:04:34 +08:00
//----------------------------------------------------------------------
abs d29, d24
// CHECK: abs d29, d24 // encoding: [0x1d,0xbb,0xe0,0x5e]
[AArch64] Add support for NEON scalar floating-point absolute difference. llvm-svn: 195803
2013-11-27 09:45:58 +08:00
//----------------------------------------------------------------------
// Scalar Floating-point Absolute Difference
//----------------------------------------------------------------------
[AArch64] Add ARMv8.2-A FP16 vector instructions ARMv8.2-A adds 16-bit floating point versions of all existing SIMD floating-point instructions. This is an optional extension, so all of these instructions require the FeatureFullFP16 subtarget feature. Note that VFP without SIMD is not a valid combination for any version of ARMv8-A, but I have ensured that these instructions all depend on both FeatureNEON and FeatureFullFP16 for consistency. The ".2h" vector type specifier is now legal (for the scalar pairwise reduction instructions), so some unrelated tests have been modified as different error messages are emitted. This is not a problem as the invalid operands are still caught. llvm-svn: 255010
2015-12-08 20:16:10 +08:00
fabd h29, h24, h20
[AArch64] Add support for NEON scalar floating-point absolute difference. llvm-svn: 195803
2013-11-27 09:45:58 +08:00
fabd s29, s24, s20
fabd d29, d24, d20
[AArch64] Add ARMv8.2-A FP16 vector instructions ARMv8.2-A adds 16-bit floating point versions of all existing SIMD floating-point instructions. This is an optional extension, so all of these instructions require the FeatureFullFP16 subtarget feature. Note that VFP without SIMD is not a valid combination for any version of ARMv8-A, but I have ensured that these instructions all depend on both FeatureNEON and FeatureFullFP16 for consistency. The ".2h" vector type specifier is now legal (for the scalar pairwise reduction instructions), so some unrelated tests have been modified as different error messages are emitted. This is not a problem as the invalid operands are still caught. llvm-svn: 255010
2015-12-08 20:16:10 +08:00
// CHECK: fabd h29, h24, h20 // encoding: [0x1d,0x17,0xd4,0x7e]
[AArch64] Add support for NEON scalar floating-point absolute difference. llvm-svn: 195803
2013-11-27 09:45:58 +08:00
// CHECK: fabd s29, s24, s20 // encoding: [0x1d,0xd7,0xb4,0x7e]
// CHECK: fabd d29, d24, d20 // encoding: [0x1d,0xd7,0xf4,0x7e]
[AArch64] Add support for NEON scalar absolute value instruction. llvm-svn: 192842
2013-10-17 05:04:34 +08:00
//----------------------------------------------------------------------
// Scalar Signed Saturating Absolute Value
[AArch64] Add support for NEON scalar signed saturating absolute value and scalar signed saturating negate instructions. llvm-svn: 192733
2013-10-16 05:18:44 +08:00
//----------------------------------------------------------------------
sqabs b19, b14
sqabs h21, h15
sqabs s20, s12
sqabs d18, d12
// CHECK: sqabs b19, b14 // encoding: [0xd3,0x79,0x20,0x5e]
// CHECK: sqabs h21, h15 // encoding: [0xf5,0x79,0x60,0x5e]
// CHECK: sqabs s20, s12 // encoding: [0x94,0x79,0xa0,0x5e]
// CHECK: sqabs d18, d12 // encoding: [0x92,0x79,0xe0,0x5e]