2016-03-05 12:36:13 +08:00
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; RUN: llc -march=amdgcn -verify-machineinstrs -o /dev/null < %s
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2017-01-25 06:02:15 +08:00
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; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs -o /dev/null < %s
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2016-02-23 07:45:42 +08:00
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; The register coalescer introduces a verifier error which later
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; results in a crash during scheduling.
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declare i32 @llvm.amdgcn.workitem.id.x() #0
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2017-03-22 05:39:51 +08:00
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define amdgpu_kernel void @reg_coalescer_breaks_dead(<2 x i32> addrspace(1)* nocapture readonly %arg, i32 %arg1, i32 %arg2, i32 %arg3) #1 {
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2016-02-23 07:45:42 +08:00
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bb:
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%id.x = call i32 @llvm.amdgcn.workitem.id.x()
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%cmp0 = icmp eq i32 %id.x, 0
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br i1 %cmp0, label %bb3, label %bb4
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bb3: ; preds = %bb
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%tmp = ashr exact i32 undef, 8
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br label %bb6
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bb4: ; preds = %bb6, %bb
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%tmp5 = phi <2 x i32> [ zeroinitializer, %bb ], [ %tmp13, %bb6 ]
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br i1 undef, label %bb15, label %bb16
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bb6: ; preds = %bb6, %bb3
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%tmp7 = phi <2 x i32> [ zeroinitializer, %bb3 ], [ %tmp13, %bb6 ]
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%tmp8 = add nsw i32 0, %arg1
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%tmp9 = add nsw i32 %tmp8, 0
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%tmp10 = sext i32 %tmp9 to i64
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%tmp11 = getelementptr inbounds <2 x i32>, <2 x i32> addrspace(1)* %arg, i64 %tmp10
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%tmp12 = load <2 x i32>, <2 x i32> addrspace(1)* %tmp11, align 8
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%tmp13 = add <2 x i32> %tmp12, %tmp7
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%tmp14 = icmp slt i32 undef, %arg2
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br i1 %tmp14, label %bb6, label %bb4
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bb15: ; preds = %bb4
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store <2 x i32> %tmp5, <2 x i32> addrspace(3)* undef, align 8
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br label %bb16
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bb16: ; preds = %bb15, %bb4
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unreachable
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}
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attributes #0 = { nounwind readnone }
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attributes #1 = { nounwind }
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