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llvm-project/llvm/test/CodeGen/SystemZ/vec-cmp-03.ll

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[SystemZ] Add CodeGen support for integer vector types This the first of a series of patches to add CodeGen support exploiting the instructions of the z13 vector facility. This patch adds support for the native integer vector types (v16i8, v8i16, v4i32, v2i64). When the vector facility is present, we default to the new vector ABI. This is characterized by two major differences: - Vector types are passed/returned in vector registers (except for unnamed arguments of a variable-argument list function). - Vector types are at most 8-byte aligned. The reason for the choice of 8-byte vector alignment is that the hardware is able to efficiently load vectors at 8-byte alignment, and the ABI only guarantees 8-byte alignment of the stack pointer, so requiring any higher alignment for vectors would require dynamic stack re-alignment code. However, for compatibility with old code that may use vector types, when *not* using the vector facility, the old alignment rules (vector types are naturally aligned) remain in use. These alignment rules are not only implemented at the C language level (implemented in clang), but also at the LLVM IR level. This is done by selecting a different DataLayout string depending on whether the vector ABI is in effect or not. Based on a patch by Richard Sandiford. llvm-svn: 236521
2015-05-06 03:25:42 +08:00
; Test v4i32 comparisons.
;
; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s
; Test eq.
define <4 x i32> @f1(<4 x i32> %dummy, <4 x i32> %val1, <4 x i32> %val2) {
; CHECK-LABEL: f1:
; CHECK: vceqf %v24, %v26, %v28
; CHECK-NEXT: br %r14
%cmp = icmp eq <4 x i32> %val1, %val2
%ret = sext <4 x i1> %cmp to <4 x i32>
ret <4 x i32> %ret
}
; Test ne.
define <4 x i32> @f2(<4 x i32> %dummy, <4 x i32> %val1, <4 x i32> %val2) {
; CHECK-LABEL: f2:
; CHECK: vceqf [[REG:%v[0-9]+]], %v26, %v28
; CHECK-NEXT: vno %v24, [[REG]], [[REG]]
; CHECK-NEXT: br %r14
%cmp = icmp ne <4 x i32> %val1, %val2
%ret = sext <4 x i1> %cmp to <4 x i32>
ret <4 x i32> %ret
}
; Test sgt.
define <4 x i32> @f3(<4 x i32> %dummy, <4 x i32> %val1, <4 x i32> %val2) {
; CHECK-LABEL: f3:
; CHECK: vchf %v24, %v26, %v28
; CHECK-NEXT: br %r14
%cmp = icmp sgt <4 x i32> %val1, %val2
%ret = sext <4 x i1> %cmp to <4 x i32>
ret <4 x i32> %ret
}
; Test sge.
define <4 x i32> @f4(<4 x i32> %dummy, <4 x i32> %val1, <4 x i32> %val2) {
; CHECK-LABEL: f4:
; CHECK: vchf [[REG:%v[0-9]+]], %v28, %v26
; CHECK-NEXT: vno %v24, [[REG]], [[REG]]
; CHECK-NEXT: br %r14
%cmp = icmp sge <4 x i32> %val1, %val2
%ret = sext <4 x i1> %cmp to <4 x i32>
ret <4 x i32> %ret
}
; Test sle.
define <4 x i32> @f5(<4 x i32> %dummy, <4 x i32> %val1, <4 x i32> %val2) {
; CHECK-LABEL: f5:
; CHECK: vchf [[REG:%v[0-9]+]], %v26, %v28
; CHECK-NEXT: vno %v24, [[REG]], [[REG]]
; CHECK-NEXT: br %r14
%cmp = icmp sle <4 x i32> %val1, %val2
%ret = sext <4 x i1> %cmp to <4 x i32>
ret <4 x i32> %ret
}
; Test slt.
define <4 x i32> @f6(<4 x i32> %dummy, <4 x i32> %val1, <4 x i32> %val2) {
; CHECK-LABEL: f6:
; CHECK: vchf %v24, %v28, %v26
; CHECK-NEXT: br %r14
%cmp = icmp slt <4 x i32> %val1, %val2
%ret = sext <4 x i1> %cmp to <4 x i32>
ret <4 x i32> %ret
}
; Test ugt.
define <4 x i32> @f7(<4 x i32> %dummy, <4 x i32> %val1, <4 x i32> %val2) {
; CHECK-LABEL: f7:
; CHECK: vchlf %v24, %v26, %v28
; CHECK-NEXT: br %r14
%cmp = icmp ugt <4 x i32> %val1, %val2
%ret = sext <4 x i1> %cmp to <4 x i32>
ret <4 x i32> %ret
}
; Test uge.
define <4 x i32> @f8(<4 x i32> %dummy, <4 x i32> %val1, <4 x i32> %val2) {
; CHECK-LABEL: f8:
; CHECK: vchlf [[REG:%v[0-9]+]], %v28, %v26
; CHECK-NEXT: vno %v24, [[REG]], [[REG]]
; CHECK-NEXT: br %r14
%cmp = icmp uge <4 x i32> %val1, %val2
%ret = sext <4 x i1> %cmp to <4 x i32>
ret <4 x i32> %ret
}
; Test ule.
define <4 x i32> @f9(<4 x i32> %dummy, <4 x i32> %val1, <4 x i32> %val2) {
; CHECK-LABEL: f9:
; CHECK: vchlf [[REG:%v[0-9]+]], %v26, %v28
; CHECK-NEXT: vno %v24, [[REG]], [[REG]]
; CHECK-NEXT: br %r14
%cmp = icmp ule <4 x i32> %val1, %val2
%ret = sext <4 x i1> %cmp to <4 x i32>
ret <4 x i32> %ret
}
; Test ult.
define <4 x i32> @f10(<4 x i32> %dummy, <4 x i32> %val1, <4 x i32> %val2) {
; CHECK-LABEL: f10:
; CHECK: vchlf %v24, %v28, %v26
; CHECK-NEXT: br %r14
%cmp = icmp ult <4 x i32> %val1, %val2
%ret = sext <4 x i1> %cmp to <4 x i32>
ret <4 x i32> %ret
}
; Test eq selects.
define <4 x i32> @f11(<4 x i32> %val1, <4 x i32> %val2,
<4 x i32> %val3, <4 x i32> %val4) {
; CHECK-LABEL: f11:
; CHECK: vceqf [[REG:%v[0-9]+]], %v24, %v26
; CHECK-NEXT: vsel %v24, %v28, %v30, [[REG]]
; CHECK-NEXT: br %r14
%cmp = icmp eq <4 x i32> %val1, %val2
%ret = select <4 x i1> %cmp, <4 x i32> %val3, <4 x i32> %val4
ret <4 x i32> %ret
}
; Test ne selects.
define <4 x i32> @f12(<4 x i32> %val1, <4 x i32> %val2,
<4 x i32> %val3, <4 x i32> %val4) {
; CHECK-LABEL: f12:
; CHECK: vceqf [[REG:%v[0-9]+]], %v24, %v26
; CHECK-NEXT: vsel %v24, %v30, %v28, [[REG]]
; CHECK-NEXT: br %r14
%cmp = icmp ne <4 x i32> %val1, %val2
%ret = select <4 x i1> %cmp, <4 x i32> %val3, <4 x i32> %val4
ret <4 x i32> %ret
}
; Test sgt selects.
define <4 x i32> @f13(<4 x i32> %val1, <4 x i32> %val2,
<4 x i32> %val3, <4 x i32> %val4) {
; CHECK-LABEL: f13:
; CHECK: vchf [[REG:%v[0-9]+]], %v24, %v26
; CHECK-NEXT: vsel %v24, %v28, %v30, [[REG]]
; CHECK-NEXT: br %r14
%cmp = icmp sgt <4 x i32> %val1, %val2
%ret = select <4 x i1> %cmp, <4 x i32> %val3, <4 x i32> %val4
ret <4 x i32> %ret
}
; Test sge selects.
define <4 x i32> @f14(<4 x i32> %val1, <4 x i32> %val2,
<4 x i32> %val3, <4 x i32> %val4) {
; CHECK-LABEL: f14:
; CHECK: vchf [[REG:%v[0-9]+]], %v26, %v24
; CHECK-NEXT: vsel %v24, %v30, %v28, [[REG]]
; CHECK-NEXT: br %r14
%cmp = icmp sge <4 x i32> %val1, %val2
%ret = select <4 x i1> %cmp, <4 x i32> %val3, <4 x i32> %val4
ret <4 x i32> %ret
}
; Test sle selects.
define <4 x i32> @f15(<4 x i32> %val1, <4 x i32> %val2,
<4 x i32> %val3, <4 x i32> %val4) {
; CHECK-LABEL: f15:
; CHECK: vchf [[REG:%v[0-9]+]], %v24, %v26
; CHECK-NEXT: vsel %v24, %v30, %v28, [[REG]]
; CHECK-NEXT: br %r14
%cmp = icmp sle <4 x i32> %val1, %val2
%ret = select <4 x i1> %cmp, <4 x i32> %val3, <4 x i32> %val4
ret <4 x i32> %ret
}
; Test slt selects.
define <4 x i32> @f16(<4 x i32> %val1, <4 x i32> %val2,
<4 x i32> %val3, <4 x i32> %val4) {
; CHECK-LABEL: f16:
; CHECK: vchf [[REG:%v[0-9]+]], %v26, %v24
; CHECK-NEXT: vsel %v24, %v28, %v30, [[REG]]
; CHECK-NEXT: br %r14
%cmp = icmp slt <4 x i32> %val1, %val2
%ret = select <4 x i1> %cmp, <4 x i32> %val3, <4 x i32> %val4
ret <4 x i32> %ret
}
; Test ugt selects.
define <4 x i32> @f17(<4 x i32> %val1, <4 x i32> %val2,
<4 x i32> %val3, <4 x i32> %val4) {
; CHECK-LABEL: f17:
; CHECK: vchlf [[REG:%v[0-9]+]], %v24, %v26
; CHECK-NEXT: vsel %v24, %v28, %v30, [[REG]]
; CHECK-NEXT: br %r14
%cmp = icmp ugt <4 x i32> %val1, %val2
%ret = select <4 x i1> %cmp, <4 x i32> %val3, <4 x i32> %val4
ret <4 x i32> %ret
}
; Test uge selects.
define <4 x i32> @f18(<4 x i32> %val1, <4 x i32> %val2,
<4 x i32> %val3, <4 x i32> %val4) {
; CHECK-LABEL: f18:
; CHECK: vchlf [[REG:%v[0-9]+]], %v26, %v24
; CHECK-NEXT: vsel %v24, %v30, %v28, [[REG]]
; CHECK-NEXT: br %r14
%cmp = icmp uge <4 x i32> %val1, %val2
%ret = select <4 x i1> %cmp, <4 x i32> %val3, <4 x i32> %val4
ret <4 x i32> %ret
}
; Test ule selects.
define <4 x i32> @f19(<4 x i32> %val1, <4 x i32> %val2,
<4 x i32> %val3, <4 x i32> %val4) {
; CHECK-LABEL: f19:
; CHECK: vchlf [[REG:%v[0-9]+]], %v24, %v26
; CHECK-NEXT: vsel %v24, %v30, %v28, [[REG]]
; CHECK-NEXT: br %r14
%cmp = icmp ule <4 x i32> %val1, %val2
%ret = select <4 x i1> %cmp, <4 x i32> %val3, <4 x i32> %val4
ret <4 x i32> %ret
}
; Test ult selects.
define <4 x i32> @f20(<4 x i32> %val1, <4 x i32> %val2,
<4 x i32> %val3, <4 x i32> %val4) {
; CHECK-LABEL: f20:
; CHECK: vchlf [[REG:%v[0-9]+]], %v26, %v24
; CHECK-NEXT: vsel %v24, %v28, %v30, [[REG]]
; CHECK-NEXT: br %r14
%cmp = icmp ult <4 x i32> %val1, %val2
%ret = select <4 x i1> %cmp, <4 x i32> %val3, <4 x i32> %val4
ret <4 x i32> %ret
}