[AMDGPU] Fix SGPR fixing through SCC chaining
Summary:
- During the fixing of SGPR copying from VGPR, ensure users of SCC is
properly propagated, i.e.
* only propagate through live def of SCC,
* skip the SCC-def inst itself, and
* stop the propagation on the other SCC-def inst after checking its
SCC-use first.
Subscribers: arsenm, kzhuravl, jvesely, wdng, nhaehnle, yaxunl, dstuttard, tpr, t-tye, hiraditya, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D59362
llvm-svn: 356258
2019-03-15 20:42:21 +08:00
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# RUN: llc -march=amdgcn -run-pass=si-fix-sgpr-copies -o - %s | FileCheck --check-prefix=GCN %s
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# GCN-LABEL: name: fix-sgpr-copies
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# GCN: V_ADD_I32_e32
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# GCN: V_ADDC_U32_e32
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---
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name: fix-sgpr-copies
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body: |
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bb.0:
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%0:vgpr_32 = IMPLICIT_DEF
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%1:sreg_32 = IMPLICIT_DEF
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%2:sreg_32 = IMPLICIT_DEF
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%3:sreg_32 = IMPLICIT_DEF
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%4:vgpr_32 = V_CVT_U32_F32_e64 0, %0:vgpr_32, 0, 0, implicit $exec
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%5:sreg_32 = COPY %4:vgpr_32
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%6:sreg_32 = S_ADD_I32 %2:sreg_32, %5:sreg_32, implicit-def $scc
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%7:sreg_32 = S_ADDC_U32 %3:sreg_32, %1:sreg_32, implicit-def $scc, implicit $scc
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...
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[AMDGPU] Fix the mis-handling of `vreg_1` copied from scalar register.
Summary:
- Don't treat the use of a scalar register as `vreg_1` an VGPR usage.
Otherwise, that promotes that scalar register into vector one, which
breaks the assumption that scalar register holds the lane mask.
- The issue is triggered in a complicated case, where if the uses of
that (lane mask) scalar register is legalized firstly before its
definition, e.g., due to the mismatch block placement and its
topological order or loop. In that cases, the legalization of PHI
introduces the use of that scalar register as `vreg_1`.
Reviewers: rampitec, nhaehnle, arsenm, alex-t
Subscribers: kzhuravl, jvesely, wdng, dstuttard, tpr, t-tye, hiraditya, llvm-commits, yaxunl
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D62492
llvm-svn: 361847
2019-05-29 00:29:39 +08:00
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# Test to ensure i1 phi copies from scalar registers through another phi won't
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# be promoted into vector ones.
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# GCN-LABEL: name: fix-sgpr-i1-phi-copies
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# GCN: .8:
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# GCN-NOT: vreg_64 = PHI
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---
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name: fix-sgpr-i1-phi-copies
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tracksRegLiveness: true
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body: |
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bb.9:
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S_BRANCH %bb.0
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bb.4:
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S_CBRANCH_SCC1 %bb.6, implicit undef $scc
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bb.5:
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%3:vreg_1 = IMPLICIT_DEF
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bb.6:
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%4:vreg_1 = PHI %2:sreg_64, %bb.4, %3:vreg_1, %bb.5
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bb.7:
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%5:vreg_1 = PHI %2:sreg_64, %bb.3, %4:vreg_1, %bb.6
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S_BRANCH %bb.8
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bb.0:
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S_CBRANCH_SCC1 %bb.2, implicit undef $scc
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bb.1:
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%0:sreg_64 = S_MOV_B64 0
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S_BRANCH %bb.3
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bb.2:
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%1:sreg_64 = S_MOV_B64 -1
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S_BRANCH %bb.3
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bb.3:
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%2:sreg_64 = PHI %0:sreg_64, %bb.1, %1:sreg_64, %bb.2
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S_CBRANCH_SCC1 %bb.7, implicit undef $scc
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S_BRANCH %bb.4
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bb.8:
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...
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