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llvm-project/llvm/test/CodeGen/AMDGPU/waitcnt-debug.mir

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[AMDGPU] Waitcnt pass: add debug options - Add "amdgpu-waitcnt-forcezero" to force all waitcnt instrs to be emitted as s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) - Add debug counters to control force emit of s_waitcnt instrs; debug counters: si-insert-waitcnts-forceexp: force emit s_waitcnt expcnt(0) instrs si-insert-waitcnts-forcevm: force emit s_waitcnt lgkmcnt(0) instrs si-insert-waitcnts-forcelgkm: force emit s_waitcnt vmcnt(0) instrs - Add some debug statements Note that a variant of this patch was previously committed/reverted. Differential Revision: https://reviews.llvm.org/D45888 llvm-svn: 330862
2018-04-26 03:21:26 +08:00
# REQUIRES: asserts
# RUN: llc -mtriple=amdgcn -verify-machineinstrs -run-pass si-insert-waitcnts -debug-counter=si-insert-waitcnts-forcelgkm-count=1 -o - %s | FileCheck -check-prefixes=GCN,LGKM %s
# RUN: llc -mtriple=amdgcn -verify-machineinstrs -run-pass si-insert-waitcnts -debug-counter=si-insert-waitcnts-forceexp-count=2 -o - %s | FileCheck -check-prefixes=GCN,EXP %s
# RUN: llc -mtriple=amdgcn -verify-machineinstrs -run-pass si-insert-waitcnts -debug-counter=si-insert-waitcnts-forcevm-count=3 -o - %s | FileCheck -check-prefixes=GCN,VM %s
# RUN: llc -mtriple=amdgcn -verify-machineinstrs -run-pass si-insert-waitcnts -amdgpu-waitcnt-forcezero=1 -debug-counter=si-insert-waitcnts-forcevm-count=2 -o - %s | FileCheck -check-prefixes=GCN,ZERO %s
# check that the waitcnt pass options that force insertion of waitcnt instructions are working as expected
...
# GCN-LABEL: name: waitcnt-debug
# LGKM: S_WAITCNT 127
# LGKM-NEXT: S_NOP 0
# LGKM-NEXT: S_NOP 0
# EXP: S_WAITCNT 3855
# EXP-NEXT: S_NOP 0
# EXP-NEXT: S_WAITCNT 3855
# EXP-NEXT: S_NOP 0
# VM: S_WAITCNT 3952
# VM-NEXT: S_NOP 0
# VM-NEXT: S_WAITCNT 3952
# VM-NEXT: S_NOP 0
# VM-NEXT: S_WAITCNT 3952
# VM-NEXT: S_NOP 0
# ZERO: S_WAITCNT 0
# ZERO-NEXT: S_WAITCNT 0
# ZERO-NEXT: S_NOP 0
# ZERO-NEXT: S_WAITCNT 0
# ZERO-NEXT: S_NOP 0
name: waitcnt-debug
liveins:
body: |
bb.0:
S_NOP 0
S_NOP 0
S_NOP 0
S_NOP 0
...