2011-04-16 05:51:11 +08:00
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//===-- MipsISelLowering.h - Mips DAG Lowering Interface --------*- C++ -*-===//
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2007-06-06 15:42:06 +08:00
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//
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// The LLVM Compiler Infrastructure
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//
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2007-12-30 04:36:04 +08:00
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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2007-06-06 15:42:06 +08:00
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//
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2011-04-16 05:51:11 +08:00
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//===----------------------------------------------------------------------===//
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2007-06-06 15:42:06 +08:00
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//
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// This file defines the interfaces that Mips uses to lower LLVM code into a
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// selection DAG.
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//
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2011-04-16 05:51:11 +08:00
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//===----------------------------------------------------------------------===//
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2007-06-06 15:42:06 +08:00
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#ifndef MipsISELLOWERING_H
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#define MipsISELLOWERING_H
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#include "Mips.h"
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#include "MipsSubtarget.h"
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2012-03-18 02:46:09 +08:00
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#include "llvm/CodeGen/SelectionDAG.h"
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#include "llvm/Target/TargetLowering.h"
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2007-06-06 15:42:06 +08:00
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namespace llvm {
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namespace MipsISD {
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enum NodeType {
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// Start the numbering from where ISD NodeType finishes.
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2008-09-24 02:42:32 +08:00
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FIRST_NUMBER = ISD::BUILTIN_OP_END,
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2007-06-06 15:42:06 +08:00
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// Jump and link (call)
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JmpLink,
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// Get the Higher 16 bits from a 32-bit immediate
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// No relation with Mips Hi register
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2011-03-05 01:51:39 +08:00
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Hi,
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2007-06-06 15:42:06 +08:00
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// Get the Lower 16 bits from a 32-bit immediate
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// No relation with Mips Lo register
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2011-03-05 01:51:39 +08:00
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Lo,
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2007-06-06 15:42:06 +08:00
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2008-07-22 02:52:34 +08:00
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// Handle gp_rel (small data/bss sections) relocation.
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GPRel,
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2011-05-31 10:53:58 +08:00
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// Thread Pointer
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ThreadPointer,
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2008-07-09 12:45:36 +08:00
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// Floating Point Branch Conditional
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Several changes to Mips backend, experimental fp support being the most
important.
- Cleanup in the Subtarget info with addition of new features, not all support
yet, but they allow the future inclusion of features easier. Among new features,
we have : Arch family info (mips1, mips2, ...), ABI info (o32, eabi), 64-bit
integer
and float registers, allegrex vector FPU (VFPU), single float only support.
- TargetMachine now detects allegrex core.
- Added allegrex (Mips32r2) sext_inreg instructions.
- *Added Float Point Instructions*, handling single float only, and
aliased accesses for 32-bit FPUs.
- Some cleanup in FP instruction formats and FP register classes.
- Calling conventions improved to support mips 32-bit EABI.
- Added Asm Printer support for fp cond codes.
- Added support for sret copy to a return register.
- EABI support added into LowerCALL and FORMAL_ARGS.
- MipsFunctionInfo now keeps a virtual register per function to track the
sret on function entry until function ret.
- MipsInstrInfo FP support into methods (isMoveInstr, isLoadFromStackSlot, ...),
FP cond codes mapping and initial FP Branch Analysis.
- Two new Mips SDNode to handle fp branch and compare instructions : FPBrcond,
FPCmp
- MipsTargetLowering : handling different FP classes, Allegrex support, sret
return copy, no homing location within EABI, non 32-bit stack objects
arguments, and asm constraint for float.
llvm-svn: 53146
2008-07-06 03:05:21 +08:00
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FPBrcond,
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2008-07-09 12:45:36 +08:00
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// Floating Point Compare
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Several changes to Mips backend, experimental fp support being the most
important.
- Cleanup in the Subtarget info with addition of new features, not all support
yet, but they allow the future inclusion of features easier. Among new features,
we have : Arch family info (mips1, mips2, ...), ABI info (o32, eabi), 64-bit
integer
and float registers, allegrex vector FPU (VFPU), single float only support.
- TargetMachine now detects allegrex core.
- Added allegrex (Mips32r2) sext_inreg instructions.
- *Added Float Point Instructions*, handling single float only, and
aliased accesses for 32-bit FPUs.
- Some cleanup in FP instruction formats and FP register classes.
- Calling conventions improved to support mips 32-bit EABI.
- Added Asm Printer support for fp cond codes.
- Added support for sret copy to a return register.
- EABI support added into LowerCALL and FORMAL_ARGS.
- MipsFunctionInfo now keeps a virtual register per function to track the
sret on function entry until function ret.
- MipsInstrInfo FP support into methods (isMoveInstr, isLoadFromStackSlot, ...),
FP cond codes mapping and initial FP Branch Analysis.
- Two new Mips SDNode to handle fp branch and compare instructions : FPBrcond,
FPCmp
- MipsTargetLowering : handling different FP classes, Allegrex support, sret
return copy, no homing location within EABI, non 32-bit stack objects
arguments, and asm constraint for float.
llvm-svn: 53146
2008-07-06 03:05:21 +08:00
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FPCmp,
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2011-04-01 02:26:17 +08:00
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// Floating Point Conditional Moves
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CMovFP_T,
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CMovFP_F,
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2009-05-28 01:23:44 +08:00
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// Floating Point Rounding
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FPRound,
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2011-03-05 01:51:39 +08:00
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// Return
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2011-01-19 03:29:17 +08:00
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Ret,
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// MAdd/Sub nodes
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MAdd,
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MAddu,
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MSub,
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2011-03-05 05:03:24 +08:00
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MSubu,
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// DivRem(u)
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DivRem,
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2011-04-16 03:52:08 +08:00
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DivRemU,
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BuildPairF64,
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2011-05-28 09:07:07 +08:00
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ExtractElementF64,
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2011-12-09 09:53:17 +08:00
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Wrapper,
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2011-06-21 08:40:49 +08:00
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2011-07-20 07:30:50 +08:00
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DynAlloc,
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2011-08-17 10:05:42 +08:00
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Sync,
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Ext,
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2012-06-02 08:03:12 +08:00
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Ins,
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// Load/Store Left/Right nodes.
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LWL = ISD::FIRST_TARGET_MEMORY_OPCODE,
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LWR,
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SWL,
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SWR,
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LDL,
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LDR,
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SDL,
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SDR
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2007-06-06 15:42:06 +08:00
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};
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}
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2011-04-16 05:51:11 +08:00
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//===--------------------------------------------------------------------===//
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2007-06-06 15:42:06 +08:00
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// TargetLowering Implementation
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2011-04-16 05:51:11 +08:00
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//===--------------------------------------------------------------------===//
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2011-03-05 01:51:39 +08:00
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2009-08-13 13:41:27 +08:00
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class MipsTargetLowering : public TargetLowering {
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2007-06-06 15:42:06 +08:00
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public:
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2007-08-03 05:21:54 +08:00
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explicit MipsTargetLowering(MipsTargetMachine &TM);
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2007-06-06 15:42:06 +08:00
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2011-11-08 02:59:49 +08:00
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virtual MVT getShiftAmountTy(EVT LHSTy) const { return MVT::i32; }
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2011-08-13 05:30:06 +08:00
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virtual bool allowsUnalignedMemoryAccesses (EVT VT) const;
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2007-06-06 15:42:06 +08:00
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/// LowerOperation - Provide custom lowering hooks for some operations.
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2010-04-17 23:26:15 +08:00
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virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
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2007-06-06 15:42:06 +08:00
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2011-03-05 01:51:39 +08:00
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/// getTargetNodeName - This method returns the name of a target specific
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2007-06-06 15:42:06 +08:00
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// DAG node.
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virtual const char *getTargetNodeName(unsigned Opcode) const;
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2008-03-10 23:42:14 +08:00
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/// getSetCCResultType - get the ISD::SETCC result ValueType
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2011-09-07 03:07:46 +08:00
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EVT getSetCCResultType(EVT VT) const;
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2008-03-10 23:42:14 +08:00
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2011-03-05 01:51:39 +08:00
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virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
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2007-06-06 15:42:06 +08:00
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private:
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Several changes to Mips backend, experimental fp support being the most
important.
- Cleanup in the Subtarget info with addition of new features, not all support
yet, but they allow the future inclusion of features easier. Among new features,
we have : Arch family info (mips1, mips2, ...), ABI info (o32, eabi), 64-bit
integer
and float registers, allegrex vector FPU (VFPU), single float only support.
- TargetMachine now detects allegrex core.
- Added allegrex (Mips32r2) sext_inreg instructions.
- *Added Float Point Instructions*, handling single float only, and
aliased accesses for 32-bit FPUs.
- Some cleanup in FP instruction formats and FP register classes.
- Calling conventions improved to support mips 32-bit EABI.
- Added Asm Printer support for fp cond codes.
- Added support for sret copy to a return register.
- EABI support added into LowerCALL and FORMAL_ARGS.
- MipsFunctionInfo now keeps a virtual register per function to track the
sret on function entry until function ret.
- MipsInstrInfo FP support into methods (isMoveInstr, isLoadFromStackSlot, ...),
FP cond codes mapping and initial FP Branch Analysis.
- Two new Mips SDNode to handle fp branch and compare instructions : FPBrcond,
FPCmp
- MipsTargetLowering : handling different FP classes, Allegrex support, sret
return copy, no homing location within EABI, non 32-bit stack objects
arguments, and asm constraint for float.
llvm-svn: 53146
2008-07-06 03:05:21 +08:00
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// Subtarget Info
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const MipsSubtarget *Subtarget;
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2012-02-28 15:46:26 +08:00
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2011-10-29 02:47:24 +08:00
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bool HasMips64, IsN64, IsO32;
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2009-08-13 13:41:27 +08:00
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2007-06-06 15:42:06 +08:00
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// Lower Operand helpers
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Major calling convention code refactoring.
Instead of awkwardly encoding calling-convention information with ISD::CALL,
ISD::FORMAL_ARGUMENTS, ISD::RET, and ISD::ARG_FLAGS nodes, TargetLowering
provides three virtual functions for targets to override:
LowerFormalArguments, LowerCall, and LowerRet, which replace the custom
lowering done on the special nodes. They provide the same information, but
in a more immediately usable format.
This also reworks much of the target-independent tail call logic. The
decision of whether or not to perform a tail call is now cleanly split
between target-independent portions, and the target dependent portion
in IsEligibleForTailCallOptimization.
This also synchronizes all in-tree targets, to help enable future
refactoring and feature work.
llvm-svn: 78142
2009-08-05 09:29:28 +08:00
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SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
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2009-09-02 16:44:58 +08:00
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CallingConv::ID CallConv, bool isVarArg,
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Major calling convention code refactoring.
Instead of awkwardly encoding calling-convention information with ISD::CALL,
ISD::FORMAL_ARGUMENTS, ISD::RET, and ISD::ARG_FLAGS nodes, TargetLowering
provides three virtual functions for targets to override:
LowerFormalArguments, LowerCall, and LowerRet, which replace the custom
lowering done on the special nodes. They provide the same information, but
in a more immediately usable format.
This also reworks much of the target-independent tail call logic. The
decision of whether or not to perform a tail call is now cleanly split
between target-independent portions, and the target dependent portion
in IsEligibleForTailCallOptimization.
This also synchronizes all in-tree targets, to help enable future
refactoring and feature work.
llvm-svn: 78142
2009-08-05 09:29:28 +08:00
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const SmallVectorImpl<ISD::InputArg> &Ins,
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DebugLoc dl, SelectionDAG &DAG,
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2010-04-17 23:26:15 +08:00
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SmallVectorImpl<SDValue> &InVals) const;
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2007-06-06 15:42:06 +08:00
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// Lower Operand specifics
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2010-04-17 23:26:15 +08:00
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SDValue LowerBRCOND(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
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2011-03-05 04:01:52 +08:00
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SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
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2010-04-17 23:26:15 +08:00
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SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerSELECT(SDValue Op, SelectionDAG &DAG) const;
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2012-07-12 03:32:27 +08:00
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SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const;
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2012-03-10 07:46:03 +08:00
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SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG) const;
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2010-04-17 23:26:15 +08:00
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SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) const;
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2011-05-26 03:32:07 +08:00
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SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const;
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2012-04-12 06:49:04 +08:00
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SDValue LowerFABS(SDValue Op, SelectionDAG &DAG) const;
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2011-06-02 08:24:44 +08:00
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SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
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2012-07-11 08:53:32 +08:00
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SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
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2011-07-20 07:30:50 +08:00
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SDValue LowerMEMBARRIER(SDValue Op, SelectionDAG& DAG) const;
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2011-07-28 06:21:52 +08:00
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SDValue LowerATOMIC_FENCE(SDValue Op, SelectionDAG& DAG) const;
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2012-05-09 08:55:21 +08:00
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SDValue LowerShiftLeftParts(SDValue Op, SelectionDAG& DAG) const;
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2012-06-15 05:10:56 +08:00
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SDValue LowerShiftRightParts(SDValue Op, SelectionDAG& DAG,
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bool IsSRA) const;
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2012-06-02 08:03:49 +08:00
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SDValue LowerLOAD(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerSTORE(SDValue Op, SelectionDAG &DAG) const;
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2008-06-06 08:58:26 +08:00
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Major calling convention code refactoring.
Instead of awkwardly encoding calling-convention information with ISD::CALL,
ISD::FORMAL_ARGUMENTS, ISD::RET, and ISD::ARG_FLAGS nodes, TargetLowering
provides three virtual functions for targets to override:
LowerFormalArguments, LowerCall, and LowerRet, which replace the custom
lowering done on the special nodes. They provide the same information, but
in a more immediately usable format.
This also reworks much of the target-independent tail call logic. The
decision of whether or not to perform a tail call is now cleanly split
between target-independent portions, and the target dependent portion
in IsEligibleForTailCallOptimization.
This also synchronizes all in-tree targets, to help enable future
refactoring and feature work.
llvm-svn: 78142
2009-08-05 09:29:28 +08:00
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virtual SDValue
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LowerFormalArguments(SDValue Chain,
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2009-09-02 16:44:58 +08:00
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CallingConv::ID CallConv, bool isVarArg,
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Major calling convention code refactoring.
Instead of awkwardly encoding calling-convention information with ISD::CALL,
ISD::FORMAL_ARGUMENTS, ISD::RET, and ISD::ARG_FLAGS nodes, TargetLowering
provides three virtual functions for targets to override:
LowerFormalArguments, LowerCall, and LowerRet, which replace the custom
lowering done on the special nodes. They provide the same information, but
in a more immediately usable format.
This also reworks much of the target-independent tail call logic. The
decision of whether or not to perform a tail call is now cleanly split
between target-independent portions, and the target dependent portion
in IsEligibleForTailCallOptimization.
This also synchronizes all in-tree targets, to help enable future
refactoring and feature work.
llvm-svn: 78142
2009-08-05 09:29:28 +08:00
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const SmallVectorImpl<ISD::InputArg> &Ins,
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DebugLoc dl, SelectionDAG &DAG,
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2010-04-17 23:26:15 +08:00
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SmallVectorImpl<SDValue> &InVals) const;
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Major calling convention code refactoring.
Instead of awkwardly encoding calling-convention information with ISD::CALL,
ISD::FORMAL_ARGUMENTS, ISD::RET, and ISD::ARG_FLAGS nodes, TargetLowering
provides three virtual functions for targets to override:
LowerFormalArguments, LowerCall, and LowerRet, which replace the custom
lowering done on the special nodes. They provide the same information, but
in a more immediately usable format.
This also reworks much of the target-independent tail call logic. The
decision of whether or not to perform a tail call is now cleanly split
between target-independent portions, and the target dependent portion
in IsEligibleForTailCallOptimization.
This also synchronizes all in-tree targets, to help enable future
refactoring and feature work.
llvm-svn: 78142
2009-08-05 09:29:28 +08:00
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virtual SDValue
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2012-05-26 00:35:28 +08:00
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LowerCall(TargetLowering::CallLoweringInfo &CLI,
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2010-04-17 23:26:15 +08:00
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SmallVectorImpl<SDValue> &InVals) const;
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Major calling convention code refactoring.
Instead of awkwardly encoding calling-convention information with ISD::CALL,
ISD::FORMAL_ARGUMENTS, ISD::RET, and ISD::ARG_FLAGS nodes, TargetLowering
provides three virtual functions for targets to override:
LowerFormalArguments, LowerCall, and LowerRet, which replace the custom
lowering done on the special nodes. They provide the same information, but
in a more immediately usable format.
This also reworks much of the target-independent tail call logic. The
decision of whether or not to perform a tail call is now cleanly split
between target-independent portions, and the target dependent portion
in IsEligibleForTailCallOptimization.
This also synchronizes all in-tree targets, to help enable future
refactoring and feature work.
llvm-svn: 78142
2009-08-05 09:29:28 +08:00
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virtual SDValue
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LowerReturn(SDValue Chain,
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2009-09-02 16:44:58 +08:00
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CallingConv::ID CallConv, bool isVarArg,
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Major calling convention code refactoring.
Instead of awkwardly encoding calling-convention information with ISD::CALL,
ISD::FORMAL_ARGUMENTS, ISD::RET, and ISD::ARG_FLAGS nodes, TargetLowering
provides three virtual functions for targets to override:
LowerFormalArguments, LowerCall, and LowerRet, which replace the custom
lowering done on the special nodes. They provide the same information, but
in a more immediately usable format.
This also reworks much of the target-independent tail call logic. The
decision of whether or not to perform a tail call is now cleanly split
between target-independent portions, and the target dependent portion
in IsEligibleForTailCallOptimization.
This also synchronizes all in-tree targets, to help enable future
refactoring and feature work.
llvm-svn: 78142
2009-08-05 09:29:28 +08:00
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const SmallVectorImpl<ISD::OutputArg> &Outs,
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2010-07-07 23:54:55 +08:00
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const SmallVectorImpl<SDValue> &OutVals,
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2010-04-17 23:26:15 +08:00
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DebugLoc dl, SelectionDAG &DAG) const;
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Major calling convention code refactoring.
Instead of awkwardly encoding calling-convention information with ISD::CALL,
ISD::FORMAL_ARGUMENTS, ISD::RET, and ISD::ARG_FLAGS nodes, TargetLowering
provides three virtual functions for targets to override:
LowerFormalArguments, LowerCall, and LowerRet, which replace the custom
lowering done on the special nodes. They provide the same information, but
in a more immediately usable format.
This also reworks much of the target-independent tail call logic. The
decision of whether or not to perform a tail call is now cleanly split
between target-independent portions, and the target dependent portion
in IsEligibleForTailCallOptimization.
This also synchronizes all in-tree targets, to help enable future
refactoring and feature work.
llvm-svn: 78142
2009-08-05 09:29:28 +08:00
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2010-05-01 08:01:06 +08:00
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virtual MachineBasicBlock *
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EmitInstrWithCustomInserter(MachineInstr *MI,
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MachineBasicBlock *MBB) const;
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2007-06-06 15:42:06 +08:00
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2007-08-22 00:09:25 +08:00
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// Inline asm support
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ConstraintType getConstraintType(const std::string &Constraint) const;
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2011-04-16 05:51:11 +08:00
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/// Examine constraint string and operand type and determine a weight value.
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/// The operand object must already have been set up with the operand type.
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2010-10-30 01:29:13 +08:00
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ConstraintWeight getSingleConstraintMatchWeight(
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AsmOperandInfo &info, const char *constraint) const;
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2011-03-05 01:51:39 +08:00
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std::pair<unsigned, const TargetRegisterClass*>
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2007-08-22 00:09:25 +08:00
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getRegForInlineAsmConstraint(const std::string &Constraint,
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2009-08-11 06:56:29 +08:00
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EVT VT) const;
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2007-08-22 00:09:25 +08:00
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2012-05-07 11:13:32 +08:00
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/// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
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/// vector. If it is invalid, don't add anything to Ops. If hasMemory is
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/// true it means one of the asm constraint of the inline asm instruction
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/// being processed is 'm'.
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virtual void LowerAsmOperandForConstraint(SDValue Op,
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std::string &Constraint,
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std::vector<SDValue> &Ops,
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SelectionDAG &DAG) const;
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Teach DAGCombine to fold constant offsets into GlobalAddress nodes,
and add a TargetLowering hook for it to use to determine when this
is legal (i.e. not in PIC mode, etc.)
This allows instruction selection to emit folded constant offsets
in more cases, such as the included testcase, eliminating the need
for explicit arithmetic instructions.
This eliminates the need for the C++ code in X86ISelDAGToDAG.cpp
that attempted to achieve the same effect, but wasn't as effective.
Also, fix handling of offsets in GlobalAddressSDNodes in several
places, including changing GlobalAddressSDNode's offset from
int to int64_t.
The Mips, Alpha, Sparc, and CellSPU targets appear to be
unaware of GlobalAddress offsets currently, so set the hook to
false on those targets.
llvm-svn: 57748
2008-10-18 10:06:02 +08:00
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virtual bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const;
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2009-10-28 03:56:55 +08:00
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2012-06-14 03:33:32 +08:00
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virtual EVT getOptimalMemOpType(uint64_t Size, unsigned DstAlign,
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unsigned SrcAlign, bool IsZeroVal,
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bool MemcpyStrSrc,
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MachineFunction &MF) const;
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2009-10-28 03:56:55 +08:00
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/// isFPImmLegal - Returns true if the target can instruction select the
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/// specified FP immediate natively. If false, the legalizer will
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/// materialize the FP immediate as a load from a constant pool.
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2009-10-28 09:43:28 +08:00
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virtual bool isFPImmLegal(const APFloat &Imm, EVT VT) const;
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2011-05-31 10:54:07 +08:00
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2012-02-03 12:33:00 +08:00
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virtual unsigned getJumpTableEncoding() const;
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2011-05-31 10:54:07 +08:00
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MachineBasicBlock *EmitAtomicBinary(MachineInstr *MI, MachineBasicBlock *BB,
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unsigned Size, unsigned BinOpcode, bool Nand = false) const;
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MachineBasicBlock *EmitAtomicBinaryPartword(MachineInstr *MI,
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MachineBasicBlock *BB, unsigned Size, unsigned BinOpcode,
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bool Nand = false) const;
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MachineBasicBlock *EmitAtomicCmpSwap(MachineInstr *MI,
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MachineBasicBlock *BB, unsigned Size) const;
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MachineBasicBlock *EmitAtomicCmpSwapPartword(MachineInstr *MI,
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MachineBasicBlock *BB, unsigned Size) const;
|
2007-06-06 15:42:06 +08:00
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};
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}
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#endif // MipsISELLOWERING_H
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