2017-11-08 00:58:13 +08:00
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//=-- SVEInstrFormats.td - AArch64 SVE Instruction classes -*- tablegen -*--=//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// AArch64 Scalable Vector Extension (SVE) Instruction Class Definitions.
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//
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//===----------------------------------------------------------------------===//
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[AArch64][SVE] Asm: PTRUE and PTRUES instructions
Summary: These instructions initialize a predicate vector from a pattern/immediate.
Reviewers: fhahn, rengolin, evandro, mcrosier, t.p.northover, samparker, olista01
Reviewed By: samparker
Subscribers: aemerson, javed.absar, tschuett, kristof.beyls, llvm-commits
Differential Revision: https://reviews.llvm.org/D41819
llvm-svn: 323124
2018-01-22 23:29:19 +08:00
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def SVEPatternOperand : AsmOperandClass {
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let Name = "SVEPattern";
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let ParserMethod = "tryParseSVEPattern";
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let PredicateMethod = "isSVEPattern";
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let RenderMethod = "addImmOperands";
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let DiagnosticType = "InvalidSVEPattern";
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}
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def sve_pred_enum : Operand<i32>, ImmLeaf<i32, [{
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return (((uint32_t)Imm) < 32);
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}]> {
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let PrintMethod = "printSVEPattern";
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let ParserMatchClass = SVEPatternOperand;
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}
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2018-05-14 19:54:41 +08:00
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def SVEPrefetchOperand : AsmOperandClass {
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let Name = "SVEPrefetch";
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let ParserMethod = "tryParsePrefetch<true>";
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let PredicateMethod = "isPrefetch";
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let RenderMethod = "addPrefetchOperands";
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}
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def sve_prfop : Operand<i32>, ImmLeaf<i32, [{
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return (((uint32_t)Imm) <= 15);
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}]> {
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let PrintMethod = "printPrefetchOp<true>";
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let ParserMatchClass = SVEPrefetchOperand;
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}
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2018-02-06 21:13:21 +08:00
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class SVELogicalImmOperand<int Width> : AsmOperandClass {
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let Name = "SVELogicalImm" # Width;
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let DiagnosticType = "LogicalSecondSource";
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let PredicateMethod = "isLogicalImm<int" # Width # "_t>";
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let RenderMethod = "addLogicalImmOperands<int" # Width # "_t>";
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}
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def sve_logical_imm8 : Operand<i64> {
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let ParserMatchClass = SVELogicalImmOperand<8>;
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let PrintMethod = "printLogicalImm<int8_t>";
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let MCOperandPredicate = [{
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if (!MCOp.isImm())
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return false;
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int64_t Val = AArch64_AM::decodeLogicalImmediate(MCOp.getImm(), 64);
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return AArch64_AM::isSVEMaskOfIdenticalElements<int8_t>(Val);
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}];
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}
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def sve_logical_imm16 : Operand<i64> {
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let ParserMatchClass = SVELogicalImmOperand<16>;
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let PrintMethod = "printLogicalImm<int16_t>";
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let MCOperandPredicate = [{
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if (!MCOp.isImm())
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return false;
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int64_t Val = AArch64_AM::decodeLogicalImmediate(MCOp.getImm(), 64);
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return AArch64_AM::isSVEMaskOfIdenticalElements<int16_t>(Val);
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}];
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}
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def sve_logical_imm32 : Operand<i64> {
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let ParserMatchClass = SVELogicalImmOperand<32>;
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let PrintMethod = "printLogicalImm<int32_t>";
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let MCOperandPredicate = [{
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if (!MCOp.isImm())
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return false;
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int64_t Val = AArch64_AM::decodeLogicalImmediate(MCOp.getImm(), 64);
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return AArch64_AM::isSVEMaskOfIdenticalElements<int32_t>(Val);
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}];
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}
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2018-06-01 15:25:46 +08:00
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class SVEPreferredLogicalImmOperand<int Width> : AsmOperandClass {
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let Name = "SVEPreferredLogicalImm" # Width;
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let PredicateMethod = "isSVEPreferredLogicalImm<int" # Width # "_t>";
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let RenderMethod = "addLogicalImmOperands<int" # Width # "_t>";
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}
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def sve_preferred_logical_imm16 : Operand<i64> {
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let ParserMatchClass = SVEPreferredLogicalImmOperand<16>;
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let PrintMethod = "printSVELogicalImm<int16_t>";
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let MCOperandPredicate = [{
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if (!MCOp.isImm())
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return false;
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int64_t Val = AArch64_AM::decodeLogicalImmediate(MCOp.getImm(), 64);
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return AArch64_AM::isSVEMaskOfIdenticalElements<int16_t>(Val) &&
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AArch64_AM::isSVEMoveMaskPreferredLogicalImmediate(Val);
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}];
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}
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def sve_preferred_logical_imm32 : Operand<i64> {
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let ParserMatchClass = SVEPreferredLogicalImmOperand<32>;
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let PrintMethod = "printSVELogicalImm<int32_t>";
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let MCOperandPredicate = [{
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if (!MCOp.isImm())
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return false;
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int64_t Val = AArch64_AM::decodeLogicalImmediate(MCOp.getImm(), 64);
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return AArch64_AM::isSVEMaskOfIdenticalElements<int32_t>(Val) &&
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AArch64_AM::isSVEMoveMaskPreferredLogicalImmediate(Val);
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}];
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}
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def sve_preferred_logical_imm64 : Operand<i64> {
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let ParserMatchClass = SVEPreferredLogicalImmOperand<64>;
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let PrintMethod = "printSVELogicalImm<int64_t>";
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let MCOperandPredicate = [{
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if (!MCOp.isImm())
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return false;
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int64_t Val = AArch64_AM::decodeLogicalImmediate(MCOp.getImm(), 64);
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return AArch64_AM::isSVEMaskOfIdenticalElements<int64_t>(Val) &&
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AArch64_AM::isSVEMoveMaskPreferredLogicalImmediate(Val);
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}];
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}
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2018-02-06 21:13:21 +08:00
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class SVELogicalImmNotOperand<int Width> : AsmOperandClass {
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let Name = "SVELogicalImm" # Width # "Not";
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let DiagnosticType = "LogicalSecondSource";
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let PredicateMethod = "isLogicalImm<int" # Width # "_t>";
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let RenderMethod = "addLogicalImmNotOperands<int" # Width # "_t>";
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}
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def sve_logical_imm8_not : Operand<i64> {
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let ParserMatchClass = SVELogicalImmNotOperand<8>;
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}
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def sve_logical_imm16_not : Operand<i64> {
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let ParserMatchClass = SVELogicalImmNotOperand<16>;
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}
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def sve_logical_imm32_not : Operand<i64> {
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let ParserMatchClass = SVELogicalImmNotOperand<32>;
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}
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2018-05-25 17:47:52 +08:00
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class SVEShiftedImmOperand<int ElementWidth, string Infix, string Predicate>
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: AsmOperandClass {
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let Name = "SVE" # Infix # "Imm" # ElementWidth;
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let DiagnosticType = "Invalid" # Name;
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let RenderMethod = "addImmWithOptionalShiftOperands<8>";
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let ParserMethod = "tryParseImmWithOptionalShift";
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let PredicateMethod = Predicate;
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}
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def SVECpyImmOperand8 : SVEShiftedImmOperand<8, "Cpy", "isSVECpyImm<int8_t>">;
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def SVECpyImmOperand16 : SVEShiftedImmOperand<16, "Cpy", "isSVECpyImm<int16_t>">;
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def SVECpyImmOperand32 : SVEShiftedImmOperand<32, "Cpy", "isSVECpyImm<int32_t>">;
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def SVECpyImmOperand64 : SVEShiftedImmOperand<64, "Cpy", "isSVECpyImm<int64_t>">;
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2018-05-29 18:39:49 +08:00
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def SVEAddSubImmOperand8 : SVEShiftedImmOperand<8, "AddSub", "isSVEAddSubImm<int8_t>">;
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def SVEAddSubImmOperand16 : SVEShiftedImmOperand<16, "AddSub", "isSVEAddSubImm<int16_t>">;
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def SVEAddSubImmOperand32 : SVEShiftedImmOperand<32, "AddSub", "isSVEAddSubImm<int32_t>">;
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def SVEAddSubImmOperand64 : SVEShiftedImmOperand<64, "AddSub", "isSVEAddSubImm<int64_t>">;
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2018-05-25 17:47:52 +08:00
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class imm8_opt_lsl<int ElementWidth, string printType,
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AsmOperandClass OpndClass, code Predicate>
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: Operand<i32>, ImmLeaf<i32, Predicate> {
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let EncoderMethod = "getImm8OptLsl";
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let DecoderMethod = "DecodeImm8OptLsl<" # ElementWidth # ">";
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let PrintMethod = "printImm8OptLsl<" # printType # ">";
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let ParserMatchClass = OpndClass;
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let MIOperandInfo = (ops i32imm, i32imm);
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}
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def cpy_imm8_opt_lsl_i8 : imm8_opt_lsl<8, "int8_t", SVECpyImmOperand8, [{
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return AArch64_AM::isSVECpyImm<int8_t>(Imm);
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}]>;
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def cpy_imm8_opt_lsl_i16 : imm8_opt_lsl<16, "int16_t", SVECpyImmOperand16, [{
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return AArch64_AM::isSVECpyImm<int16_t>(Imm);
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}]>;
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def cpy_imm8_opt_lsl_i32 : imm8_opt_lsl<32, "int32_t", SVECpyImmOperand32, [{
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return AArch64_AM::isSVECpyImm<int32_t>(Imm);
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}]>;
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def cpy_imm8_opt_lsl_i64 : imm8_opt_lsl<64, "int64_t", SVECpyImmOperand64, [{
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return AArch64_AM::isSVECpyImm<int64_t>(Imm);
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}]>;
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2018-05-29 18:39:49 +08:00
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def addsub_imm8_opt_lsl_i8 : imm8_opt_lsl<8, "uint8_t", SVEAddSubImmOperand8, [{
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return AArch64_AM::isSVEAddSubImm<int8_t>(Imm);
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}]>;
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def addsub_imm8_opt_lsl_i16 : imm8_opt_lsl<16, "uint16_t", SVEAddSubImmOperand16, [{
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return AArch64_AM::isSVEAddSubImm<int16_t>(Imm);
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}]>;
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def addsub_imm8_opt_lsl_i32 : imm8_opt_lsl<32, "uint32_t", SVEAddSubImmOperand32, [{
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return AArch64_AM::isSVEAddSubImm<int32_t>(Imm);
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}]>;
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def addsub_imm8_opt_lsl_i64 : imm8_opt_lsl<64, "uint64_t", SVEAddSubImmOperand64, [{
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return AArch64_AM::isSVEAddSubImm<int64_t>(Imm);
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}]>;
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2018-06-15 21:11:49 +08:00
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class SVEExactFPImm<string Suffix, string ValA, string ValB> : AsmOperandClass {
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let Name = "SVEExactFPImmOperand" # Suffix;
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let DiagnosticType = "Invalid" # Name;
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let ParserMethod = "tryParseFPImm<false>";
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let PredicateMethod = "isExactFPImm<" # ValA # ", " # ValB # ">";
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let RenderMethod = "addExactFPImmOperands<" # ValA # ", " # ValB # ">";
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}
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class SVEExactFPImmOperand<string Suffix, string ValA, string ValB> : Operand<i32> {
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let PrintMethod = "printExactFPImm<" # ValA # ", " # ValB # ">";
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let ParserMatchClass = SVEExactFPImm<Suffix, ValA, ValB>;
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}
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2018-06-04 14:40:55 +08:00
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2018-06-15 21:57:51 +08:00
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def sve_fpimm_half_one
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: SVEExactFPImmOperand<"HalfOne", "AArch64ExactFPImm::half",
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"AArch64ExactFPImm::one">;
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def sve_fpimm_half_two
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: SVEExactFPImmOperand<"HalfTwo", "AArch64ExactFPImm::half",
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"AArch64ExactFPImm::two">;
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def sve_fpimm_zero_one
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: SVEExactFPImmOperand<"ZeroOne", "AArch64ExactFPImm::zero",
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"AArch64ExactFPImm::one">;
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2018-06-15 23:47:44 +08:00
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def sve_incdec_imm : Operand<i32>, ImmLeaf<i32, [{
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return (((uint32_t)Imm) > 0) && (((uint32_t)Imm) < 17);
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}]> {
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let ParserMatchClass = Imm1_16Operand;
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let EncoderMethod = "getSVEIncDecImm";
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let DecoderMethod = "DecodeSVEIncDecImm";
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}
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[AArch64][SVE] Asm: PTRUE and PTRUES instructions
Summary: These instructions initialize a predicate vector from a pattern/immediate.
Reviewers: fhahn, rengolin, evandro, mcrosier, t.p.northover, samparker, olista01
Reviewed By: samparker
Subscribers: aemerson, javed.absar, tschuett, kristof.beyls, llvm-commits
Differential Revision: https://reviews.llvm.org/D41819
llvm-svn: 323124
2018-01-22 23:29:19 +08:00
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//===----------------------------------------------------------------------===//
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// SVE PTrue - These are used extensively throughout the pattern matching so
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// it's important we define them first.
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//===----------------------------------------------------------------------===//
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class sve_int_ptrue<bits<2> sz8_64, bits<3> opc, string asm, PPRRegOp pprty>
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: I<(outs pprty:$Pd), (ins sve_pred_enum:$pattern),
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asm, "\t$Pd, $pattern",
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"",
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[]>, Sched<[]> {
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bits<4> Pd;
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bits<5> pattern;
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let Inst{31-24} = 0b00100101;
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let Inst{23-22} = sz8_64;
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let Inst{21-19} = 0b011;
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let Inst{18-17} = opc{2-1};
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let Inst{16} = opc{0};
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let Inst{15-10} = 0b111000;
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let Inst{9-5} = pattern;
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let Inst{4} = 0b0;
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let Inst{3-0} = Pd;
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let Defs = !if(!eq (opc{0}, 1), [NZCV], []);
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}
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multiclass sve_int_ptrue<bits<3> opc, string asm> {
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def _B : sve_int_ptrue<0b00, opc, asm, PPR8>;
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def _H : sve_int_ptrue<0b01, opc, asm, PPR16>;
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def _S : sve_int_ptrue<0b10, opc, asm, PPR32>;
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def _D : sve_int_ptrue<0b11, opc, asm, PPR64>;
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def : InstAlias<asm # "\t$Pd",
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(!cast<Instruction>(NAME # _B) PPR8:$Pd, 0b11111), 1>;
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def : InstAlias<asm # "\t$Pd",
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(!cast<Instruction>(NAME # _H) PPR16:$Pd, 0b11111), 1>;
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def : InstAlias<asm # "\t$Pd",
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(!cast<Instruction>(NAME # _S) PPR32:$Pd, 0b11111), 1>;
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def : InstAlias<asm # "\t$Pd",
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(!cast<Instruction>(NAME # _D) PPR64:$Pd, 0b11111), 1>;
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}
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let Predicates = [HasSVE] in {
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defm PTRUE : sve_int_ptrue<0b000, "ptrue">;
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defm PTRUES : sve_int_ptrue<0b001, "ptrues">;
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}
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2018-06-15 23:47:44 +08:00
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[AArch64][SVE] Asm: Support for (SQ)INCP/DECP (scalar, vector)
Increments/decrements the result with the number of active bits
from the predicate.
The inc/dec variants added are:
- incp x0, p0.h (scalar)
- incp z0.h, p0 (vector)
The unsigned saturating inc/dec variants added are:
- uqincp x0, p0.h (scalar)
- uqincp w0, p0.h (scalar, 32bit)
- uqincp z0.h, p0 (vector)
The signed saturating inc/dec variants added are:
- sqincp x0, p0.h (scalar)
- sqincp x0, p0.h, w0 (scalar, 32bit)
- sqincp z0.h, p0 (vector)
llvm-svn: 336091
2018-07-02 18:08:36 +08:00
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//===----------------------------------------------------------------------===//
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// SVE Predicate Count Group
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//===----------------------------------------------------------------------===//
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class sve_int_count_r<bits<2> sz8_64, bits<5> opc, string asm,
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RegisterOperand dty, PPRRegOp pprty, RegisterOperand sty>
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: I<(outs dty:$Rdn), (ins pprty:$Pg, sty:$_Rdn),
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asm, "\t$Rdn, $Pg",
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"",
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[]>, Sched<[]> {
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bits<5> Rdn;
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bits<4> Pg;
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let Inst{31-24} = 0b00100101;
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let Inst{23-22} = sz8_64;
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let Inst{21-19} = 0b101;
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let Inst{18-16} = opc{4-2};
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let Inst{15-11} = 0b10001;
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let Inst{10-9} = opc{1-0};
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let Inst{8-5} = Pg;
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let Inst{4-0} = Rdn;
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// Signed 32bit forms require their GPR operand printed.
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let AsmString = !if(!eq(opc{4,2-0}, 0b0000),
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!strconcat(asm, "\t$Rdn, $Pg, $_Rdn"),
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!strconcat(asm, "\t$Rdn, $Pg"));
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let Constraints = "$Rdn = $_Rdn";
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}
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multiclass sve_int_count_r_s32<bits<5> opc, string asm> {
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def _B : sve_int_count_r<0b00, opc, asm, GPR64z, PPR8, GPR64as32>;
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def _H : sve_int_count_r<0b01, opc, asm, GPR64z, PPR16, GPR64as32>;
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def _S : sve_int_count_r<0b10, opc, asm, GPR64z, PPR32, GPR64as32>;
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def _D : sve_int_count_r<0b11, opc, asm, GPR64z, PPR64, GPR64as32>;
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}
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multiclass sve_int_count_r_u32<bits<5> opc, string asm> {
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def _B : sve_int_count_r<0b00, opc, asm, GPR32z, PPR8, GPR32z>;
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def _H : sve_int_count_r<0b01, opc, asm, GPR32z, PPR16, GPR32z>;
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def _S : sve_int_count_r<0b10, opc, asm, GPR32z, PPR32, GPR32z>;
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def _D : sve_int_count_r<0b11, opc, asm, GPR32z, PPR64, GPR32z>;
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}
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multiclass sve_int_count_r_x64<bits<5> opc, string asm> {
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def _B : sve_int_count_r<0b00, opc, asm, GPR64z, PPR8, GPR64z>;
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def _H : sve_int_count_r<0b01, opc, asm, GPR64z, PPR16, GPR64z>;
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def _S : sve_int_count_r<0b10, opc, asm, GPR64z, PPR32, GPR64z>;
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def _D : sve_int_count_r<0b11, opc, asm, GPR64z, PPR64, GPR64z>;
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}
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class sve_int_count_v<bits<2> sz8_64, bits<5> opc, string asm,
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ZPRRegOp zprty>
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: I<(outs zprty:$Zdn), (ins zprty:$_Zdn, PPRAny:$Pg),
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asm, "\t$Zdn, $Pg",
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"",
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[]>, Sched<[]> {
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bits<4> Pg;
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bits<5> Zdn;
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let Inst{31-24} = 0b00100101;
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let Inst{23-22} = sz8_64;
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let Inst{21-19} = 0b101;
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let Inst{18-16} = opc{4-2};
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let Inst{15-11} = 0b10000;
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let Inst{10-9} = opc{1-0};
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let Inst{8-5} = Pg;
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let Inst{4-0} = Zdn;
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let Constraints = "$Zdn = $_Zdn";
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}
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multiclass sve_int_count_v<bits<5> opc, string asm> {
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def _H : sve_int_count_v<0b01, opc, asm, ZPR16>;
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def _S : sve_int_count_v<0b10, opc, asm, ZPR32>;
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def _D : sve_int_count_v<0b11, opc, asm, ZPR64>;
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}
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2018-07-09 23:22:08 +08:00
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class sve_int_pcount_pred<bits<2> sz8_64, bits<4> opc, string asm,
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PPRRegOp pprty>
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: I<(outs GPR64:$Rd), (ins PPRAny:$Pg, pprty:$Pn),
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asm, "\t$Rd, $Pg, $Pn",
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"",
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[]>, Sched<[]> {
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bits<4> Pg;
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bits<4> Pn;
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bits<5> Rd;
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let Inst{31-24} = 0b00100101;
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let Inst{23-22} = sz8_64;
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let Inst{21-19} = 0b100;
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let Inst{18-16} = opc{3-1};
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let Inst{15-14} = 0b10;
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let Inst{13-10} = Pg;
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let Inst{9} = opc{0};
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let Inst{8-5} = Pn;
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let Inst{4-0} = Rd;
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}
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multiclass sve_int_pcount_pred<bits<4> opc, string asm> {
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def _B : sve_int_pcount_pred<0b00, opc, asm, PPR8>;
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def _H : sve_int_pcount_pred<0b01, opc, asm, PPR16>;
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def _S : sve_int_pcount_pred<0b10, opc, asm, PPR32>;
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def _D : sve_int_pcount_pred<0b11, opc, asm, PPR64>;
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}
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[AArch64][SVE] Asm: Support for (SQ)INCP/DECP (scalar, vector)
Increments/decrements the result with the number of active bits
from the predicate.
The inc/dec variants added are:
- incp x0, p0.h (scalar)
- incp z0.h, p0 (vector)
The unsigned saturating inc/dec variants added are:
- uqincp x0, p0.h (scalar)
- uqincp w0, p0.h (scalar, 32bit)
- uqincp z0.h, p0 (vector)
The signed saturating inc/dec variants added are:
- sqincp x0, p0.h (scalar)
- sqincp x0, p0.h, w0 (scalar, 32bit)
- sqincp z0.h, p0 (vector)
llvm-svn: 336091
2018-07-02 18:08:36 +08:00
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2018-06-15 23:47:44 +08:00
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//===----------------------------------------------------------------------===//
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// SVE Element Count Group
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//===----------------------------------------------------------------------===//
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2018-07-09 23:22:08 +08:00
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class sve_int_count<bits<3> opc, string asm>
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: I<(outs GPR64:$Rd), (ins sve_pred_enum:$pattern, sve_incdec_imm:$imm4),
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asm, "\t$Rd, $pattern, mul $imm4",
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"",
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[]>, Sched<[]> {
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bits<5> Rd;
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bits<4> imm4;
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bits<5> pattern;
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let Inst{31-24} = 0b00000100;
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let Inst{23-22} = opc{2-1};
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let Inst{21-20} = 0b10;
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let Inst{19-16} = imm4;
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let Inst{15-11} = 0b11100;
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let Inst{10} = opc{0};
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let Inst{9-5} = pattern;
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let Inst{4-0} = Rd;
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}
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multiclass sve_int_count<bits<3> opc, string asm> {
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def NAME : sve_int_count<opc, asm>;
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def : InstAlias<asm # "\t$Rd, $pattern",
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(!cast<Instruction>(NAME) GPR64:$Rd, sve_pred_enum:$pattern, 1), 1>;
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def : InstAlias<asm # "\t$Rd",
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(!cast<Instruction>(NAME) GPR64:$Rd, 0b11111, 1), 2>;
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}
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[AArch64][SVE] Asm: Support for (saturating) vector INC/DEC instructions.
Increment/decrement vector by multiple of predicate constraint
element count.
The variants added by this patch are:
- INCH, INCW, INC
and (saturating):
- SQINCH, SQINCW, SQINCD
- UQINCH, UQINCW, UQINCW
- SQDECH, SQINCW, SQINCD
- UQDECH, UQINCW, UQINCW
For example:
incw z0.s, all, mul #4
llvm-svn: 336090
2018-07-02 17:31:11 +08:00
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class sve_int_countvlv<bits<5> opc, string asm, ZPRRegOp zprty>
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: I<(outs zprty:$Zdn), (ins zprty:$_Zdn, sve_pred_enum:$pattern, sve_incdec_imm:$imm4),
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asm, "\t$Zdn, $pattern, mul $imm4",
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"",
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[]>, Sched<[]> {
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bits<5> Zdn;
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bits<5> pattern;
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bits<4> imm4;
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let Inst{31-24} = 0b00000100;
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let Inst{23-22} = opc{4-3};
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let Inst{21} = 0b1;
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let Inst{20} = opc{2};
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let Inst{19-16} = imm4;
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let Inst{15-12} = 0b1100;
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let Inst{11-10} = opc{1-0};
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let Inst{9-5} = pattern;
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let Inst{4-0} = Zdn;
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let Constraints = "$Zdn = $_Zdn";
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}
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multiclass sve_int_countvlv<bits<5> opc, string asm, ZPRRegOp zprty> {
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def NAME : sve_int_countvlv<opc, asm, zprty>;
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def : InstAlias<asm # "\t$Zdn, $pattern",
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(!cast<Instruction>(NAME) zprty:$Zdn, sve_pred_enum:$pattern, 1), 1>;
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def : InstAlias<asm # "\t$Zdn",
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(!cast<Instruction>(NAME) zprty:$Zdn, 0b11111, 1), 2>;
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}
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2018-06-15 23:47:44 +08:00
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class sve_int_pred_pattern_a<bits<3> opc, string asm>
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: I<(outs GPR64:$Rdn), (ins GPR64:$_Rdn, sve_pred_enum:$pattern, sve_incdec_imm:$imm4),
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asm, "\t$Rdn, $pattern, mul $imm4",
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"",
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[]>, Sched<[]> {
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bits<5> Rdn;
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bits<5> pattern;
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bits<4> imm4;
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let Inst{31-24} = 0b00000100;
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let Inst{23-22} = opc{2-1};
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let Inst{21-20} = 0b11;
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let Inst{19-16} = imm4;
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let Inst{15-11} = 0b11100;
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let Inst{10} = opc{0};
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let Inst{9-5} = pattern;
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let Inst{4-0} = Rdn;
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let Constraints = "$Rdn = $_Rdn";
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}
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multiclass sve_int_pred_pattern_a<bits<3> opc, string asm> {
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def NAME : sve_int_pred_pattern_a<opc, asm>;
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def : InstAlias<asm # "\t$Rdn, $pattern",
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(!cast<Instruction>(NAME) GPR64:$Rdn, sve_pred_enum:$pattern, 1), 1>;
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def : InstAlias<asm # "\t$Rdn",
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(!cast<Instruction>(NAME) GPR64:$Rdn, 0b11111, 1), 2>;
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}
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2018-06-18 22:47:52 +08:00
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class sve_int_pred_pattern_b<bits<5> opc, string asm, RegisterOperand dt,
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RegisterOperand st>
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: I<(outs dt:$Rdn), (ins st:$_Rdn, sve_pred_enum:$pattern, sve_incdec_imm:$imm4),
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asm, "\t$Rdn, $pattern, mul $imm4",
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"",
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[]>, Sched<[]> {
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bits<5> Rdn;
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bits<5> pattern;
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bits<4> imm4;
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let Inst{31-24} = 0b00000100;
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let Inst{23-22} = opc{4-3};
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let Inst{21} = 0b1;
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let Inst{20} = opc{2};
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let Inst{19-16} = imm4;
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let Inst{15-12} = 0b1111;
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let Inst{11-10} = opc{1-0};
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let Inst{9-5} = pattern;
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let Inst{4-0} = Rdn;
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|
2018-07-02 15:34:52 +08:00
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// Signed 32bit forms require their GPR operand printed.
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let AsmString = !if(!eq(opc{2,0}, 0b00),
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!strconcat(asm, "\t$Rdn, $_Rdn, $pattern, mul $imm4"),
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!strconcat(asm, "\t$Rdn, $pattern, mul $imm4"));
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|
2018-06-18 22:47:52 +08:00
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let Constraints = "$Rdn = $_Rdn";
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}
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|
2018-07-02 15:34:52 +08:00
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multiclass sve_int_pred_pattern_b_s32<bits<5> opc, string asm> {
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def NAME : sve_int_pred_pattern_b<opc, asm, GPR64z, GPR64as32>;
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def : InstAlias<asm # "\t$Rd, $Rn, $pattern",
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(!cast<Instruction>(NAME) GPR64z:$Rd, GPR64as32:$Rn, sve_pred_enum:$pattern, 1), 1>;
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def : InstAlias<asm # "\t$Rd, $Rn",
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(!cast<Instruction>(NAME) GPR64z:$Rd, GPR64as32:$Rn, 0b11111, 1), 2>;
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}
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|
|
multiclass sve_int_pred_pattern_b_u32<bits<5> opc, string asm> {
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def NAME : sve_int_pred_pattern_b<opc, asm, GPR32z, GPR32z>;
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|
|
|
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def : InstAlias<asm # "\t$Rdn, $pattern",
|
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(!cast<Instruction>(NAME) GPR32z:$Rdn, sve_pred_enum:$pattern, 1), 1>;
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|
|
def : InstAlias<asm # "\t$Rdn",
|
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|
|
(!cast<Instruction>(NAME) GPR32z:$Rdn, 0b11111, 1), 2>;
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|
|
}
|
|
|
|
|
2018-06-18 22:47:52 +08:00
|
|
|
multiclass sve_int_pred_pattern_b_x64<bits<5> opc, string asm> {
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|
|
def NAME : sve_int_pred_pattern_b<opc, asm, GPR64z, GPR64z>;
|
|
|
|
|
|
|
|
def : InstAlias<asm # "\t$Rdn, $pattern",
|
|
|
|
(!cast<Instruction>(NAME) GPR64z:$Rdn, sve_pred_enum:$pattern, 1), 1>;
|
|
|
|
def : InstAlias<asm # "\t$Rdn",
|
|
|
|
(!cast<Instruction>(NAME) GPR64z:$Rdn, 0b11111, 1), 2>;
|
|
|
|
}
|
|
|
|
|
2018-06-15 23:47:44 +08:00
|
|
|
|
2017-11-08 00:58:13 +08:00
|
|
|
//===----------------------------------------------------------------------===//
|
2018-01-10 19:32:47 +08:00
|
|
|
// SVE Permute - Cross Lane Group
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
|
|
|
|
class sve_int_perm_dup_r<bits<2> sz8_64, string asm, ZPRRegOp zprty,
|
|
|
|
RegisterClass srcRegType>
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|
|
|
: I<(outs zprty:$Zd), (ins srcRegType:$Rn),
|
|
|
|
asm, "\t$Zd, $Rn",
|
|
|
|
"",
|
|
|
|
[]>, Sched<[]> {
|
|
|
|
bits<5> Rn;
|
|
|
|
bits<5> Zd;
|
|
|
|
let Inst{31-24} = 0b00000101;
|
|
|
|
let Inst{23-22} = sz8_64;
|
|
|
|
let Inst{21-10} = 0b100000001110;
|
|
|
|
let Inst{9-5} = Rn;
|
|
|
|
let Inst{4-0} = Zd;
|
|
|
|
}
|
|
|
|
|
|
|
|
multiclass sve_int_perm_dup_r<string asm> {
|
|
|
|
def _B : sve_int_perm_dup_r<0b00, asm, ZPR8, GPR32sp>;
|
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|
|
def _H : sve_int_perm_dup_r<0b01, asm, ZPR16, GPR32sp>;
|
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|
|
def _S : sve_int_perm_dup_r<0b10, asm, ZPR32, GPR32sp>;
|
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|
|
def _D : sve_int_perm_dup_r<0b11, asm, ZPR64, GPR64sp>;
|
|
|
|
|
|
|
|
def : InstAlias<"mov $Zd, $Rn",
|
|
|
|
(!cast<Instruction>(NAME # _B) ZPR8:$Zd, GPR32sp:$Rn), 1>;
|
|
|
|
def : InstAlias<"mov $Zd, $Rn",
|
|
|
|
(!cast<Instruction>(NAME # _H) ZPR16:$Zd, GPR32sp:$Rn), 1>;
|
|
|
|
def : InstAlias<"mov $Zd, $Rn",
|
|
|
|
(!cast<Instruction>(NAME # _S) ZPR32:$Zd, GPR32sp:$Rn), 1>;
|
|
|
|
def : InstAlias<"mov $Zd, $Rn",
|
|
|
|
(!cast<Instruction>(NAME # _D) ZPR64:$Zd, GPR64sp:$Rn), 1>;
|
|
|
|
}
|
|
|
|
|
2018-06-04 14:40:55 +08:00
|
|
|
class sve_int_perm_dup_i<bits<5> tsz, Operand immtype, string asm,
|
|
|
|
ZPRRegOp zprty>
|
|
|
|
: I<(outs zprty:$Zd), (ins zprty:$Zn, immtype:$idx),
|
|
|
|
asm, "\t$Zd, $Zn$idx",
|
|
|
|
"",
|
|
|
|
[]>, Sched<[]> {
|
|
|
|
bits<5> Zd;
|
|
|
|
bits<5> Zn;
|
|
|
|
bits<7> idx;
|
|
|
|
let Inst{31-24} = 0b00000101;
|
|
|
|
let Inst{23-22} = {?,?}; // imm3h
|
|
|
|
let Inst{21} = 0b1;
|
|
|
|
let Inst{20-16} = tsz;
|
|
|
|
let Inst{15-10} = 0b001000;
|
|
|
|
let Inst{9-5} = Zn;
|
|
|
|
let Inst{4-0} = Zd;
|
|
|
|
}
|
|
|
|
|
|
|
|
multiclass sve_int_perm_dup_i<string asm> {
|
|
|
|
def _B : sve_int_perm_dup_i<{?,?,?,?,1}, sve_elm_idx_extdup_b, asm, ZPR8> {
|
|
|
|
let Inst{23-22} = idx{5-4};
|
|
|
|
let Inst{20-17} = idx{3-0};
|
|
|
|
}
|
|
|
|
def _H : sve_int_perm_dup_i<{?,?,?,1,0}, sve_elm_idx_extdup_h, asm, ZPR16> {
|
|
|
|
let Inst{23-22} = idx{4-3};
|
|
|
|
let Inst{20-18} = idx{2-0};
|
|
|
|
}
|
|
|
|
def _S : sve_int_perm_dup_i<{?,?,1,0,0}, sve_elm_idx_extdup_s, asm, ZPR32> {
|
|
|
|
let Inst{23-22} = idx{3-2};
|
|
|
|
let Inst{20-19} = idx{1-0};
|
|
|
|
}
|
|
|
|
def _D : sve_int_perm_dup_i<{?,1,0,0,0}, sve_elm_idx_extdup_d, asm, ZPR64> {
|
|
|
|
let Inst{23-22} = idx{2-1};
|
|
|
|
let Inst{20} = idx{0};
|
|
|
|
}
|
|
|
|
def _Q : sve_int_perm_dup_i<{1,0,0,0,0}, sve_elm_idx_extdup_q, asm, ZPR128> {
|
|
|
|
let Inst{23-22} = idx{1-0};
|
|
|
|
}
|
|
|
|
|
|
|
|
def : InstAlias<"mov $Zd, $Zn$idx",
|
|
|
|
(!cast<Instruction>(NAME # _B) ZPR8:$Zd, ZPR8:$Zn, sve_elm_idx_extdup_b:$idx), 1>;
|
|
|
|
def : InstAlias<"mov $Zd, $Zn$idx",
|
|
|
|
(!cast<Instruction>(NAME # _H) ZPR16:$Zd, ZPR16:$Zn, sve_elm_idx_extdup_h:$idx), 1>;
|
|
|
|
def : InstAlias<"mov $Zd, $Zn$idx",
|
|
|
|
(!cast<Instruction>(NAME # _S) ZPR32:$Zd, ZPR32:$Zn, sve_elm_idx_extdup_s:$idx), 1>;
|
|
|
|
def : InstAlias<"mov $Zd, $Zn$idx",
|
|
|
|
(!cast<Instruction>(NAME # _D) ZPR64:$Zd, ZPR64:$Zn, sve_elm_idx_extdup_d:$idx), 1>;
|
|
|
|
def : InstAlias<"mov $Zd, $Zn$idx",
|
|
|
|
(!cast<Instruction>(NAME # _Q) ZPR128:$Zd, ZPR128:$Zn, sve_elm_idx_extdup_q:$idx), 1>;
|
2018-06-04 15:07:35 +08:00
|
|
|
def : InstAlias<"mov $Zd, $Bn",
|
|
|
|
(!cast<Instruction>(NAME # _B) ZPR8:$Zd, FPR8asZPR:$Bn, 0), 2>;
|
|
|
|
def : InstAlias<"mov $Zd, $Hn",
|
|
|
|
(!cast<Instruction>(NAME # _H) ZPR16:$Zd, FPR16asZPR:$Hn, 0), 2>;
|
|
|
|
def : InstAlias<"mov $Zd, $Sn",
|
|
|
|
(!cast<Instruction>(NAME # _S) ZPR32:$Zd, FPR32asZPR:$Sn, 0), 2>;
|
|
|
|
def : InstAlias<"mov $Zd, $Dn",
|
|
|
|
(!cast<Instruction>(NAME # _D) ZPR64:$Zd, FPR64asZPR:$Dn, 0), 2>;
|
|
|
|
def : InstAlias<"mov $Zd, $Qn",
|
|
|
|
(!cast<Instruction>(NAME # _Q) ZPR128:$Zd, FPR128asZPR:$Qn, 0), 2>;
|
2018-06-04 14:40:55 +08:00
|
|
|
}
|
|
|
|
|
2018-07-09 20:32:56 +08:00
|
|
|
class sve_int_perm_tbl<bits<2> sz8_64, string asm, ZPRRegOp zprty,
|
|
|
|
RegisterOperand VecList>
|
|
|
|
: I<(outs zprty:$Zd), (ins VecList:$Zn, zprty:$Zm),
|
|
|
|
asm, "\t$Zd, $Zn, $Zm",
|
|
|
|
"",
|
|
|
|
[]>, Sched<[]> {
|
|
|
|
bits<5> Zd;
|
|
|
|
bits<5> Zm;
|
|
|
|
bits<5> Zn;
|
|
|
|
let Inst{31-24} = 0b00000101;
|
|
|
|
let Inst{23-22} = sz8_64;
|
|
|
|
let Inst{21} = 0b1;
|
|
|
|
let Inst{20-16} = Zm;
|
|
|
|
let Inst{15-10} = 0b001100;
|
|
|
|
let Inst{9-5} = Zn;
|
|
|
|
let Inst{4-0} = Zd;
|
|
|
|
}
|
|
|
|
|
|
|
|
multiclass sve_int_perm_tbl<string asm> {
|
|
|
|
def _B : sve_int_perm_tbl<0b00, asm, ZPR8, Z_b>;
|
|
|
|
def _H : sve_int_perm_tbl<0b01, asm, ZPR16, Z_h>;
|
|
|
|
def _S : sve_int_perm_tbl<0b10, asm, ZPR32, Z_s>;
|
|
|
|
def _D : sve_int_perm_tbl<0b11, asm, ZPR64, Z_d>;
|
|
|
|
|
|
|
|
def : InstAlias<asm # "\t$Zd, $Zn, $Zm",
|
|
|
|
(!cast<Instruction>(NAME # _B) ZPR8:$Zd, ZPR8:$Zn, ZPR8:$Zm), 0>;
|
|
|
|
def : InstAlias<asm # "\t$Zd, $Zn, $Zm",
|
|
|
|
(!cast<Instruction>(NAME # _H) ZPR16:$Zd, ZPR16:$Zn, ZPR16:$Zm), 0>;
|
|
|
|
def : InstAlias<asm # "\t$Zd, $Zn, $Zm",
|
|
|
|
(!cast<Instruction>(NAME # _S) ZPR32:$Zd, ZPR32:$Zn, ZPR32:$Zm), 0>;
|
|
|
|
def : InstAlias<asm # "\t$Zd, $Zn, $Zm",
|
|
|
|
(!cast<Instruction>(NAME # _D) ZPR64:$Zd, ZPR64:$Zn, ZPR64:$Zm), 0>;
|
|
|
|
}
|
2018-06-17 18:11:04 +08:00
|
|
|
|
2018-07-13 17:25:43 +08:00
|
|
|
class sve_int_perm_unpk<bits<2> sz16_64, bits<2> opc, string asm,
|
|
|
|
ZPRRegOp zprty1, ZPRRegOp zprty2>
|
|
|
|
: I<(outs zprty1:$Zd), (ins zprty2:$Zn),
|
|
|
|
asm, "\t$Zd, $Zn",
|
|
|
|
"", []>, Sched<[]> {
|
|
|
|
bits<5> Zd;
|
|
|
|
bits<5> Zn;
|
|
|
|
let Inst{31-24} = 0b00000101;
|
|
|
|
let Inst{23-22} = sz16_64;
|
|
|
|
let Inst{21-18} = 0b1100;
|
|
|
|
let Inst{17-16} = opc;
|
|
|
|
let Inst{15-10} = 0b001110;
|
|
|
|
let Inst{9-5} = Zn;
|
|
|
|
let Inst{4-0} = Zd;
|
|
|
|
}
|
|
|
|
|
|
|
|
multiclass sve_int_perm_unpk<bits<2> opc, string asm> {
|
|
|
|
def _H : sve_int_perm_unpk<0b01, opc, asm, ZPR16, ZPR8>;
|
|
|
|
def _S : sve_int_perm_unpk<0b10, opc, asm, ZPR32, ZPR16>;
|
|
|
|
def _D : sve_int_perm_unpk<0b11, opc, asm, ZPR64, ZPR32>;
|
|
|
|
}
|
|
|
|
|
2018-07-13 16:51:57 +08:00
|
|
|
class sve_int_perm_insrs<bits<2> sz8_64, string asm, ZPRRegOp zprty,
|
|
|
|
RegisterClass srcRegType>
|
|
|
|
: I<(outs zprty:$Zdn), (ins zprty:$_Zdn, srcRegType:$Rm),
|
|
|
|
asm, "\t$Zdn, $Rm",
|
|
|
|
"",
|
|
|
|
[]>, Sched<[]> {
|
|
|
|
bits<5> Rm;
|
|
|
|
bits<5> Zdn;
|
|
|
|
let Inst{31-24} = 0b00000101;
|
|
|
|
let Inst{23-22} = sz8_64;
|
|
|
|
let Inst{21-10} = 0b100100001110;
|
|
|
|
let Inst{9-5} = Rm;
|
|
|
|
let Inst{4-0} = Zdn;
|
|
|
|
|
|
|
|
let Constraints = "$Zdn = $_Zdn";
|
|
|
|
}
|
|
|
|
|
|
|
|
multiclass sve_int_perm_insrs<string asm> {
|
|
|
|
def _B : sve_int_perm_insrs<0b00, asm, ZPR8, GPR32>;
|
|
|
|
def _H : sve_int_perm_insrs<0b01, asm, ZPR16, GPR32>;
|
|
|
|
def _S : sve_int_perm_insrs<0b10, asm, ZPR32, GPR32>;
|
|
|
|
def _D : sve_int_perm_insrs<0b11, asm, ZPR64, GPR64>;
|
|
|
|
}
|
|
|
|
|
|
|
|
class sve_int_perm_insrv<bits<2> sz8_64, string asm, ZPRRegOp zprty,
|
|
|
|
RegisterClass srcRegType>
|
|
|
|
: I<(outs zprty:$Zdn), (ins zprty:$_Zdn, srcRegType:$Vm),
|
|
|
|
asm, "\t$Zdn, $Vm",
|
|
|
|
"",
|
|
|
|
[]>, Sched<[]> {
|
|
|
|
bits<5> Vm;
|
|
|
|
bits<5> Zdn;
|
|
|
|
let Inst{31-24} = 0b00000101;
|
|
|
|
let Inst{23-22} = sz8_64;
|
|
|
|
let Inst{21-10} = 0b110100001110;
|
|
|
|
let Inst{9-5} = Vm;
|
|
|
|
let Inst{4-0} = Zdn;
|
|
|
|
|
|
|
|
let Constraints = "$Zdn = $_Zdn";
|
|
|
|
}
|
|
|
|
|
|
|
|
multiclass sve_int_perm_insrv<string asm> {
|
|
|
|
def _B : sve_int_perm_insrv<0b00, asm, ZPR8, FPR8>;
|
|
|
|
def _H : sve_int_perm_insrv<0b01, asm, ZPR16, FPR16>;
|
|
|
|
def _S : sve_int_perm_insrv<0b10, asm, ZPR32, FPR32>;
|
|
|
|
def _D : sve_int_perm_insrv<0b11, asm, ZPR64, FPR64>;
|
|
|
|
}
|
|
|
|
|
2018-07-17 16:39:48 +08:00
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
// SVE Permute - Extract Group
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
|
|
|
|
class sve_int_perm_extract_i<string asm>
|
|
|
|
: I<(outs ZPR8:$Zdn), (ins ZPR8:$_Zdn, ZPR8:$Zm, imm0_255:$imm8),
|
|
|
|
asm, "\t$Zdn, $_Zdn, $Zm, $imm8",
|
|
|
|
"", []>, Sched<[]> {
|
|
|
|
bits<5> Zdn;
|
|
|
|
bits<5> Zm;
|
|
|
|
bits<8> imm8;
|
|
|
|
let Inst{31-21} = 0b00000101001;
|
|
|
|
let Inst{20-16} = imm8{7-3};
|
|
|
|
let Inst{15-13} = 0b000;
|
|
|
|
let Inst{12-10} = imm8{2-0};
|
|
|
|
let Inst{9-5} = Zm;
|
|
|
|
let Inst{4-0} = Zdn;
|
|
|
|
|
|
|
|
let Constraints = "$Zdn = $_Zdn";
|
|
|
|
}
|
2018-07-13 16:51:57 +08:00
|
|
|
|
2018-06-17 18:11:04 +08:00
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
// SVE Vector Select Group
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
|
|
|
|
class sve_int_sel_vvv<bits<2> sz8_64, string asm, ZPRRegOp zprty>
|
|
|
|
: I<(outs zprty:$Zd), (ins PPRAny:$Pg, zprty:$Zn, zprty:$Zm),
|
|
|
|
asm, "\t$Zd, $Pg, $Zn, $Zm",
|
|
|
|
"",
|
|
|
|
[]>, Sched<[]> {
|
|
|
|
bits<4> Pg;
|
|
|
|
bits<5> Zd;
|
|
|
|
bits<5> Zm;
|
|
|
|
bits<5> Zn;
|
|
|
|
let Inst{31-24} = 0b00000101;
|
|
|
|
let Inst{23-22} = sz8_64;
|
|
|
|
let Inst{21} = 0b1;
|
|
|
|
let Inst{20-16} = Zm;
|
|
|
|
let Inst{15-14} = 0b11;
|
|
|
|
let Inst{13-10} = Pg;
|
|
|
|
let Inst{9-5} = Zn;
|
|
|
|
let Inst{4-0} = Zd;
|
|
|
|
}
|
|
|
|
|
|
|
|
multiclass sve_int_sel_vvv<string asm> {
|
|
|
|
def _B : sve_int_sel_vvv<0b00, asm, ZPR8>;
|
|
|
|
def _H : sve_int_sel_vvv<0b01, asm, ZPR16>;
|
|
|
|
def _S : sve_int_sel_vvv<0b10, asm, ZPR32>;
|
|
|
|
def _D : sve_int_sel_vvv<0b11, asm, ZPR64>;
|
|
|
|
|
|
|
|
def : InstAlias<"mov $Zd, $Pg/m, $Zn",
|
|
|
|
(!cast<Instruction>(NAME # _B) ZPR8:$Zd, PPRAny:$Pg, ZPR8:$Zn, ZPR8:$Zd), 1>;
|
|
|
|
def : InstAlias<"mov $Zd, $Pg/m, $Zn",
|
|
|
|
(!cast<Instruction>(NAME # _H) ZPR16:$Zd, PPRAny:$Pg, ZPR16:$Zn, ZPR16:$Zd), 1>;
|
|
|
|
def : InstAlias<"mov $Zd, $Pg/m, $Zn",
|
|
|
|
(!cast<Instruction>(NAME # _S) ZPR32:$Zd, PPRAny:$Pg, ZPR32:$Zn, ZPR32:$Zd), 1>;
|
|
|
|
def : InstAlias<"mov $Zd, $Pg/m, $Zn",
|
|
|
|
(!cast<Instruction>(NAME # _D) ZPR64:$Zd, PPRAny:$Pg, ZPR64:$Zn, ZPR64:$Zd), 1>;
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
// SVE Predicate Logical Operations Group
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
|
|
|
|
class sve_int_pred_log<bits<4> opc, string asm>
|
|
|
|
: I<(outs PPR8:$Pd), (ins PPRAny:$Pg, PPR8:$Pn, PPR8:$Pm),
|
|
|
|
asm, "\t$Pd, $Pg/z, $Pn, $Pm",
|
|
|
|
"",
|
|
|
|
[]>, Sched<[]> {
|
|
|
|
bits<4> Pd;
|
|
|
|
bits<4> Pg;
|
|
|
|
bits<4> Pm;
|
|
|
|
bits<4> Pn;
|
|
|
|
let Inst{31-24} = 0b00100101;
|
|
|
|
let Inst{23-22} = opc{3-2};
|
|
|
|
let Inst{21-20} = 0b00;
|
|
|
|
let Inst{19-16} = Pm;
|
|
|
|
let Inst{15-14} = 0b01;
|
|
|
|
let Inst{13-10} = Pg;
|
|
|
|
let Inst{9} = opc{1};
|
|
|
|
let Inst{8-5} = Pn;
|
|
|
|
let Inst{4} = opc{0};
|
|
|
|
let Inst{3-0} = Pd;
|
|
|
|
|
|
|
|
// SEL has no predication qualifier.
|
|
|
|
let AsmString = !if(!eq(opc, 0b0011),
|
|
|
|
!strconcat(asm, "\t$Pd, $Pg, $Pn, $Pm"),
|
|
|
|
!strconcat(asm, "\t$Pd, $Pg/z, $Pn, $Pm"));
|
|
|
|
|
|
|
|
let Defs = !if(!eq (opc{2}, 1), [NZCV], []);
|
|
|
|
}
|
|
|
|
|
|
|
|
|
2018-02-06 21:13:21 +08:00
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
// SVE Logical Mask Immediate Group
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
|
|
|
|
class sve_int_log_imm<bits<2> opc, string asm>
|
|
|
|
: I<(outs ZPR64:$Zdn), (ins ZPR64:$_Zdn, logical_imm64:$imms13),
|
|
|
|
asm, "\t$Zdn, $_Zdn, $imms13",
|
|
|
|
"", []>, Sched<[]> {
|
|
|
|
bits<5> Zdn;
|
|
|
|
bits<13> imms13;
|
|
|
|
let Inst{31-24} = 0b00000101;
|
|
|
|
let Inst{23-22} = opc;
|
|
|
|
let Inst{21-18} = 0b0000;
|
|
|
|
let Inst{17-5} = imms13;
|
|
|
|
let Inst{4-0} = Zdn;
|
|
|
|
|
|
|
|
let Constraints = "$Zdn = $_Zdn";
|
|
|
|
let DecoderMethod = "DecodeSVELogicalImmInstruction";
|
|
|
|
}
|
|
|
|
|
|
|
|
multiclass sve_int_log_imm<bits<2> opc, string asm, string alias> {
|
|
|
|
def NAME : sve_int_log_imm<opc, asm>;
|
|
|
|
|
|
|
|
def : InstAlias<asm # "\t$Zdn, $Zdn, $imm",
|
|
|
|
(!cast<Instruction>(NAME) ZPR8:$Zdn, sve_logical_imm8:$imm), 4>;
|
|
|
|
def : InstAlias<asm # "\t$Zdn, $Zdn, $imm",
|
|
|
|
(!cast<Instruction>(NAME) ZPR16:$Zdn, sve_logical_imm16:$imm), 3>;
|
|
|
|
def : InstAlias<asm # "\t$Zdn, $Zdn, $imm",
|
|
|
|
(!cast<Instruction>(NAME) ZPR32:$Zdn, sve_logical_imm32:$imm), 2>;
|
|
|
|
|
|
|
|
def : InstAlias<alias # "\t$Zdn, $Zdn, $imm",
|
|
|
|
(!cast<Instruction>(NAME) ZPR8:$Zdn, sve_logical_imm8_not:$imm), 0>;
|
|
|
|
def : InstAlias<alias # "\t$Zdn, $Zdn, $imm",
|
|
|
|
(!cast<Instruction>(NAME) ZPR16:$Zdn, sve_logical_imm16_not:$imm), 0>;
|
|
|
|
def : InstAlias<alias # "\t$Zdn, $Zdn, $imm",
|
|
|
|
(!cast<Instruction>(NAME) ZPR32:$Zdn, sve_logical_imm32_not:$imm), 0>;
|
|
|
|
def : InstAlias<alias # "\t$Zdn, $Zdn, $imm",
|
|
|
|
(!cast<Instruction>(NAME) ZPR64:$Zdn, logical_imm64_not:$imm), 0>;
|
|
|
|
}
|
|
|
|
|
2018-06-01 15:25:46 +08:00
|
|
|
class sve_int_dup_mask_imm<string asm>
|
|
|
|
: I<(outs ZPR64:$Zd), (ins logical_imm64:$imms),
|
|
|
|
asm, "\t$Zd, $imms",
|
|
|
|
"",
|
|
|
|
[]>, Sched<[]> {
|
|
|
|
bits<5> Zd;
|
|
|
|
bits<13> imms;
|
|
|
|
let Inst{31-18} = 0b00000101110000;
|
|
|
|
let Inst{17-5} = imms;
|
|
|
|
let Inst{4-0} = Zd;
|
|
|
|
|
|
|
|
let isReMaterializable = 1;
|
|
|
|
let DecoderMethod = "DecodeSVELogicalImmInstruction";
|
|
|
|
}
|
|
|
|
|
|
|
|
multiclass sve_int_dup_mask_imm<string asm> {
|
|
|
|
def NAME : sve_int_dup_mask_imm<asm>;
|
|
|
|
|
|
|
|
def : InstAlias<"dupm $Zd, $imm",
|
|
|
|
(!cast<Instruction>(NAME) ZPR8:$Zd, sve_logical_imm8:$imm), 4>;
|
|
|
|
def : InstAlias<"dupm $Zd, $imm",
|
|
|
|
(!cast<Instruction>(NAME) ZPR16:$Zd, sve_logical_imm16:$imm), 3>;
|
|
|
|
def : InstAlias<"dupm $Zd, $imm",
|
|
|
|
(!cast<Instruction>(NAME) ZPR32:$Zd, sve_logical_imm32:$imm), 2>;
|
|
|
|
|
|
|
|
// All Zd.b forms have a CPY/DUP equivalent, hence no byte alias here.
|
|
|
|
def : InstAlias<"mov $Zd, $imm",
|
|
|
|
(!cast<Instruction>(NAME) ZPR16:$Zd, sve_preferred_logical_imm16:$imm), 7>;
|
|
|
|
def : InstAlias<"mov $Zd, $imm",
|
|
|
|
(!cast<Instruction>(NAME) ZPR32:$Zd, sve_preferred_logical_imm32:$imm), 6>;
|
|
|
|
def : InstAlias<"mov $Zd, $imm",
|
|
|
|
(!cast<Instruction>(NAME) ZPR64:$Zd, sve_preferred_logical_imm64:$imm), 5>;
|
|
|
|
}
|
|
|
|
|
2018-01-10 19:32:47 +08:00
|
|
|
//===----------------------------------------------------------------------===//
|
2017-12-15 00:09:48 +08:00
|
|
|
// SVE Integer Arithmetic - Unpredicated Group.
|
2017-11-08 00:58:13 +08:00
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
|
|
|
|
class sve_int_bin_cons_arit_0<bits<2> sz8_64, bits<3> opc, string asm,
|
|
|
|
ZPRRegOp zprty>
|
|
|
|
: I<(outs zprty:$Zd), (ins zprty:$Zn, zprty:$Zm),
|
|
|
|
asm, "\t$Zd, $Zn, $Zm",
|
|
|
|
"", []>, Sched<[]> {
|
|
|
|
bits<5> Zd;
|
|
|
|
bits<5> Zm;
|
|
|
|
bits<5> Zn;
|
|
|
|
let Inst{31-24} = 0b00000100;
|
|
|
|
let Inst{23-22} = sz8_64;
|
|
|
|
let Inst{21} = 0b1;
|
|
|
|
let Inst{20-16} = Zm;
|
|
|
|
let Inst{15-13} = 0b000;
|
|
|
|
let Inst{12-10} = opc;
|
|
|
|
let Inst{9-5} = Zn;
|
|
|
|
let Inst{4-0} = Zd;
|
|
|
|
}
|
|
|
|
|
|
|
|
multiclass sve_int_bin_cons_arit_0<bits<3> opc, string asm> {
|
|
|
|
def _B : sve_int_bin_cons_arit_0<0b00, opc, asm, ZPR8>;
|
|
|
|
def _H : sve_int_bin_cons_arit_0<0b01, opc, asm, ZPR16>;
|
|
|
|
def _S : sve_int_bin_cons_arit_0<0b10, opc, asm, ZPR32>;
|
|
|
|
def _D : sve_int_bin_cons_arit_0<0b11, opc, asm, ZPR64>;
|
|
|
|
}
|
2017-12-20 19:02:42 +08:00
|
|
|
|
2018-06-15 21:57:51 +08:00
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
// SVE Floating Point Arithmetic - Predicated Group
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
|
|
|
|
class sve_fp_2op_i_p_zds<bits<2> sz, bits<3> opc, string asm,
|
|
|
|
ZPRRegOp zprty,
|
|
|
|
Operand imm_ty>
|
|
|
|
: I<(outs zprty:$Zdn), (ins PPR3bAny:$Pg, zprty:$_Zdn, imm_ty:$i1),
|
|
|
|
asm, "\t$Zdn, $Pg/m, $_Zdn, $i1",
|
|
|
|
"",
|
|
|
|
[]>, Sched<[]> {
|
|
|
|
bits<3> Pg;
|
|
|
|
bits<5> Zdn;
|
|
|
|
bit i1;
|
|
|
|
let Inst{31-24} = 0b01100101;
|
|
|
|
let Inst{23-22} = sz;
|
|
|
|
let Inst{21-19} = 0b011;
|
|
|
|
let Inst{18-16} = opc;
|
|
|
|
let Inst{15-13} = 0b100;
|
|
|
|
let Inst{12-10} = Pg;
|
|
|
|
let Inst{9-6} = 0b0000;
|
|
|
|
let Inst{5} = i1;
|
|
|
|
let Inst{4-0} = Zdn;
|
|
|
|
|
|
|
|
let Constraints = "$Zdn = $_Zdn";
|
|
|
|
}
|
|
|
|
|
|
|
|
multiclass sve_fp_2op_i_p_zds<bits<3> opc, string asm, Operand imm_ty> {
|
|
|
|
def _H : sve_fp_2op_i_p_zds<0b01, opc, asm, ZPR16, imm_ty>;
|
|
|
|
def _S : sve_fp_2op_i_p_zds<0b10, opc, asm, ZPR32, imm_ty>;
|
|
|
|
def _D : sve_fp_2op_i_p_zds<0b11, opc, asm, ZPR64, imm_ty>;
|
|
|
|
}
|
|
|
|
|
2018-07-17 17:48:57 +08:00
|
|
|
class sve_fp_2op_p_zds<bits<2> sz, bits<4> opc, string asm,
|
|
|
|
ZPRRegOp zprty>
|
|
|
|
: I<(outs zprty:$Zdn), (ins PPR3bAny:$Pg, zprty:$_Zdn, zprty:$Zm),
|
|
|
|
asm, "\t$Zdn, $Pg/m, $_Zdn, $Zm",
|
|
|
|
"",
|
|
|
|
[]>, Sched<[]> {
|
|
|
|
bits<3> Pg;
|
|
|
|
bits<5> Zdn;
|
|
|
|
bits<5> Zm;
|
|
|
|
let Inst{31-24} = 0b01100101;
|
|
|
|
let Inst{23-22} = sz;
|
|
|
|
let Inst{21-20} = 0b00;
|
|
|
|
let Inst{19-16} = opc;
|
|
|
|
let Inst{15-13} = 0b100;
|
|
|
|
let Inst{12-10} = Pg;
|
|
|
|
let Inst{9-5} = Zm;
|
|
|
|
let Inst{4-0} = Zdn;
|
|
|
|
|
|
|
|
let Constraints = "$Zdn = $_Zdn";
|
|
|
|
}
|
|
|
|
|
|
|
|
multiclass sve_fp_2op_p_zds<bits<4> opc, string asm> {
|
|
|
|
def _H : sve_fp_2op_p_zds<0b01, opc, asm, ZPR16>;
|
|
|
|
def _S : sve_fp_2op_p_zds<0b10, opc, asm, ZPR32>;
|
|
|
|
def _D : sve_fp_2op_p_zds<0b11, opc, asm, ZPR64>;
|
|
|
|
}
|
|
|
|
|
|
|
|
|
2018-07-17 21:58:46 +08:00
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
// SVE Floating Point Fused Multiply-Add Group
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
|
|
|
|
class sve_fp_3op_p_zds_a<bits<2> sz, bits<2> opc, string asm, ZPRRegOp zprty>
|
|
|
|
: I<(outs zprty:$Zda), (ins PPR3bAny:$Pg, zprty:$_Zda, zprty:$Zn, zprty:$Zm),
|
|
|
|
asm, "\t$Zda, $Pg/m, $Zn, $Zm",
|
|
|
|
"",
|
|
|
|
[]>, Sched<[]> {
|
|
|
|
bits<3> Pg;
|
|
|
|
bits<5> Zda;
|
|
|
|
bits<5> Zm;
|
|
|
|
bits<5> Zn;
|
|
|
|
let Inst{31-24} = 0b01100101;
|
|
|
|
let Inst{23-22} = sz;
|
|
|
|
let Inst{21} = 0b1;
|
|
|
|
let Inst{20-16} = Zm;
|
|
|
|
let Inst{15} = 0b0;
|
|
|
|
let Inst{14-13} = opc;
|
|
|
|
let Inst{12-10} = Pg;
|
|
|
|
let Inst{9-5} = Zn;
|
|
|
|
let Inst{4-0} = Zda;
|
|
|
|
|
|
|
|
let Constraints = "$Zda = $_Zda";
|
|
|
|
}
|
|
|
|
|
|
|
|
multiclass sve_fp_3op_p_zds_a<bits<2> opc, string asm> {
|
|
|
|
def _H : sve_fp_3op_p_zds_a<0b01, opc, asm, ZPR16>;
|
|
|
|
def _S : sve_fp_3op_p_zds_a<0b10, opc, asm, ZPR32>;
|
|
|
|
def _D : sve_fp_3op_p_zds_a<0b11, opc, asm, ZPR64>;
|
|
|
|
}
|
|
|
|
|
|
|
|
class sve_fp_3op_p_zds_b<bits<2> sz, bits<2> opc, string asm,
|
|
|
|
ZPRRegOp zprty>
|
|
|
|
: I<(outs zprty:$Zdn), (ins PPR3bAny:$Pg, zprty:$_Zdn, zprty:$Zm, zprty:$Za),
|
|
|
|
asm, "\t$Zdn, $Pg/m, $Zm, $Za",
|
|
|
|
"",
|
|
|
|
[]>, Sched<[]> {
|
|
|
|
bits<3> Pg;
|
|
|
|
bits<5> Za;
|
|
|
|
bits<5> Zdn;
|
|
|
|
bits<5> Zm;
|
|
|
|
let Inst{31-24} = 0b01100101;
|
|
|
|
let Inst{23-22} = sz;
|
|
|
|
let Inst{21} = 0b1;
|
|
|
|
let Inst{20-16} = Za;
|
|
|
|
let Inst{15} = 0b1;
|
|
|
|
let Inst{14-13} = opc;
|
|
|
|
let Inst{12-10} = Pg;
|
|
|
|
let Inst{9-5} = Zm;
|
|
|
|
let Inst{4-0} = Zdn;
|
|
|
|
|
|
|
|
let Constraints = "$Zdn = $_Zdn";
|
|
|
|
}
|
|
|
|
|
|
|
|
multiclass sve_fp_3op_p_zds_b<bits<2> opc, string asm> {
|
|
|
|
def _H : sve_fp_3op_p_zds_b<0b01, opc, asm, ZPR16>;
|
|
|
|
def _S : sve_fp_3op_p_zds_b<0b10, opc, asm, ZPR32>;
|
|
|
|
def _D : sve_fp_3op_p_zds_b<0b11, opc, asm, ZPR64>;
|
|
|
|
}
|
|
|
|
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
// SVE Floating Point Multiply-Add - Indexed Group
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
|
|
|
|
class sve_fp_fma_by_indexed_elem<bits<2> sz, bit opc, string asm,
|
|
|
|
ZPRRegOp zprty1,
|
|
|
|
ZPRRegOp zprty2, Operand itype>
|
|
|
|
: I<(outs zprty1:$Zda), (ins zprty1:$_Zda, zprty1:$Zn, zprty2:$Zm, itype:$iop),
|
|
|
|
asm, "\t$Zda, $Zn, $Zm$iop", "", []>, Sched<[]> {
|
|
|
|
bits<5> Zda;
|
|
|
|
bits<5> Zn;
|
|
|
|
let Inst{31-24} = 0b01100100;
|
|
|
|
let Inst{23-22} = sz;
|
|
|
|
let Inst{21} = 0b1;
|
|
|
|
let Inst{15-11} = 0;
|
|
|
|
let Inst{10} = opc;
|
|
|
|
let Inst{9-5} = Zn;
|
|
|
|
let Inst{4-0} = Zda;
|
|
|
|
|
|
|
|
let Constraints = "$Zda = $_Zda";
|
|
|
|
}
|
|
|
|
|
|
|
|
multiclass sve_fp_fma_by_indexed_elem<bit opc, string asm> {
|
|
|
|
def _H : sve_fp_fma_by_indexed_elem<{0, ?}, opc, asm, ZPR16, ZPR3b16, VectorIndexH> {
|
|
|
|
bits<3> Zm;
|
|
|
|
bits<3> iop;
|
|
|
|
let Inst{22} = iop{2};
|
|
|
|
let Inst{20-19} = iop{1-0};
|
|
|
|
let Inst{18-16} = Zm;
|
|
|
|
}
|
|
|
|
def _S : sve_fp_fma_by_indexed_elem<0b10, opc, asm, ZPR32, ZPR3b32, VectorIndexS> {
|
|
|
|
bits<3> Zm;
|
|
|
|
bits<2> iop;
|
|
|
|
let Inst{20-19} = iop;
|
|
|
|
let Inst{18-16} = Zm;
|
|
|
|
}
|
|
|
|
def _D : sve_fp_fma_by_indexed_elem<0b11, opc, asm, ZPR64, ZPR4b64, VectorIndexD> {
|
|
|
|
bits<4> Zm;
|
|
|
|
bit iop;
|
|
|
|
let Inst{20} = iop;
|
|
|
|
let Inst{19-16} = Zm;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
|
2018-07-03 23:31:04 +08:00
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
// SVE Floating Point Multiply - Indexed Group
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
|
|
|
|
class sve_fp_fmul_by_indexed_elem<bits<2> sz, string asm, ZPRRegOp zprty,
|
|
|
|
ZPRRegOp zprty2, Operand itype>
|
|
|
|
: I<(outs zprty:$Zd), (ins zprty:$Zn, zprty2:$Zm, itype:$iop),
|
|
|
|
asm, "\t$Zd, $Zn, $Zm$iop", "", []>, Sched<[]> {
|
|
|
|
bits<5> Zd;
|
|
|
|
bits<5> Zn;
|
|
|
|
let Inst{31-24} = 0b01100100;
|
|
|
|
let Inst{23-22} = sz;
|
|
|
|
let Inst{21} = 0b1;
|
|
|
|
let Inst{15-10} = 0b001000;
|
|
|
|
let Inst{9-5} = Zn;
|
|
|
|
let Inst{4-0} = Zd;
|
|
|
|
}
|
|
|
|
|
|
|
|
multiclass sve_fp_fmul_by_indexed_elem<string asm> {
|
|
|
|
def _H : sve_fp_fmul_by_indexed_elem<{0, ?}, asm, ZPR16, ZPR3b16, VectorIndexH> {
|
|
|
|
bits<3> Zm;
|
|
|
|
bits<3> iop;
|
|
|
|
let Inst{22} = iop{2};
|
|
|
|
let Inst{20-19} = iop{1-0};
|
|
|
|
let Inst{18-16} = Zm;
|
|
|
|
}
|
|
|
|
def _S : sve_fp_fmul_by_indexed_elem<0b10, asm, ZPR32, ZPR3b32, VectorIndexS> {
|
|
|
|
bits<3> Zm;
|
|
|
|
bits<2> iop;
|
|
|
|
let Inst{20-19} = iop;
|
|
|
|
let Inst{18-16} = Zm;
|
|
|
|
}
|
|
|
|
def _D : sve_fp_fmul_by_indexed_elem<0b11, asm, ZPR64, ZPR4b64, VectorIndexD> {
|
|
|
|
bits<4> Zm;
|
|
|
|
bit iop;
|
|
|
|
let Inst{20} = iop;
|
|
|
|
let Inst{19-16} = Zm;
|
|
|
|
}
|
|
|
|
}
|
2018-06-15 21:57:51 +08:00
|
|
|
|
[AArch64][SVE] Asm: Support for FP Complex ADD/MLA.
The variants added in this patch are:
- Predicated Complex floating point ADD with rotate, e.g.
fcadd z0.h, p0/m, z0.h, z1.h, #90
- Predicated Complex floating point MLA with rotate, e.g.
fcmla z0.h, p0/m, z1.h, z2.h, #180
- Unpredicated Complex floating point MLA with rotate (indexed operand), e.g.
fcmla z0.h, p0/m, z1.h, z2.h[0], #180
Reviewers: rengolin, fhahn, SjoerdMeijer, samparker, javed.absar
Reviewed By: fhahn
Differential Revision: https://reviews.llvm.org/D48824
llvm-svn: 336210
2018-07-04 00:01:27 +08:00
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//===----------------------------------------------------------------------===//
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// SVE Floating Point Complex Multiply-Add Group
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//===----------------------------------------------------------------------===//
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class sve_fp_fcmla<bits<2> sz, string asm, ZPRRegOp zprty>
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: I<(outs zprty:$Zda), (ins PPR3bAny:$Pg, zprty:$_Zda, zprty:$Zn, zprty:$Zm,
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complexrotateop:$imm),
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asm, "\t$Zda, $Pg/m, $Zn, $Zm, $imm",
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"", []>, Sched<[]> {
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bits<5> Zda;
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bits<3> Pg;
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bits<5> Zn;
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bits<5> Zm;
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bits<2> imm;
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let Inst{31-24} = 0b01100100;
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let Inst{23-22} = sz;
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let Inst{21} = 0;
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let Inst{20-16} = Zm;
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let Inst{15} = 0;
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let Inst{14-13} = imm;
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let Inst{12-10} = Pg;
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let Inst{9-5} = Zn;
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let Inst{4-0} = Zda;
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let Constraints = "$Zda = $_Zda";
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}
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multiclass sve_fp_fcmla<string asm> {
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def _H : sve_fp_fcmla<0b01, asm, ZPR16>;
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def _S : sve_fp_fcmla<0b10, asm, ZPR32>;
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def _D : sve_fp_fcmla<0b11, asm, ZPR64>;
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}
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//===----------------------------------------------------------------------===//
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// SVE Floating Point Complex Multiply-Add - Indexed Group
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//===----------------------------------------------------------------------===//
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class sve_fp_fcmla_by_indexed_elem<bits<2> sz, string asm,
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ZPRRegOp zprty,
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ZPRRegOp zprty2, Operand itype>
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: I<(outs zprty:$Zda), (ins zprty:$_Zda, zprty:$Zn, zprty2:$Zm, itype:$iop,
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complexrotateop:$imm),
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asm, "\t$Zda, $Zn, $Zm$iop, $imm",
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"", []>, Sched<[]> {
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bits<5> Zda;
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bits<5> Zn;
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bits<2> imm;
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let Inst{31-24} = 0b01100100;
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let Inst{23-22} = sz;
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let Inst{21} = 0b1;
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let Inst{15-12} = 0b0001;
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let Inst{11-10} = imm;
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let Inst{9-5} = Zn;
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let Inst{4-0} = Zda;
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let Constraints = "$Zda = $_Zda";
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}
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multiclass sve_fp_fcmla_by_indexed_elem<string asm> {
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def _H : sve_fp_fcmla_by_indexed_elem<0b10, asm, ZPR16, ZPR3b16, VectorIndexS> {
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bits<3> Zm;
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bits<2> iop;
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let Inst{20-19} = iop;
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let Inst{18-16} = Zm;
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}
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def _S : sve_fp_fcmla_by_indexed_elem<0b11, asm, ZPR32, ZPR4b32, VectorIndexD> {
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bits<4> Zm;
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bits<1> iop;
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let Inst{20} = iop;
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let Inst{19-16} = Zm;
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}
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}
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//===----------------------------------------------------------------------===//
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// SVE Floating Point Complex Addition Group
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//===----------------------------------------------------------------------===//
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class sve_fp_fcadd<bits<2> sz, string asm, ZPRRegOp zprty>
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: I<(outs zprty:$Zdn), (ins PPR3bAny:$Pg, zprty:$_Zdn, zprty:$Zm,
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complexrotateopodd:$imm),
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asm, "\t$Zdn, $Pg/m, $_Zdn, $Zm, $imm",
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"",
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[]>, Sched<[]> {
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bits<5> Zdn;
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bits<5> Zm;
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bits<3> Pg;
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bit imm;
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let Inst{31-24} = 0b01100100;
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let Inst{23-22} = sz;
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let Inst{21-17} = 0;
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let Inst{16} = imm;
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let Inst{15-13} = 0b100;
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let Inst{12-10} = Pg;
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let Inst{9-5} = Zm;
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let Inst{4-0} = Zdn;
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let Constraints = "$Zdn = $_Zdn";
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}
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multiclass sve_fp_fcadd<string asm> {
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def _H : sve_fp_fcadd<0b01, asm, ZPR16>;
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def _S : sve_fp_fcadd<0b10, asm, ZPR32>;
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def _D : sve_fp_fcadd<0b11, asm, ZPR64>;
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}
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[AArch64][SVE] Asm: Add support for RDVL/ADDVL/ADDPL instructions
Reviewers: fhahn, rengolin, t.p.northover, echristo, olista01, SjoerdMeijer
Reviewed By: SjoerdMeijer
Subscribers: SjoerdMeijer, aemerson, javed.absar, tschuett, kristof.beyls, llvm-commits
Differential Revision: https://reviews.llvm.org/D41900
llvm-svn: 322951
2018-01-19 23:22:00 +08:00
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//===----------------------------------------------------------------------===//
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// SVE Stack Allocation Group
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//===----------------------------------------------------------------------===//
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class sve_int_arith_vl<bit opc, string asm>
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: I<(outs GPR64sp:$Rd), (ins GPR64sp:$Rn, simm6_32b:$imm6),
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asm, "\t$Rd, $Rn, $imm6",
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"",
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[]>, Sched<[]> {
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bits<5> Rd;
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bits<5> Rn;
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bits<6> imm6;
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let Inst{31-23} = 0b000001000;
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let Inst{22} = opc;
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let Inst{21} = 0b1;
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let Inst{20-16} = Rn;
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let Inst{15-11} = 0b01010;
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let Inst{10-5} = imm6;
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let Inst{4-0} = Rd;
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}
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class sve_int_read_vl_a<bit op, bits<5> opc2, string asm>
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: I<(outs GPR64:$Rd), (ins simm6_32b:$imm6),
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asm, "\t$Rd, $imm6",
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"",
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[]>, Sched<[]> {
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bits<5> Rd;
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bits<6> imm6;
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let Inst{31-23} = 0b000001001;
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let Inst{22} = op;
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let Inst{21} = 0b1;
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let Inst{20-16} = opc2{4-0};
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let Inst{15-11} = 0b01010;
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let Inst{10-5} = imm6;
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let Inst{4-0} = Rd;
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}
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2017-12-20 19:02:42 +08:00
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//===----------------------------------------------------------------------===//
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// SVE Permute - In Lane Group
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//===----------------------------------------------------------------------===//
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class sve_int_perm_bin_perm_zz<bits<3> opc, bits<2> sz8_64, string asm,
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ZPRRegOp zprty>
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: I<(outs zprty:$Zd), (ins zprty:$Zn, zprty:$Zm),
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asm, "\t$Zd, $Zn, $Zm",
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"",
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[]>, Sched<[]> {
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bits<5> Zd;
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bits<5> Zm;
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bits<5> Zn;
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let Inst{31-24} = 0b00000101;
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let Inst{23-22} = sz8_64;
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let Inst{21} = 0b1;
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let Inst{20-16} = Zm;
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let Inst{15-13} = 0b011;
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let Inst{12-10} = opc;
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let Inst{9-5} = Zn;
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let Inst{4-0} = Zd;
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}
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multiclass sve_int_perm_bin_perm_zz<bits<3> opc, string asm> {
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def _B : sve_int_perm_bin_perm_zz<opc, 0b00, asm, ZPR8>;
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def _H : sve_int_perm_bin_perm_zz<opc, 0b01, asm, ZPR16>;
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def _S : sve_int_perm_bin_perm_zz<opc, 0b10, asm, ZPR32>;
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def _D : sve_int_perm_bin_perm_zz<opc, 0b11, asm, ZPR64>;
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}
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[AArch64][SVE] Asm: Support for FP conversion instructions.
The variants added are:
- fcvt (FP convert precision)
- scvtf (signed int -> FP)
- ucvtf (unsigned int -> FP)
- fcvtzs (FP -> signed int (round to zero))
- fcvtzu (FP -> unsigned int (round to zero))
For example:
fcvt z0.h, p0/m, z0.s (single- to half-precision FP)
scvtf z0.h, p0/m, z0.s (32-bit int to half-precision FP)
ucvtf z0.h, p0/m, z0.s (32-bit unsigned int to half-precision FP)
fcvtzs z0.s, p0/m, z0.h (half-precision FP to 32-bit int)
fcvtzu z0.s, p0/m, z0.h (half-precision FP to 32-bit unsigned int)
llvm-svn: 336265
2018-07-04 20:13:17 +08:00
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//===----------------------------------------------------------------------===//
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// SVE Floating Point Unary Operations Group
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//===----------------------------------------------------------------------===//
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class sve_fp_2op_p_zd<bits<7> opc, string asm, RegisterOperand i_zprtype,
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RegisterOperand o_zprtype>
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: I<(outs o_zprtype:$Zd), (ins i_zprtype:$_Zd, PPR3bAny:$Pg, i_zprtype:$Zn),
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asm, "\t$Zd, $Pg/m, $Zn",
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"",
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[]>, Sched<[]> {
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bits<3> Pg;
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bits<5> Zd;
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bits<5> Zn;
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let Inst{31-24} = 0b01100101;
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let Inst{23-22} = opc{6-5};
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let Inst{21} = 0b0;
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let Inst{20-16} = opc{4-0};
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let Inst{15-13} = 0b101;
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let Inst{12-10} = Pg;
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let Inst{9-5} = Zn;
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let Inst{4-0} = Zd;
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let Constraints = "$Zd = $_Zd";
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}
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2018-07-06 04:21:21 +08:00
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multiclass sve_fp_2op_p_zd_HSD<bits<5> opc, string asm> {
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def _H : sve_fp_2op_p_zd<{ 0b01, opc }, asm, ZPR16, ZPR16>;
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def _S : sve_fp_2op_p_zd<{ 0b10, opc }, asm, ZPR32, ZPR32>;
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def _D : sve_fp_2op_p_zd<{ 0b11, opc }, asm, ZPR64, ZPR64>;
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}
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2017-12-20 19:02:42 +08:00
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//===----------------------------------------------------------------------===//
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2018-01-10 01:01:27 +08:00
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// SVE Integer Arithmetic - Binary Predicated Group
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//===----------------------------------------------------------------------===//
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class sve_int_bin_pred_arit_log<bits<2> sz8_64, bits<2> fmt, bits<3> opc,
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string asm, ZPRRegOp zprty>
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: I<(outs zprty:$Zdn), (ins PPR3bAny:$Pg, zprty:$_Zdn, zprty:$Zm),
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asm, "\t$Zdn, $Pg/m, $_Zdn, $Zm", "", []>, Sched<[]> {
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bits<3> Pg;
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bits<5> Zdn;
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bits<5> Zm;
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let Inst{31-24} = 0b00000100;
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let Inst{23-22} = sz8_64;
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let Inst{21} = 0b0;
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let Inst{20-19} = fmt;
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let Inst{18-16} = opc;
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let Inst{15-13} = 0b000;
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let Inst{12-10} = Pg;
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let Inst{9-5} = Zm;
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let Inst{4-0} = Zdn;
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let Constraints = "$Zdn = $_Zdn";
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}
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[AArch64][SVE] Asm: Support for AND, ORR, EOR and BIC instructions.
This patch addresses the following variants:
- bitmask immediate, e.g. 'and z0.d, z0.d, #0x6'.
- unpredicated data vectors, e.g. 'and z0.d, z1.d, z2.d'.
- predicated data vectors, e.g. 'and z0.d, p0/m, z0.d, z1.d'.
And also several aliases, such as:
- ORN, alias of ORR.
- EON, alias of EOR.
- BIC, alias of AND (immediate variant)
- MOV, alias of ORR (if unpredicated and source register operands are the same)
Reviewers: rengolin, huntergr, fhahn, samparker, SjoerdMeijer, javed.absar
Reviewed By: fhahn
Differential Revision: https://reviews.llvm.org/D47363
llvm-svn: 333414
2018-05-29 21:08:43 +08:00
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multiclass sve_int_bin_pred_log<bits<3> opc, string asm> {
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def _B : sve_int_bin_pred_arit_log<0b00, 0b11, opc, asm, ZPR8>;
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def _H : sve_int_bin_pred_arit_log<0b01, 0b11, opc, asm, ZPR16>;
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def _S : sve_int_bin_pred_arit_log<0b10, 0b11, opc, asm, ZPR32>;
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def _D : sve_int_bin_pred_arit_log<0b11, 0b11, opc, asm, ZPR64>;
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}
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2018-01-10 01:01:27 +08:00
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multiclass sve_int_bin_pred_arit_0<bits<3> opc, string asm> {
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def _B : sve_int_bin_pred_arit_log<0b00, 0b00, opc, asm, ZPR8>;
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def _H : sve_int_bin_pred_arit_log<0b01, 0b00, opc, asm, ZPR16>;
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def _S : sve_int_bin_pred_arit_log<0b10, 0b00, opc, asm, ZPR32>;
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def _D : sve_int_bin_pred_arit_log<0b11, 0b00, opc, asm, ZPR64>;
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}
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[AArch64][SVE] Asm: Support for signed/unsigned MIN/MAX/ABD
This patch implements the following varieties:
- Unpredicated signed max, e.g. smax z0.h, z1.h, #-128
- Unpredicated signed min, e.g. smin z0.h, z1.h, #-128
- Unpredicated unsigned max, e.g. umax z0.h, z1.h, #255
- Unpredicated unsigned min, e.g. umin z0.h, z1.h, #255
- Predicated signed max, e.g. smax z0.h, p0/m, z0.h, z1.h
- Predicated signed min, e.g. smin z0.h, p0/m, z0.h, z1.h
- Predicated signed abd, e.g. sabd z0.h, p0/m, z0.h, z1.h
- Predicated unsigned max, e.g. umax z0.h, p0/m, z0.h, z1.h
- Predicated unsigned min, e.g. umin z0.h, p0/m, z0.h, z1.h
- Predicated unsigned abd, e.g. uabd z0.h, p0/m, z0.h, z1.h
llvm-svn: 336317
2018-07-05 15:54:10 +08:00
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multiclass sve_int_bin_pred_arit_1<bits<3> opc, string asm> {
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def _B : sve_int_bin_pred_arit_log<0b00, 0b01, opc, asm, ZPR8>;
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def _H : sve_int_bin_pred_arit_log<0b01, 0b01, opc, asm, ZPR16>;
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def _S : sve_int_bin_pred_arit_log<0b10, 0b01, opc, asm, ZPR32>;
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def _D : sve_int_bin_pred_arit_log<0b11, 0b01, opc, asm, ZPR64>;
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}
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[AArch64][SVE] Asm: Support for integer MUL instructions.
This patch adds the following instructions:
MUL - multiply vectors, e.g.
mul z0.h, p0/m, z0.h, z1.h
- multiply with immediate, e.g.
mul z0.h, z0.h, #127
SMULH - signed multiply returning high half, e.g.
smulh z0.h, p0/m, z0.h, z1.h
UMULH - unsigned multiply returning high half, e.g.
umulh z0.h, p0/m, z0.h, z1.h
llvm-svn: 337358
2018-07-18 16:10:03 +08:00
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multiclass sve_int_bin_pred_arit_2<bits<3> opc, string asm> {
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def _B : sve_int_bin_pred_arit_log<0b00, 0b10, opc, asm, ZPR8>;
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def _H : sve_int_bin_pred_arit_log<0b01, 0b10, opc, asm, ZPR16>;
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def _S : sve_int_bin_pred_arit_log<0b10, 0b10, opc, asm, ZPR32>;
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def _D : sve_int_bin_pred_arit_log<0b11, 0b10, opc, asm, ZPR64>;
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}
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2018-07-17 23:41:58 +08:00
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|
//===----------------------------------------------------------------------===//
|
|
|
|
// SVE Integer Multiply-Add Group
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
|
|
|
|
class sve_int_mladdsub_vvv_pred<bits<2> sz8_64, bits<1> opc, string asm,
|
|
|
|
ZPRRegOp zprty>
|
|
|
|
: I<(outs zprty:$Zdn), (ins PPR3bAny:$Pg, zprty:$_Zdn, zprty:$Zm, zprty:$Za),
|
|
|
|
asm, "\t$Zdn, $Pg/m, $Zm, $Za",
|
|
|
|
"",
|
|
|
|
[]>, Sched<[]> {
|
|
|
|
bits<3> Pg;
|
|
|
|
bits<5> Zdn;
|
|
|
|
bits<5> Za;
|
|
|
|
bits<5> Zm;
|
|
|
|
let Inst{31-24} = 0b00000100;
|
|
|
|
let Inst{23-22} = sz8_64;
|
|
|
|
let Inst{21} = 0b0;
|
|
|
|
let Inst{20-16} = Zm;
|
|
|
|
let Inst{15-14} = 0b11;
|
|
|
|
let Inst{13} = opc;
|
|
|
|
let Inst{12-10} = Pg;
|
|
|
|
let Inst{9-5} = Za;
|
|
|
|
let Inst{4-0} = Zdn;
|
|
|
|
|
|
|
|
let Constraints = "$Zdn = $_Zdn";
|
|
|
|
}
|
|
|
|
|
|
|
|
multiclass sve_int_mladdsub_vvv_pred<bits<1> opc, string asm> {
|
|
|
|
def _B : sve_int_mladdsub_vvv_pred<0b00, opc, asm, ZPR8>;
|
|
|
|
def _H : sve_int_mladdsub_vvv_pred<0b01, opc, asm, ZPR16>;
|
|
|
|
def _S : sve_int_mladdsub_vvv_pred<0b10, opc, asm, ZPR32>;
|
|
|
|
def _D : sve_int_mladdsub_vvv_pred<0b11, opc, asm, ZPR64>;
|
|
|
|
}
|
|
|
|
|
|
|
|
class sve_int_mlas_vvv_pred<bits<2> sz8_64, bits<1> opc, string asm,
|
|
|
|
ZPRRegOp zprty>
|
|
|
|
: I<(outs zprty:$Zda), (ins PPR3bAny:$Pg, zprty:$_Zda, zprty:$Zn, zprty:$Zm),
|
|
|
|
asm, "\t$Zda, $Pg/m, $Zn, $Zm",
|
|
|
|
"",
|
|
|
|
[]>, Sched<[]> {
|
|
|
|
bits<3> Pg;
|
|
|
|
bits<5> Zda;
|
|
|
|
bits<5> Zm;
|
|
|
|
bits<5> Zn;
|
|
|
|
let Inst{31-24} = 0b00000100;
|
|
|
|
let Inst{23-22} = sz8_64;
|
|
|
|
let Inst{21} = 0b0;
|
|
|
|
let Inst{20-16} = Zm;
|
|
|
|
let Inst{15-14} = 0b01;
|
|
|
|
let Inst{13} = opc;
|
|
|
|
let Inst{12-10} = Pg;
|
|
|
|
let Inst{9-5} = Zn;
|
|
|
|
let Inst{4-0} = Zda;
|
|
|
|
|
|
|
|
let Constraints = "$Zda = $_Zda";
|
|
|
|
}
|
|
|
|
|
|
|
|
multiclass sve_int_mlas_vvv_pred<bits<1> opc, string asm> {
|
|
|
|
def _B : sve_int_mlas_vvv_pred<0b00, opc, asm, ZPR8>;
|
|
|
|
def _H : sve_int_mlas_vvv_pred<0b01, opc, asm, ZPR16>;
|
|
|
|
def _S : sve_int_mlas_vvv_pred<0b10, opc, asm, ZPR32>;
|
|
|
|
def _D : sve_int_mlas_vvv_pred<0b11, opc, asm, ZPR64>;
|
|
|
|
}
|
|
|
|
|
[AArch64][SVE] Asm: Support for predicated unary operations.
The patch includes support for the following instructions:
ABS z0.h, p0/m, z0.h
NEG z0.h, p0/m, z0.h
(S|U)XTB z0.h, p0/m, z0.h
(S|U)XTB z0.s, p0/m, z0.s
(S|U)XTB z0.d, p0/m, z0.d
(S|U)XTH z0.s, p0/m, z0.s
(S|U)XTH z0.d, p0/m, z0.d
(S|U)XTW z0.d, p0/m, z0.d
llvm-svn: 336204
2018-07-03 22:57:48 +08:00
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
// SVE Integer Arithmetic - Unary Predicated Group
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
|
2018-07-10 22:05:55 +08:00
|
|
|
class sve_int_un_pred_arit<bits<2> sz8_64, bits<4> opc,
|
|
|
|
string asm, ZPRRegOp zprty>
|
[AArch64][SVE] Asm: Support for predicated unary operations.
The patch includes support for the following instructions:
ABS z0.h, p0/m, z0.h
NEG z0.h, p0/m, z0.h
(S|U)XTB z0.h, p0/m, z0.h
(S|U)XTB z0.s, p0/m, z0.s
(S|U)XTB z0.d, p0/m, z0.d
(S|U)XTH z0.s, p0/m, z0.s
(S|U)XTH z0.d, p0/m, z0.d
(S|U)XTW z0.d, p0/m, z0.d
llvm-svn: 336204
2018-07-03 22:57:48 +08:00
|
|
|
: I<(outs zprty:$Zd), (ins zprty:$_Zd, PPR3bAny:$Pg, zprty:$Zn),
|
|
|
|
asm, "\t$Zd, $Pg/m, $Zn",
|
|
|
|
"",
|
|
|
|
[]>, Sched<[]> {
|
|
|
|
bits<3> Pg;
|
|
|
|
bits<5> Zd;
|
|
|
|
bits<5> Zn;
|
|
|
|
let Inst{31-24} = 0b00000100;
|
|
|
|
let Inst{23-22} = sz8_64;
|
2018-07-10 22:05:55 +08:00
|
|
|
let Inst{21-20} = 0b01;
|
|
|
|
let Inst{19} = opc{0};
|
|
|
|
let Inst{18-16} = opc{3-1};
|
[AArch64][SVE] Asm: Support for predicated unary operations.
The patch includes support for the following instructions:
ABS z0.h, p0/m, z0.h
NEG z0.h, p0/m, z0.h
(S|U)XTB z0.h, p0/m, z0.h
(S|U)XTB z0.s, p0/m, z0.s
(S|U)XTB z0.d, p0/m, z0.d
(S|U)XTH z0.s, p0/m, z0.s
(S|U)XTH z0.d, p0/m, z0.d
(S|U)XTW z0.d, p0/m, z0.d
llvm-svn: 336204
2018-07-03 22:57:48 +08:00
|
|
|
let Inst{15-13} = 0b101;
|
|
|
|
let Inst{12-10} = Pg;
|
|
|
|
let Inst{9-5} = Zn;
|
|
|
|
let Inst{4-0} = Zd;
|
|
|
|
|
|
|
|
let Constraints = "$Zd = $_Zd";
|
|
|
|
}
|
|
|
|
|
|
|
|
multiclass sve_int_un_pred_arit_0<bits<3> opc, string asm> {
|
2018-07-10 22:05:55 +08:00
|
|
|
def _B : sve_int_un_pred_arit<0b00, { opc, 0b0 }, asm, ZPR8>;
|
|
|
|
def _H : sve_int_un_pred_arit<0b01, { opc, 0b0 }, asm, ZPR16>;
|
|
|
|
def _S : sve_int_un_pred_arit<0b10, { opc, 0b0 }, asm, ZPR32>;
|
|
|
|
def _D : sve_int_un_pred_arit<0b11, { opc, 0b0 }, asm, ZPR64>;
|
[AArch64][SVE] Asm: Support for predicated unary operations.
The patch includes support for the following instructions:
ABS z0.h, p0/m, z0.h
NEG z0.h, p0/m, z0.h
(S|U)XTB z0.h, p0/m, z0.h
(S|U)XTB z0.s, p0/m, z0.s
(S|U)XTB z0.d, p0/m, z0.d
(S|U)XTH z0.s, p0/m, z0.s
(S|U)XTH z0.d, p0/m, z0.d
(S|U)XTW z0.d, p0/m, z0.d
llvm-svn: 336204
2018-07-03 22:57:48 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
multiclass sve_int_un_pred_arit_0_h<bits<3> opc, string asm> {
|
2018-07-10 22:05:55 +08:00
|
|
|
def _H : sve_int_un_pred_arit<0b01, { opc, 0b0 }, asm, ZPR16>;
|
|
|
|
def _S : sve_int_un_pred_arit<0b10, { opc, 0b0 }, asm, ZPR32>;
|
|
|
|
def _D : sve_int_un_pred_arit<0b11, { opc, 0b0 }, asm, ZPR64>;
|
[AArch64][SVE] Asm: Support for predicated unary operations.
The patch includes support for the following instructions:
ABS z0.h, p0/m, z0.h
NEG z0.h, p0/m, z0.h
(S|U)XTB z0.h, p0/m, z0.h
(S|U)XTB z0.s, p0/m, z0.s
(S|U)XTB z0.d, p0/m, z0.d
(S|U)XTH z0.s, p0/m, z0.s
(S|U)XTH z0.d, p0/m, z0.d
(S|U)XTW z0.d, p0/m, z0.d
llvm-svn: 336204
2018-07-03 22:57:48 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
multiclass sve_int_un_pred_arit_0_w<bits<3> opc, string asm> {
|
2018-07-10 22:05:55 +08:00
|
|
|
def _S : sve_int_un_pred_arit<0b10, { opc, 0b0 }, asm, ZPR32>;
|
|
|
|
def _D : sve_int_un_pred_arit<0b11, { opc, 0b0 }, asm, ZPR64>;
|
[AArch64][SVE] Asm: Support for predicated unary operations.
The patch includes support for the following instructions:
ABS z0.h, p0/m, z0.h
NEG z0.h, p0/m, z0.h
(S|U)XTB z0.h, p0/m, z0.h
(S|U)XTB z0.s, p0/m, z0.s
(S|U)XTB z0.d, p0/m, z0.d
(S|U)XTH z0.s, p0/m, z0.s
(S|U)XTH z0.d, p0/m, z0.d
(S|U)XTW z0.d, p0/m, z0.d
llvm-svn: 336204
2018-07-03 22:57:48 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
multiclass sve_int_un_pred_arit_0_d<bits<3> opc, string asm> {
|
2018-07-10 22:05:55 +08:00
|
|
|
def _D : sve_int_un_pred_arit<0b11, { opc, 0b0 }, asm, ZPR64>;
|
[AArch64][SVE] Asm: Support for predicated unary operations.
The patch includes support for the following instructions:
ABS z0.h, p0/m, z0.h
NEG z0.h, p0/m, z0.h
(S|U)XTB z0.h, p0/m, z0.h
(S|U)XTB z0.s, p0/m, z0.s
(S|U)XTB z0.d, p0/m, z0.d
(S|U)XTH z0.s, p0/m, z0.s
(S|U)XTH z0.d, p0/m, z0.d
(S|U)XTW z0.d, p0/m, z0.d
llvm-svn: 336204
2018-07-03 22:57:48 +08:00
|
|
|
}
|
|
|
|
|
2018-07-10 22:05:55 +08:00
|
|
|
multiclass sve_int_un_pred_arit_1<bits<3> opc, string asm> {
|
|
|
|
def _B : sve_int_un_pred_arit<0b00, { opc, 0b1 }, asm, ZPR8>;
|
|
|
|
def _H : sve_int_un_pred_arit<0b01, { opc, 0b1 }, asm, ZPR16>;
|
|
|
|
def _S : sve_int_un_pred_arit<0b10, { opc, 0b1 }, asm, ZPR32>;
|
|
|
|
def _D : sve_int_un_pred_arit<0b11, { opc, 0b1 }, asm, ZPR64>;
|
|
|
|
}
|
|
|
|
|
|
|
|
multiclass sve_int_un_pred_arit_1_fp<bits<3> opc, string asm> {
|
|
|
|
def _H : sve_int_un_pred_arit<0b01, { opc, 0b1 }, asm, ZPR16>;
|
|
|
|
def _S : sve_int_un_pred_arit<0b10, { opc, 0b1 }, asm, ZPR32>;
|
|
|
|
def _D : sve_int_un_pred_arit<0b11, { opc, 0b1 }, asm, ZPR64>;
|
|
|
|
}
|
[AArch64][SVE] Asm: Support for predicated unary operations.
The patch includes support for the following instructions:
ABS z0.h, p0/m, z0.h
NEG z0.h, p0/m, z0.h
(S|U)XTB z0.h, p0/m, z0.h
(S|U)XTB z0.s, p0/m, z0.s
(S|U)XTB z0.d, p0/m, z0.d
(S|U)XTH z0.s, p0/m, z0.s
(S|U)XTH z0.d, p0/m, z0.d
(S|U)XTW z0.d, p0/m, z0.d
llvm-svn: 336204
2018-07-03 22:57:48 +08:00
|
|
|
|
2018-05-25 17:47:52 +08:00
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
// SVE Integer Wide Immediate - Unpredicated Group
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
class sve_int_dup_imm<bits<2> sz8_64, string asm,
|
|
|
|
ZPRRegOp zprty, Operand immtype>
|
|
|
|
: I<(outs zprty:$Zd), (ins immtype:$imm),
|
|
|
|
asm, "\t$Zd, $imm",
|
|
|
|
"",
|
|
|
|
[]>, Sched<[]> {
|
|
|
|
bits<5> Zd;
|
|
|
|
bits<9> imm;
|
|
|
|
let Inst{31-24} = 0b00100101;
|
|
|
|
let Inst{23-22} = sz8_64;
|
|
|
|
let Inst{21-14} = 0b11100011;
|
|
|
|
let Inst{13} = imm{8}; // sh
|
|
|
|
let Inst{12-5} = imm{7-0}; // imm8
|
|
|
|
let Inst{4-0} = Zd;
|
|
|
|
|
|
|
|
let isReMaterializable = 1;
|
|
|
|
}
|
|
|
|
|
|
|
|
multiclass sve_int_dup_imm<string asm> {
|
|
|
|
def _B : sve_int_dup_imm<0b00, asm, ZPR8, cpy_imm8_opt_lsl_i8>;
|
|
|
|
def _H : sve_int_dup_imm<0b01, asm, ZPR16, cpy_imm8_opt_lsl_i16>;
|
|
|
|
def _S : sve_int_dup_imm<0b10, asm, ZPR32, cpy_imm8_opt_lsl_i32>;
|
|
|
|
def _D : sve_int_dup_imm<0b11, asm, ZPR64, cpy_imm8_opt_lsl_i64>;
|
|
|
|
|
|
|
|
def : InstAlias<"mov $Zd, $imm",
|
|
|
|
(!cast<Instruction>(NAME # _B) ZPR8:$Zd, cpy_imm8_opt_lsl_i8:$imm), 1>;
|
|
|
|
def : InstAlias<"mov $Zd, $imm",
|
|
|
|
(!cast<Instruction>(NAME # _H) ZPR16:$Zd, cpy_imm8_opt_lsl_i16:$imm), 1>;
|
|
|
|
def : InstAlias<"mov $Zd, $imm",
|
|
|
|
(!cast<Instruction>(NAME # _S) ZPR32:$Zd, cpy_imm8_opt_lsl_i32:$imm), 1>;
|
|
|
|
def : InstAlias<"mov $Zd, $imm",
|
|
|
|
(!cast<Instruction>(NAME # _D) ZPR64:$Zd, cpy_imm8_opt_lsl_i64:$imm), 1>;
|
2018-06-01 20:54:46 +08:00
|
|
|
|
|
|
|
def : InstAlias<"fmov $Zd, #0.0",
|
|
|
|
(!cast<Instruction>(NAME # _H) ZPR16:$Zd, 0, 0), 1>;
|
|
|
|
def : InstAlias<"fmov $Zd, #0.0",
|
|
|
|
(!cast<Instruction>(NAME # _S) ZPR32:$Zd, 0, 0), 1>;
|
|
|
|
def : InstAlias<"fmov $Zd, #0.0",
|
|
|
|
(!cast<Instruction>(NAME # _D) ZPR64:$Zd, 0, 0), 1>;
|
|
|
|
}
|
|
|
|
|
|
|
|
class sve_int_dup_fpimm<bits<2> sz8_64, Operand fpimmtype,
|
|
|
|
string asm, ZPRRegOp zprty>
|
|
|
|
: I<(outs zprty:$Zd), (ins fpimmtype:$imm8),
|
|
|
|
asm, "\t$Zd, $imm8",
|
|
|
|
"",
|
|
|
|
[]>, Sched<[]> {
|
|
|
|
bits<5> Zd;
|
|
|
|
bits<8> imm8;
|
|
|
|
let Inst{31-24} = 0b00100101;
|
|
|
|
let Inst{23-22} = sz8_64;
|
|
|
|
let Inst{21-14} = 0b11100111;
|
|
|
|
let Inst{13} = 0b0;
|
|
|
|
let Inst{12-5} = imm8;
|
|
|
|
let Inst{4-0} = Zd;
|
|
|
|
|
|
|
|
let isReMaterializable = 1;
|
|
|
|
}
|
|
|
|
|
|
|
|
multiclass sve_int_dup_fpimm<string asm> {
|
|
|
|
def _H : sve_int_dup_fpimm<0b01, fpimm16, asm, ZPR16>;
|
|
|
|
def _S : sve_int_dup_fpimm<0b10, fpimm32, asm, ZPR32>;
|
|
|
|
def _D : sve_int_dup_fpimm<0b11, fpimm64, asm, ZPR64>;
|
|
|
|
|
|
|
|
def : InstAlias<"fmov $Zd, $imm8",
|
|
|
|
(!cast<Instruction>(NAME # _H) ZPR16:$Zd, fpimm16:$imm8), 1>;
|
|
|
|
def : InstAlias<"fmov $Zd, $imm8",
|
|
|
|
(!cast<Instruction>(NAME # _S) ZPR32:$Zd, fpimm32:$imm8), 1>;
|
|
|
|
def : InstAlias<"fmov $Zd, $imm8",
|
|
|
|
(!cast<Instruction>(NAME # _D) ZPR64:$Zd, fpimm64:$imm8), 1>;
|
2018-05-25 17:47:52 +08:00
|
|
|
}
|
[AArch64][SVE] Asm: Add support for SVE INDEX instructions.
Reviewers: rengolin, fhahn, javed.absar, SjoerdMeijer, huntergr, t.p.northover, echristo, evandro
Reviewed By: rengolin, fhahn
Subscribers: tschuett, llvm-commits, kristof.beyls
Differential Revision: https://reviews.llvm.org/D45370
llvm-svn: 329674
2018-04-10 15:01:53 +08:00
|
|
|
|
2018-05-29 18:39:49 +08:00
|
|
|
class sve_int_arith_imm0<bits<2> sz8_64, bits<3> opc, string asm,
|
|
|
|
ZPRRegOp zprty, Operand immtype>
|
|
|
|
: I<(outs zprty:$Zdn), (ins zprty:$_Zdn, immtype:$imm),
|
|
|
|
asm, "\t$Zdn, $_Zdn, $imm",
|
|
|
|
"",
|
|
|
|
[]>, Sched<[]> {
|
|
|
|
bits<5> Zdn;
|
|
|
|
bits<9> imm;
|
|
|
|
let Inst{31-24} = 0b00100101;
|
|
|
|
let Inst{23-22} = sz8_64;
|
|
|
|
let Inst{21-19} = 0b100;
|
|
|
|
let Inst{18-16} = opc;
|
|
|
|
let Inst{15-14} = 0b11;
|
|
|
|
let Inst{13} = imm{8}; // sh
|
|
|
|
let Inst{12-5} = imm{7-0}; // imm8
|
|
|
|
let Inst{4-0} = Zdn;
|
|
|
|
|
|
|
|
let Constraints = "$Zdn = $_Zdn";
|
|
|
|
}
|
|
|
|
|
|
|
|
multiclass sve_int_arith_imm0<bits<3> opc, string asm> {
|
|
|
|
def _B : sve_int_arith_imm0<0b00, opc, asm, ZPR8, addsub_imm8_opt_lsl_i8>;
|
|
|
|
def _H : sve_int_arith_imm0<0b01, opc, asm, ZPR16, addsub_imm8_opt_lsl_i16>;
|
|
|
|
def _S : sve_int_arith_imm0<0b10, opc, asm, ZPR32, addsub_imm8_opt_lsl_i32>;
|
|
|
|
def _D : sve_int_arith_imm0<0b11, opc, asm, ZPR64, addsub_imm8_opt_lsl_i64>;
|
|
|
|
}
|
|
|
|
|
[AArch64][SVE] Asm: Support for integer MUL instructions.
This patch adds the following instructions:
MUL - multiply vectors, e.g.
mul z0.h, p0/m, z0.h, z1.h
- multiply with immediate, e.g.
mul z0.h, z0.h, #127
SMULH - signed multiply returning high half, e.g.
smulh z0.h, p0/m, z0.h, z1.h
UMULH - unsigned multiply returning high half, e.g.
umulh z0.h, p0/m, z0.h, z1.h
llvm-svn: 337358
2018-07-18 16:10:03 +08:00
|
|
|
class sve_int_arith_imm<bits<2> sz8_64, bits<6> opc, string asm,
|
|
|
|
ZPRRegOp zprty, Operand immtype>
|
[AArch64][SVE] Asm: Support for signed/unsigned MIN/MAX/ABD
This patch implements the following varieties:
- Unpredicated signed max, e.g. smax z0.h, z1.h, #-128
- Unpredicated signed min, e.g. smin z0.h, z1.h, #-128
- Unpredicated unsigned max, e.g. umax z0.h, z1.h, #255
- Unpredicated unsigned min, e.g. umin z0.h, z1.h, #255
- Predicated signed max, e.g. smax z0.h, p0/m, z0.h, z1.h
- Predicated signed min, e.g. smin z0.h, p0/m, z0.h, z1.h
- Predicated signed abd, e.g. sabd z0.h, p0/m, z0.h, z1.h
- Predicated unsigned max, e.g. umax z0.h, p0/m, z0.h, z1.h
- Predicated unsigned min, e.g. umin z0.h, p0/m, z0.h, z1.h
- Predicated unsigned abd, e.g. uabd z0.h, p0/m, z0.h, z1.h
llvm-svn: 336317
2018-07-05 15:54:10 +08:00
|
|
|
: I<(outs zprty:$Zdn), (ins zprty:$_Zdn, immtype:$imm),
|
|
|
|
asm, "\t$Zdn, $_Zdn, $imm",
|
|
|
|
"",
|
|
|
|
[]>, Sched<[]> {
|
|
|
|
bits<5> Zdn;
|
|
|
|
bits<8> imm;
|
|
|
|
let Inst{31-24} = 0b00100101;
|
|
|
|
let Inst{23-22} = sz8_64;
|
[AArch64][SVE] Asm: Support for integer MUL instructions.
This patch adds the following instructions:
MUL - multiply vectors, e.g.
mul z0.h, p0/m, z0.h, z1.h
- multiply with immediate, e.g.
mul z0.h, z0.h, #127
SMULH - signed multiply returning high half, e.g.
smulh z0.h, p0/m, z0.h, z1.h
UMULH - unsigned multiply returning high half, e.g.
umulh z0.h, p0/m, z0.h, z1.h
llvm-svn: 337358
2018-07-18 16:10:03 +08:00
|
|
|
let Inst{21-16} = opc;
|
[AArch64][SVE] Asm: Support for signed/unsigned MIN/MAX/ABD
This patch implements the following varieties:
- Unpredicated signed max, e.g. smax z0.h, z1.h, #-128
- Unpredicated signed min, e.g. smin z0.h, z1.h, #-128
- Unpredicated unsigned max, e.g. umax z0.h, z1.h, #255
- Unpredicated unsigned min, e.g. umin z0.h, z1.h, #255
- Predicated signed max, e.g. smax z0.h, p0/m, z0.h, z1.h
- Predicated signed min, e.g. smin z0.h, p0/m, z0.h, z1.h
- Predicated signed abd, e.g. sabd z0.h, p0/m, z0.h, z1.h
- Predicated unsigned max, e.g. umax z0.h, p0/m, z0.h, z1.h
- Predicated unsigned min, e.g. umin z0.h, p0/m, z0.h, z1.h
- Predicated unsigned abd, e.g. uabd z0.h, p0/m, z0.h, z1.h
llvm-svn: 336317
2018-07-05 15:54:10 +08:00
|
|
|
let Inst{15-13} = 0b110;
|
|
|
|
let Inst{12-5} = imm;
|
|
|
|
let Inst{4-0} = Zdn;
|
|
|
|
|
|
|
|
let Constraints = "$Zdn = $_Zdn";
|
|
|
|
}
|
|
|
|
|
|
|
|
multiclass sve_int_arith_imm1<bits<2> opc, string asm, Operand immtype> {
|
[AArch64][SVE] Asm: Support for integer MUL instructions.
This patch adds the following instructions:
MUL - multiply vectors, e.g.
mul z0.h, p0/m, z0.h, z1.h
- multiply with immediate, e.g.
mul z0.h, z0.h, #127
SMULH - signed multiply returning high half, e.g.
smulh z0.h, p0/m, z0.h, z1.h
UMULH - unsigned multiply returning high half, e.g.
umulh z0.h, p0/m, z0.h, z1.h
llvm-svn: 337358
2018-07-18 16:10:03 +08:00
|
|
|
def _B : sve_int_arith_imm<0b00, { 0b1010, opc }, asm, ZPR8, immtype>;
|
|
|
|
def _H : sve_int_arith_imm<0b01, { 0b1010, opc }, asm, ZPR16, immtype>;
|
|
|
|
def _S : sve_int_arith_imm<0b10, { 0b1010, opc }, asm, ZPR32, immtype>;
|
|
|
|
def _D : sve_int_arith_imm<0b11, { 0b1010, opc }, asm, ZPR64, immtype>;
|
|
|
|
}
|
|
|
|
|
|
|
|
multiclass sve_int_arith_imm2<string asm> {
|
|
|
|
def _B : sve_int_arith_imm<0b00, 0b110000, asm, ZPR8, simm8>;
|
|
|
|
def _H : sve_int_arith_imm<0b01, 0b110000, asm, ZPR16, simm8>;
|
|
|
|
def _S : sve_int_arith_imm<0b10, 0b110000, asm, ZPR32, simm8>;
|
|
|
|
def _D : sve_int_arith_imm<0b11, 0b110000, asm, ZPR64, simm8>;
|
[AArch64][SVE] Asm: Support for signed/unsigned MIN/MAX/ABD
This patch implements the following varieties:
- Unpredicated signed max, e.g. smax z0.h, z1.h, #-128
- Unpredicated signed min, e.g. smin z0.h, z1.h, #-128
- Unpredicated unsigned max, e.g. umax z0.h, z1.h, #255
- Unpredicated unsigned min, e.g. umin z0.h, z1.h, #255
- Predicated signed max, e.g. smax z0.h, p0/m, z0.h, z1.h
- Predicated signed min, e.g. smin z0.h, p0/m, z0.h, z1.h
- Predicated signed abd, e.g. sabd z0.h, p0/m, z0.h, z1.h
- Predicated unsigned max, e.g. umax z0.h, p0/m, z0.h, z1.h
- Predicated unsigned min, e.g. umin z0.h, p0/m, z0.h, z1.h
- Predicated unsigned abd, e.g. uabd z0.h, p0/m, z0.h, z1.h
llvm-svn: 336317
2018-07-05 15:54:10 +08:00
|
|
|
}
|
[AArch64][SVE] Asm: Support for AND, ORR, EOR and BIC instructions.
This patch addresses the following variants:
- bitmask immediate, e.g. 'and z0.d, z0.d, #0x6'.
- unpredicated data vectors, e.g. 'and z0.d, z1.d, z2.d'.
- predicated data vectors, e.g. 'and z0.d, p0/m, z0.d, z1.d'.
And also several aliases, such as:
- ORN, alias of ORR.
- EON, alias of EOR.
- BIC, alias of AND (immediate variant)
- MOV, alias of ORR (if unpredicated and source register operands are the same)
Reviewers: rengolin, huntergr, fhahn, samparker, SjoerdMeijer, javed.absar
Reviewed By: fhahn
Differential Revision: https://reviews.llvm.org/D47363
llvm-svn: 333414
2018-05-29 21:08:43 +08:00
|
|
|
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
// SVE Bitwise Logical - Unpredicated Group
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
|
|
|
|
class sve_int_bin_cons_log<bits<2> opc, string asm>
|
|
|
|
: I<(outs ZPR64:$Zd), (ins ZPR64:$Zn, ZPR64:$Zm),
|
|
|
|
asm, "\t$Zd, $Zn, $Zm",
|
|
|
|
"",
|
|
|
|
[]>, Sched<[]> {
|
|
|
|
bits<5> Zd;
|
|
|
|
bits<5> Zm;
|
|
|
|
bits<5> Zn;
|
|
|
|
let Inst{31-24} = 0b00000100;
|
|
|
|
let Inst{23-22} = opc{1-0};
|
|
|
|
let Inst{21} = 0b1;
|
|
|
|
let Inst{20-16} = Zm;
|
|
|
|
let Inst{15-10} = 0b001100;
|
|
|
|
let Inst{9-5} = Zn;
|
|
|
|
let Inst{4-0} = Zd;
|
|
|
|
}
|
|
|
|
|
2018-06-04 13:40:46 +08:00
|
|
|
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
// SVE Integer Wide Immediate - Predicated Group
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
|
2018-06-04 13:58:06 +08:00
|
|
|
class sve_int_dup_fpimm_pred<bits<2> sz, Operand fpimmtype,
|
|
|
|
string asm, ZPRRegOp zprty>
|
|
|
|
: I<(outs zprty:$Zd), (ins zprty:$_Zd, PPRAny:$Pg, fpimmtype:$imm8),
|
|
|
|
asm, "\t$Zd, $Pg/m, $imm8",
|
|
|
|
"",
|
|
|
|
[]>, Sched<[]> {
|
|
|
|
bits<4> Pg;
|
|
|
|
bits<5> Zd;
|
|
|
|
bits<8> imm8;
|
|
|
|
let Inst{31-24} = 0b00000101;
|
|
|
|
let Inst{23-22} = sz;
|
|
|
|
let Inst{21-20} = 0b01;
|
|
|
|
let Inst{19-16} = Pg;
|
|
|
|
let Inst{15-13} = 0b110;
|
|
|
|
let Inst{12-5} = imm8;
|
|
|
|
let Inst{4-0} = Zd;
|
|
|
|
|
|
|
|
let Constraints = "$Zd = $_Zd";
|
|
|
|
}
|
|
|
|
|
|
|
|
multiclass sve_int_dup_fpimm_pred<string asm> {
|
|
|
|
def _H : sve_int_dup_fpimm_pred<0b01, fpimm16, asm, ZPR16>;
|
|
|
|
def _S : sve_int_dup_fpimm_pred<0b10, fpimm32, asm, ZPR32>;
|
|
|
|
def _D : sve_int_dup_fpimm_pred<0b11, fpimm64, asm, ZPR64>;
|
|
|
|
|
|
|
|
def : InstAlias<"fmov $Zd, $Pg/m, $imm8",
|
|
|
|
(!cast<Instruction>(NAME # _H) ZPR16:$Zd, PPRAny:$Pg, fpimm16:$imm8), 1>;
|
|
|
|
def : InstAlias<"fmov $Zd, $Pg/m, $imm8",
|
|
|
|
(!cast<Instruction>(NAME # _S) ZPR32:$Zd, PPRAny:$Pg, fpimm32:$imm8), 1>;
|
|
|
|
def : InstAlias<"fmov $Zd, $Pg/m, $imm8",
|
|
|
|
(!cast<Instruction>(NAME # _D) ZPR64:$Zd, PPRAny:$Pg, fpimm64:$imm8), 1>;
|
|
|
|
}
|
|
|
|
|
2018-06-04 13:40:46 +08:00
|
|
|
class sve_int_dup_imm_pred<bits<2> sz8_64, bit m, string asm,
|
|
|
|
ZPRRegOp zprty, string pred_qual, dag iops>
|
|
|
|
: I<(outs zprty:$Zd), iops,
|
|
|
|
asm, "\t$Zd, $Pg"#pred_qual#", $imm",
|
|
|
|
"", []>, Sched<[]> {
|
|
|
|
bits<5> Zd;
|
|
|
|
bits<4> Pg;
|
|
|
|
bits<9> imm;
|
|
|
|
let Inst{31-24} = 0b00000101;
|
|
|
|
let Inst{23-22} = sz8_64;
|
|
|
|
let Inst{21-20} = 0b01;
|
|
|
|
let Inst{19-16} = Pg;
|
|
|
|
let Inst{15} = 0b0;
|
|
|
|
let Inst{14} = m;
|
|
|
|
let Inst{13} = imm{8}; // sh
|
|
|
|
let Inst{12-5} = imm{7-0}; // imm8
|
|
|
|
let Inst{4-0} = Zd;
|
|
|
|
}
|
|
|
|
|
|
|
|
multiclass sve_int_dup_imm_pred_merge<string asm> {
|
|
|
|
let Constraints = "$Zd = $_Zd" in {
|
|
|
|
def _B : sve_int_dup_imm_pred<0b00, 1, asm, ZPR8, "/m", (ins ZPR8:$_Zd, PPRAny:$Pg, cpy_imm8_opt_lsl_i8:$imm)>;
|
|
|
|
def _H : sve_int_dup_imm_pred<0b01, 1, asm, ZPR16, "/m", (ins ZPR16:$_Zd, PPRAny:$Pg, cpy_imm8_opt_lsl_i16:$imm)>;
|
|
|
|
def _S : sve_int_dup_imm_pred<0b10, 1, asm, ZPR32, "/m", (ins ZPR32:$_Zd, PPRAny:$Pg, cpy_imm8_opt_lsl_i32:$imm)>;
|
|
|
|
def _D : sve_int_dup_imm_pred<0b11, 1, asm, ZPR64, "/m", (ins ZPR64:$_Zd, PPRAny:$Pg, cpy_imm8_opt_lsl_i64:$imm)>;
|
|
|
|
}
|
|
|
|
|
|
|
|
def : InstAlias<"mov $Zd, $Pg/m, $imm",
|
|
|
|
(!cast<Instruction>(NAME # _B) ZPR8:$Zd, PPRAny:$Pg, cpy_imm8_opt_lsl_i8:$imm), 1>;
|
|
|
|
def : InstAlias<"mov $Zd, $Pg/m, $imm",
|
|
|
|
(!cast<Instruction>(NAME # _H) ZPR16:$Zd, PPRAny:$Pg, cpy_imm8_opt_lsl_i16:$imm), 1>;
|
|
|
|
def : InstAlias<"mov $Zd, $Pg/m, $imm",
|
|
|
|
(!cast<Instruction>(NAME # _S) ZPR32:$Zd, PPRAny:$Pg, cpy_imm8_opt_lsl_i32:$imm), 1>;
|
|
|
|
def : InstAlias<"mov $Zd, $Pg/m, $imm",
|
|
|
|
(!cast<Instruction>(NAME # _D) ZPR64:$Zd, PPRAny:$Pg, cpy_imm8_opt_lsl_i64:$imm), 1>;
|
2018-06-04 13:58:06 +08:00
|
|
|
|
|
|
|
def : InstAlias<"fmov $Zd, $Pg/m, #0.0",
|
|
|
|
(!cast<Instruction>(NAME # _H) ZPR16:$Zd, PPRAny:$Pg, 0, 0), 0>;
|
|
|
|
def : InstAlias<"fmov $Zd, $Pg/m, #0.0",
|
|
|
|
(!cast<Instruction>(NAME # _S) ZPR32:$Zd, PPRAny:$Pg, 0, 0), 0>;
|
|
|
|
def : InstAlias<"fmov $Zd, $Pg/m, #0.0",
|
|
|
|
(!cast<Instruction>(NAME # _D) ZPR64:$Zd, PPRAny:$Pg, 0, 0), 0>;
|
2018-06-04 13:40:46 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
multiclass sve_int_dup_imm_pred_zero<string asm> {
|
|
|
|
def _B : sve_int_dup_imm_pred<0b00, 0, asm, ZPR8, "/z", (ins PPRAny:$Pg, cpy_imm8_opt_lsl_i8:$imm)>;
|
|
|
|
def _H : sve_int_dup_imm_pred<0b01, 0, asm, ZPR16, "/z", (ins PPRAny:$Pg, cpy_imm8_opt_lsl_i16:$imm)>;
|
|
|
|
def _S : sve_int_dup_imm_pred<0b10, 0, asm, ZPR32, "/z", (ins PPRAny:$Pg, cpy_imm8_opt_lsl_i32:$imm)>;
|
|
|
|
def _D : sve_int_dup_imm_pred<0b11, 0, asm, ZPR64, "/z", (ins PPRAny:$Pg, cpy_imm8_opt_lsl_i64:$imm)>;
|
|
|
|
|
|
|
|
def : InstAlias<"mov $Zd, $Pg/z, $imm",
|
|
|
|
(!cast<Instruction>(NAME # _B) ZPR8:$Zd, PPRAny:$Pg, cpy_imm8_opt_lsl_i8:$imm), 1>;
|
|
|
|
def : InstAlias<"mov $Zd, $Pg/z, $imm",
|
|
|
|
(!cast<Instruction>(NAME # _H) ZPR16:$Zd, PPRAny:$Pg, cpy_imm8_opt_lsl_i16:$imm), 1>;
|
|
|
|
def : InstAlias<"mov $Zd, $Pg/z, $imm",
|
|
|
|
(!cast<Instruction>(NAME # _S) ZPR32:$Zd, PPRAny:$Pg, cpy_imm8_opt_lsl_i32:$imm), 1>;
|
|
|
|
def : InstAlias<"mov $Zd, $Pg/z, $imm",
|
|
|
|
(!cast<Instruction>(NAME # _D) ZPR64:$Zd, PPRAny:$Pg, cpy_imm8_opt_lsl_i64:$imm), 1>;
|
|
|
|
}
|
|
|
|
|
[AArch64][SVE] Asm: Support for vector element compares.
This patch adds instructions for comparing elements from two vectors, e.g.
cmpgt p0.s, p0/z, z0.s, z1.s
and also adds support for comparing to a 64-bit wide element vector, e.g.
cmpgt p0.s, p0/z, z0.s, z1.d
The patch also contains aliases for certain comparisons, e.g.:
cmple p0.s, p0/z, z0.s, z1.s => cmpge p0.s, p0/z, z1.s, z0.s
cmplo p0.s, p0/z, z0.s, z1.s => cmphi p0.s, p0/z, z1.s, z0.s
cmpls p0.s, p0/z, z0.s, z1.s => cmphs p0.s, p0/z, z1.s, z0.s
cmplt p0.s, p0/z, z0.s, z1.s => cmpgt p0.s, p0/z, z1.s, z0.s
llvm-svn: 334931
2018-06-18 18:59:19 +08:00
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
// SVE Integer Compare - Vectors Group
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
|
|
|
|
class sve_int_cmp<bit cmp_1, bits<2> sz8_64, bits<3> opc, string asm,
|
|
|
|
PPRRegOp pprty, ZPRRegOp zprty1, ZPRRegOp zprty2>
|
|
|
|
: I<(outs pprty:$Pd), (ins PPR3bAny:$Pg, zprty1:$Zn, zprty2:$Zm),
|
|
|
|
asm, "\t$Pd, $Pg/z, $Zn, $Zm",
|
|
|
|
"",
|
|
|
|
[]>, Sched<[]> {
|
|
|
|
bits<4> Pd;
|
|
|
|
bits<3> Pg;
|
|
|
|
bits<5> Zm;
|
|
|
|
bits<5> Zn;
|
|
|
|
let Inst{31-24} = 0b00100100;
|
|
|
|
let Inst{23-22} = sz8_64;
|
|
|
|
let Inst{21} = 0b0;
|
|
|
|
let Inst{20-16} = Zm;
|
|
|
|
let Inst{15} = opc{2};
|
|
|
|
let Inst{14} = cmp_1;
|
|
|
|
let Inst{13} = opc{1};
|
|
|
|
let Inst{12-10} = Pg;
|
|
|
|
let Inst{9-5} = Zn;
|
|
|
|
let Inst{4} = opc{0};
|
|
|
|
let Inst{3-0} = Pd;
|
|
|
|
|
|
|
|
let Defs = [NZCV];
|
|
|
|
}
|
|
|
|
|
|
|
|
multiclass sve_int_cmp_0<bits<3> opc, string asm> {
|
|
|
|
def _B : sve_int_cmp<0b0, 0b00, opc, asm, PPR8, ZPR8, ZPR8>;
|
|
|
|
def _H : sve_int_cmp<0b0, 0b01, opc, asm, PPR16, ZPR16, ZPR16>;
|
|
|
|
def _S : sve_int_cmp<0b0, 0b10, opc, asm, PPR32, ZPR32, ZPR32>;
|
|
|
|
def _D : sve_int_cmp<0b0, 0b11, opc, asm, PPR64, ZPR64, ZPR64>;
|
|
|
|
}
|
|
|
|
|
|
|
|
multiclass sve_int_cmp_0_wide<bits<3> opc, string asm> {
|
|
|
|
def _B : sve_int_cmp<0b0, 0b00, opc, asm, PPR8, ZPR8, ZPR64>;
|
|
|
|
def _H : sve_int_cmp<0b0, 0b01, opc, asm, PPR16, ZPR16, ZPR64>;
|
|
|
|
def _S : sve_int_cmp<0b0, 0b10, opc, asm, PPR32, ZPR32, ZPR64>;
|
|
|
|
}
|
|
|
|
|
|
|
|
multiclass sve_int_cmp_1_wide<bits<3> opc, string asm> {
|
|
|
|
def _B : sve_int_cmp<0b1, 0b00, opc, asm, PPR8, ZPR8, ZPR64>;
|
|
|
|
def _H : sve_int_cmp<0b1, 0b01, opc, asm, PPR16, ZPR16, ZPR64>;
|
|
|
|
def _S : sve_int_cmp<0b1, 0b10, opc, asm, PPR32, ZPR32, ZPR64>;
|
|
|
|
}
|
|
|
|
|
2018-07-02 16:20:59 +08:00
|
|
|
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
// SVE Integer Compare - Signed Immediate Group
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
|
|
|
|
class sve_int_scmp_vi<bits<2> sz8_64, bits<3> opc, string asm, PPRRegOp pprty,
|
|
|
|
ZPRRegOp zprty,
|
|
|
|
Operand immtype>
|
|
|
|
: I<(outs pprty:$Pd), (ins PPR3bAny:$Pg, zprty:$Zn, immtype:$imm5),
|
|
|
|
asm, "\t$Pd, $Pg/z, $Zn, $imm5",
|
|
|
|
"",
|
|
|
|
[]>, Sched<[]> {
|
|
|
|
bits<4> Pd;
|
|
|
|
bits<3> Pg;
|
|
|
|
bits<5> Zn;
|
|
|
|
bits<5> imm5;
|
|
|
|
let Inst{31-24} = 0b00100101;
|
|
|
|
let Inst{23-22} = sz8_64;
|
|
|
|
let Inst{21} = 0b0;
|
|
|
|
let Inst{20-16} = imm5;
|
|
|
|
let Inst{15} = opc{2};
|
|
|
|
let Inst{14} = 0b0;
|
|
|
|
let Inst{13} = opc{1};
|
|
|
|
let Inst{12-10} = Pg;
|
|
|
|
let Inst{9-5} = Zn;
|
|
|
|
let Inst{4} = opc{0};
|
|
|
|
let Inst{3-0} = Pd;
|
|
|
|
|
|
|
|
let Defs = [NZCV];
|
|
|
|
}
|
|
|
|
|
|
|
|
multiclass sve_int_scmp_vi<bits<3> opc, string asm> {
|
|
|
|
def _B : sve_int_scmp_vi<0b00, opc, asm, PPR8, ZPR8, simm5_32b>;
|
|
|
|
def _H : sve_int_scmp_vi<0b01, opc, asm, PPR16, ZPR16, simm5_32b>;
|
|
|
|
def _S : sve_int_scmp_vi<0b10, opc, asm, PPR32, ZPR32, simm5_32b>;
|
|
|
|
def _D : sve_int_scmp_vi<0b11, opc, asm, PPR64, ZPR64, simm5_64b>;
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
// SVE Integer Compare - Unsigned Immediate Group
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
|
|
|
|
class sve_int_ucmp_vi<bits<2> sz8_64, bits<2> opc, string asm, PPRRegOp pprty,
|
|
|
|
ZPRRegOp zprty, Operand immtype>
|
|
|
|
: I<(outs pprty:$Pd), (ins PPR3bAny:$Pg, zprty:$Zn, immtype:$imm7),
|
|
|
|
asm, "\t$Pd, $Pg/z, $Zn, $imm7",
|
|
|
|
"",
|
|
|
|
[]>, Sched<[]> {
|
|
|
|
bits<4> Pd;
|
|
|
|
bits<3> Pg;
|
|
|
|
bits<5> Zn;
|
|
|
|
bits<7> imm7;
|
|
|
|
let Inst{31-24} = 0b00100100;
|
|
|
|
let Inst{23-22} = sz8_64;
|
|
|
|
let Inst{21} = 1;
|
|
|
|
let Inst{20-14} = imm7;
|
|
|
|
let Inst{13} = opc{1};
|
|
|
|
let Inst{12-10} = Pg;
|
|
|
|
let Inst{9-5} = Zn;
|
|
|
|
let Inst{4} = opc{0};
|
|
|
|
let Inst{3-0} = Pd;
|
|
|
|
|
|
|
|
let Defs = [NZCV];
|
|
|
|
}
|
|
|
|
|
|
|
|
multiclass sve_int_ucmp_vi<bits<2> opc, string asm> {
|
|
|
|
def _B : sve_int_ucmp_vi<0b00, opc, asm, PPR8, ZPR8, imm0_127>;
|
|
|
|
def _H : sve_int_ucmp_vi<0b01, opc, asm, PPR16, ZPR16, imm0_127>;
|
|
|
|
def _S : sve_int_ucmp_vi<0b10, opc, asm, PPR32, ZPR32, imm0_127>;
|
|
|
|
def _D : sve_int_ucmp_vi<0b11, opc, asm, PPR64, ZPR64, imm0_127>;
|
|
|
|
}
|
|
|
|
|
|
|
|
|
[AArch64][SVE] Asm: Support for vector element FP compare.
Contains the following variants:
- Compare with (elements from) other vector
instructions: fcmeq, fcmgt, fcmge, fcmne, fcmuo.
aliases: fcmle, fcmlt.
e.g. fcmle p0.h, p0/z, z0.h, z1.h => fcmge p0.h, p0/z, z1.h, z0.h
- Compare absolute values with (absolute values from) other vector.
instructions: facge, facgt.
aliases: facle, faclt.
e.g. facle p0.h, p0/z, z0.h, z1.h => facge p0.h, p0/z, z1.h, z0.h
- Compare vector elements with #0.0
instructions: fcmeq, fcmgt, fcmge, fcmle, fcmlt, fcmne.
e.g. fcmle p0.h, p0/z, z0.h, #0.0
llvm-svn: 336182
2018-07-03 17:07:23 +08:00
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
// SVE Floating Point Compare - Vectors Group
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
|
|
|
|
class sve_fp_3op_p_pd<bits<2> sz, bits<3> opc, string asm, PPRRegOp pprty,
|
|
|
|
ZPRRegOp zprty>
|
|
|
|
: I<(outs pprty:$Pd), (ins PPR3bAny:$Pg, zprty:$Zn, zprty:$Zm),
|
|
|
|
asm, "\t$Pd, $Pg/z, $Zn, $Zm",
|
|
|
|
"",
|
|
|
|
[]>, Sched<[]> {
|
|
|
|
bits<4> Pd;
|
|
|
|
bits<3> Pg;
|
|
|
|
bits<5> Zm;
|
|
|
|
bits<5> Zn;
|
|
|
|
let Inst{31-24} = 0b01100101;
|
|
|
|
let Inst{23-22} = sz;
|
|
|
|
let Inst{21} = 0b0;
|
|
|
|
let Inst{20-16} = Zm;
|
|
|
|
let Inst{15} = opc{2};
|
|
|
|
let Inst{14} = 0b1;
|
|
|
|
let Inst{13} = opc{1};
|
|
|
|
let Inst{12-10} = Pg;
|
|
|
|
let Inst{9-5} = Zn;
|
|
|
|
let Inst{4} = opc{0};
|
|
|
|
let Inst{3-0} = Pd;
|
|
|
|
}
|
|
|
|
|
|
|
|
multiclass sve_fp_3op_p_pd<bits<3> opc, string asm> {
|
|
|
|
def _H : sve_fp_3op_p_pd<0b01, opc, asm, PPR16, ZPR16>;
|
|
|
|
def _S : sve_fp_3op_p_pd<0b10, opc, asm, PPR32, ZPR32>;
|
|
|
|
def _D : sve_fp_3op_p_pd<0b11, opc, asm, PPR64, ZPR64>;
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
// SVE Floating Point Compare - with Zero Group
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
|
|
|
|
class sve_fp_2op_p_pd<bits<2> sz, bits<3> opc, string asm, PPRRegOp pprty,
|
|
|
|
ZPRRegOp zprty>
|
|
|
|
: I<(outs pprty:$Pd), (ins PPR3bAny:$Pg, zprty:$Zn),
|
|
|
|
asm, "\t$Pd, $Pg/z, $Zn, #0.0",
|
|
|
|
"",
|
|
|
|
[]>, Sched<[]> {
|
|
|
|
bits<4> Pd;
|
|
|
|
bits<3> Pg;
|
|
|
|
bits<5> Zn;
|
|
|
|
let Inst{31-24} = 0b01100101;
|
|
|
|
let Inst{23-22} = sz;
|
|
|
|
let Inst{21-18} = 0b0100;
|
|
|
|
let Inst{17-16} = opc{2-1};
|
|
|
|
let Inst{15-13} = 0b001;
|
|
|
|
let Inst{12-10} = Pg;
|
|
|
|
let Inst{9-5} = Zn;
|
|
|
|
let Inst{4} = opc{0};
|
|
|
|
let Inst{3-0} = Pd;
|
|
|
|
}
|
|
|
|
|
|
|
|
multiclass sve_fp_2op_p_pd<bits<3> opc, string asm> {
|
|
|
|
def _H : sve_fp_2op_p_pd<0b01, opc, asm, PPR16, ZPR16>;
|
|
|
|
def _S : sve_fp_2op_p_pd<0b10, opc, asm, PPR32, ZPR32>;
|
|
|
|
def _D : sve_fp_2op_p_pd<0b11, opc, asm, PPR64, ZPR64>;
|
|
|
|
}
|
|
|
|
|
|
|
|
|
[AArch64][SVE] Asm: Add support for SVE INDEX instructions.
Reviewers: rengolin, fhahn, javed.absar, SjoerdMeijer, huntergr, t.p.northover, echristo, evandro
Reviewed By: rengolin, fhahn
Subscribers: tschuett, llvm-commits, kristof.beyls
Differential Revision: https://reviews.llvm.org/D45370
llvm-svn: 329674
2018-04-10 15:01:53 +08:00
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
//SVE Index Generation Group
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
|
|
|
|
class sve_int_index_ii<bits<2> sz8_64, string asm, ZPRRegOp zprty,
|
|
|
|
Operand imm_ty>
|
|
|
|
: I<(outs zprty:$Zd), (ins imm_ty:$imm5, imm_ty:$imm5b),
|
|
|
|
asm, "\t$Zd, $imm5, $imm5b",
|
|
|
|
"", []>, Sched<[]> {
|
|
|
|
bits<5> Zd;
|
|
|
|
bits<5> imm5;
|
|
|
|
bits<5> imm5b;
|
|
|
|
let Inst{31-24} = 0b00000100;
|
|
|
|
let Inst{23-22} = sz8_64;
|
|
|
|
let Inst{21} = 0b1;
|
|
|
|
let Inst{20-16} = imm5b;
|
|
|
|
let Inst{15-10} = 0b010000;
|
|
|
|
let Inst{9-5} = imm5;
|
|
|
|
let Inst{4-0} = Zd;
|
|
|
|
}
|
|
|
|
|
|
|
|
multiclass sve_int_index_ii<string asm> {
|
|
|
|
def _B : sve_int_index_ii<0b00, asm, ZPR8, simm5_32b>;
|
|
|
|
def _H : sve_int_index_ii<0b01, asm, ZPR16, simm5_32b>;
|
|
|
|
def _S : sve_int_index_ii<0b10, asm, ZPR32, simm5_32b>;
|
|
|
|
def _D : sve_int_index_ii<0b11, asm, ZPR64, simm5_64b>;
|
|
|
|
}
|
|
|
|
|
|
|
|
class sve_int_index_ir<bits<2> sz8_64, string asm, ZPRRegOp zprty,
|
|
|
|
RegisterClass srcRegType, Operand imm_ty>
|
|
|
|
: I<(outs zprty:$Zd), (ins imm_ty:$imm5, srcRegType:$Rm),
|
|
|
|
asm, "\t$Zd, $imm5, $Rm",
|
|
|
|
"", []>, Sched<[]> {
|
|
|
|
bits<5> Rm;
|
|
|
|
bits<5> Zd;
|
|
|
|
bits<5> imm5;
|
|
|
|
let Inst{31-24} = 0b00000100;
|
|
|
|
let Inst{23-22} = sz8_64;
|
|
|
|
let Inst{21} = 0b1;
|
|
|
|
let Inst{20-16} = Rm;
|
|
|
|
let Inst{15-10} = 0b010010;
|
|
|
|
let Inst{9-5} = imm5;
|
|
|
|
let Inst{4-0} = Zd;
|
|
|
|
}
|
|
|
|
|
|
|
|
multiclass sve_int_index_ir<string asm> {
|
|
|
|
def _B : sve_int_index_ir<0b00, asm, ZPR8, GPR32, simm5_32b>;
|
|
|
|
def _H : sve_int_index_ir<0b01, asm, ZPR16, GPR32, simm5_32b>;
|
|
|
|
def _S : sve_int_index_ir<0b10, asm, ZPR32, GPR32, simm5_32b>;
|
|
|
|
def _D : sve_int_index_ir<0b11, asm, ZPR64, GPR64, simm5_64b>;
|
|
|
|
}
|
|
|
|
|
|
|
|
class sve_int_index_ri<bits<2> sz8_64, string asm, ZPRRegOp zprty,
|
|
|
|
RegisterClass srcRegType, Operand imm_ty>
|
|
|
|
: I<(outs zprty:$Zd), (ins srcRegType:$Rn, imm_ty:$imm5),
|
|
|
|
asm, "\t$Zd, $Rn, $imm5",
|
|
|
|
"", []>, Sched<[]> {
|
|
|
|
bits<5> Rn;
|
|
|
|
bits<5> Zd;
|
|
|
|
bits<5> imm5;
|
|
|
|
let Inst{31-24} = 0b00000100;
|
|
|
|
let Inst{23-22} = sz8_64;
|
|
|
|
let Inst{21} = 0b1;
|
|
|
|
let Inst{20-16} = imm5;
|
|
|
|
let Inst{15-10} = 0b010001;
|
|
|
|
let Inst{9-5} = Rn;
|
|
|
|
let Inst{4-0} = Zd;
|
|
|
|
}
|
|
|
|
|
|
|
|
multiclass sve_int_index_ri<string asm> {
|
|
|
|
def _B : sve_int_index_ri<0b00, asm, ZPR8, GPR32, simm5_32b>;
|
|
|
|
def _H : sve_int_index_ri<0b01, asm, ZPR16, GPR32, simm5_32b>;
|
|
|
|
def _S : sve_int_index_ri<0b10, asm, ZPR32, GPR32, simm5_32b>;
|
|
|
|
def _D : sve_int_index_ri<0b11, asm, ZPR64, GPR64, simm5_64b>;
|
|
|
|
}
|
|
|
|
|
|
|
|
class sve_int_index_rr<bits<2> sz8_64, string asm, ZPRRegOp zprty,
|
|
|
|
RegisterClass srcRegType>
|
|
|
|
: I<(outs zprty:$Zd), (ins srcRegType:$Rn, srcRegType:$Rm),
|
|
|
|
asm, "\t$Zd, $Rn, $Rm",
|
|
|
|
"", []>, Sched<[]> {
|
|
|
|
bits<5> Zd;
|
|
|
|
bits<5> Rm;
|
|
|
|
bits<5> Rn;
|
|
|
|
let Inst{31-24} = 0b00000100;
|
|
|
|
let Inst{23-22} = sz8_64;
|
|
|
|
let Inst{21} = 0b1;
|
|
|
|
let Inst{20-16} = Rm;
|
|
|
|
let Inst{15-10} = 0b010011;
|
|
|
|
let Inst{9-5} = Rn;
|
|
|
|
let Inst{4-0} = Zd;
|
|
|
|
}
|
|
|
|
|
|
|
|
multiclass sve_int_index_rr<string asm> {
|
|
|
|
def _B : sve_int_index_rr<0b00, asm, ZPR8, GPR32>;
|
|
|
|
def _H : sve_int_index_rr<0b01, asm, ZPR16, GPR32>;
|
|
|
|
def _S : sve_int_index_rr<0b10, asm, ZPR32, GPR32>;
|
|
|
|
def _D : sve_int_index_rr<0b11, asm, ZPR64, GPR64>;
|
|
|
|
}
|
2018-05-29 22:40:24 +08:00
|
|
|
//
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
// SVE Bitwise Shift - Predicated Group
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
|
[AArch64][SVE] Asm: Support for remaining shift instructions.
This patch completes support for shifts, which include:
- LSL - Logical Shift Left
- LSLR - Logical Shift Left, Reversed form
- LSR - Logical Shift Right
- LSRR - Logical Shift Right, Reversed form
- ASR - Arithmetic Shift Right
- ASRR - Arithmetic Shift Right, Reversed form
- ASRD - Arithmetic Shift Right for Divide
In the following variants:
- Predicated shift by immediate - ASR, LSL, LSR, ASRD
e.g.
asr z0.h, p0/m, z0.h, #1
(active lanes of z0 shifted by #1)
- Unpredicated shift by immediate - ASR, LSL*, LSR*
e.g.
asr z0.h, z1.h, #1
(all lanes of z1 shifted by #1, stored in z0)
- Predicated shift by vector - ASR, LSL*, LSR*
e.g.
asr z0.h, p0/m, z0.h, z1.h
(active lanes of z0 shifted by z1, stored in z0)
- Predicated shift by vector, reversed form - ASRR, LSLR, LSRR
e.g.
lslr z0.h, p0/m, z0.h, z1.h
(active lanes of z1 shifted by z0, stored in z0)
- Predicated shift left/right by wide vector - ASR, LSL, LSR
e.g.
lsl z0.h, p0/m, z0.h, z1.d
(active lanes of z0 shifted by wide elements of vector z1)
- Unpredicated shift left/right by wide vector - ASR, LSL, LSR
e.g.
lsl z0.h, z1.h, z2.d
(all lanes of z1 shifted by wide elements of z2, stored in z0)
*Variants added in previous patches.
llvm-svn: 336547
2018-07-09 21:23:41 +08:00
|
|
|
class sve_int_bin_pred_shift_imm<bits<4> tsz8_64, bits<3> opc, string asm,
|
|
|
|
ZPRRegOp zprty, Operand immtype>
|
|
|
|
: I<(outs zprty:$Zdn), (ins PPR3bAny:$Pg, zprty:$_Zdn, immtype:$imm),
|
|
|
|
asm, "\t$Zdn, $Pg/m, $_Zdn, $imm",
|
|
|
|
"",
|
|
|
|
[]>, Sched<[]> {
|
|
|
|
bits<3> Pg;
|
|
|
|
bits<5> Zdn;
|
|
|
|
bits<6> imm;
|
|
|
|
let Inst{31-24} = 0b00000100;
|
|
|
|
let Inst{23-22} = tsz8_64{3-2};
|
|
|
|
let Inst{21-19} = 0b000;
|
|
|
|
let Inst{18-16} = opc;
|
|
|
|
let Inst{15-13} = 0b100;
|
|
|
|
let Inst{12-10} = Pg;
|
|
|
|
let Inst{9-8} = tsz8_64{1-0};
|
|
|
|
let Inst{7-5} = imm{2-0}; // imm3
|
|
|
|
let Inst{4-0} = Zdn;
|
|
|
|
|
|
|
|
let Constraints = "$Zdn = $_Zdn";
|
|
|
|
}
|
|
|
|
|
|
|
|
multiclass sve_int_bin_pred_shift_imm_left<bits<3> opc, string asm> {
|
|
|
|
def _B : sve_int_bin_pred_shift_imm<{0,0,0,1}, opc, asm, ZPR8, vecshiftL8>;
|
|
|
|
def _H : sve_int_bin_pred_shift_imm<{0,0,1,?}, opc, asm, ZPR16, vecshiftL16> {
|
|
|
|
let Inst{8} = imm{3};
|
|
|
|
}
|
|
|
|
def _S : sve_int_bin_pred_shift_imm<{0,1,?,?}, opc, asm, ZPR32, vecshiftL32> {
|
|
|
|
let Inst{9-8} = imm{4-3};
|
|
|
|
}
|
|
|
|
def _D : sve_int_bin_pred_shift_imm<{1,?,?,?}, opc, asm, ZPR64, vecshiftL64> {
|
|
|
|
let Inst{22} = imm{5};
|
|
|
|
let Inst{9-8} = imm{4-3};
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
multiclass sve_int_bin_pred_shift_imm_right<bits<3> opc, string asm> {
|
|
|
|
def _B : sve_int_bin_pred_shift_imm<{0,0,0,1}, opc, asm, ZPR8, vecshiftR8>;
|
|
|
|
def _H : sve_int_bin_pred_shift_imm<{0,0,1,?}, opc, asm, ZPR16, vecshiftR16> {
|
|
|
|
let Inst{8} = imm{3};
|
|
|
|
}
|
|
|
|
def _S : sve_int_bin_pred_shift_imm<{0,1,?,?}, opc, asm, ZPR32, vecshiftR32> {
|
|
|
|
let Inst{9-8} = imm{4-3};
|
|
|
|
}
|
|
|
|
def _D : sve_int_bin_pred_shift_imm<{1,?,?,?}, opc, asm, ZPR64, vecshiftR64> {
|
|
|
|
let Inst{22} = imm{5};
|
|
|
|
let Inst{9-8} = imm{4-3};
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
class sve_int_bin_pred_shift<bits<2> sz8_64, bit wide, bits<3> opc,
|
|
|
|
string asm, ZPRRegOp zprty, ZPRRegOp zprty2>
|
|
|
|
: I<(outs zprty:$Zdn), (ins PPR3bAny:$Pg, zprty:$_Zdn, zprty2:$Zm),
|
2018-05-29 22:40:24 +08:00
|
|
|
asm, "\t$Zdn, $Pg/m, $_Zdn, $Zm",
|
|
|
|
"",
|
|
|
|
[]>, Sched<[]> {
|
|
|
|
bits<3> Pg;
|
|
|
|
bits<5> Zdn;
|
|
|
|
bits<5> Zm;
|
|
|
|
let Inst{31-24} = 0b00000100;
|
|
|
|
let Inst{23-22} = sz8_64;
|
[AArch64][SVE] Asm: Support for remaining shift instructions.
This patch completes support for shifts, which include:
- LSL - Logical Shift Left
- LSLR - Logical Shift Left, Reversed form
- LSR - Logical Shift Right
- LSRR - Logical Shift Right, Reversed form
- ASR - Arithmetic Shift Right
- ASRR - Arithmetic Shift Right, Reversed form
- ASRD - Arithmetic Shift Right for Divide
In the following variants:
- Predicated shift by immediate - ASR, LSL, LSR, ASRD
e.g.
asr z0.h, p0/m, z0.h, #1
(active lanes of z0 shifted by #1)
- Unpredicated shift by immediate - ASR, LSL*, LSR*
e.g.
asr z0.h, z1.h, #1
(all lanes of z1 shifted by #1, stored in z0)
- Predicated shift by vector - ASR, LSL*, LSR*
e.g.
asr z0.h, p0/m, z0.h, z1.h
(active lanes of z0 shifted by z1, stored in z0)
- Predicated shift by vector, reversed form - ASRR, LSLR, LSRR
e.g.
lslr z0.h, p0/m, z0.h, z1.h
(active lanes of z1 shifted by z0, stored in z0)
- Predicated shift left/right by wide vector - ASR, LSL, LSR
e.g.
lsl z0.h, p0/m, z0.h, z1.d
(active lanes of z0 shifted by wide elements of vector z1)
- Unpredicated shift left/right by wide vector - ASR, LSL, LSR
e.g.
lsl z0.h, z1.h, z2.d
(all lanes of z1 shifted by wide elements of z2, stored in z0)
*Variants added in previous patches.
llvm-svn: 336547
2018-07-09 21:23:41 +08:00
|
|
|
let Inst{21-20} = 0b01;
|
|
|
|
let Inst{19} = wide;
|
2018-05-29 22:40:24 +08:00
|
|
|
let Inst{18-16} = opc;
|
|
|
|
let Inst{15-13} = 0b100;
|
|
|
|
let Inst{12-10} = Pg;
|
|
|
|
let Inst{9-5} = Zm;
|
|
|
|
let Inst{4-0} = Zdn;
|
|
|
|
|
|
|
|
let Constraints = "$Zdn = $_Zdn";
|
|
|
|
}
|
|
|
|
|
[AArch64][SVE] Asm: Support for remaining shift instructions.
This patch completes support for shifts, which include:
- LSL - Logical Shift Left
- LSLR - Logical Shift Left, Reversed form
- LSR - Logical Shift Right
- LSRR - Logical Shift Right, Reversed form
- ASR - Arithmetic Shift Right
- ASRR - Arithmetic Shift Right, Reversed form
- ASRD - Arithmetic Shift Right for Divide
In the following variants:
- Predicated shift by immediate - ASR, LSL, LSR, ASRD
e.g.
asr z0.h, p0/m, z0.h, #1
(active lanes of z0 shifted by #1)
- Unpredicated shift by immediate - ASR, LSL*, LSR*
e.g.
asr z0.h, z1.h, #1
(all lanes of z1 shifted by #1, stored in z0)
- Predicated shift by vector - ASR, LSL*, LSR*
e.g.
asr z0.h, p0/m, z0.h, z1.h
(active lanes of z0 shifted by z1, stored in z0)
- Predicated shift by vector, reversed form - ASRR, LSLR, LSRR
e.g.
lslr z0.h, p0/m, z0.h, z1.h
(active lanes of z1 shifted by z0, stored in z0)
- Predicated shift left/right by wide vector - ASR, LSL, LSR
e.g.
lsl z0.h, p0/m, z0.h, z1.d
(active lanes of z0 shifted by wide elements of vector z1)
- Unpredicated shift left/right by wide vector - ASR, LSL, LSR
e.g.
lsl z0.h, z1.h, z2.d
(all lanes of z1 shifted by wide elements of z2, stored in z0)
*Variants added in previous patches.
llvm-svn: 336547
2018-07-09 21:23:41 +08:00
|
|
|
multiclass sve_int_bin_pred_shift<bits<3> opc, string asm> {
|
|
|
|
def _B : sve_int_bin_pred_shift<0b00, 0b0, opc, asm, ZPR8, ZPR8>;
|
|
|
|
def _H : sve_int_bin_pred_shift<0b01, 0b0, opc, asm, ZPR16, ZPR16>;
|
|
|
|
def _S : sve_int_bin_pred_shift<0b10, 0b0, opc, asm, ZPR32, ZPR32>;
|
|
|
|
def _D : sve_int_bin_pred_shift<0b11, 0b0, opc, asm, ZPR64, ZPR64>;
|
2018-05-29 22:40:24 +08:00
|
|
|
}
|
|
|
|
|
[AArch64][SVE] Asm: Support for remaining shift instructions.
This patch completes support for shifts, which include:
- LSL - Logical Shift Left
- LSLR - Logical Shift Left, Reversed form
- LSR - Logical Shift Right
- LSRR - Logical Shift Right, Reversed form
- ASR - Arithmetic Shift Right
- ASRR - Arithmetic Shift Right, Reversed form
- ASRD - Arithmetic Shift Right for Divide
In the following variants:
- Predicated shift by immediate - ASR, LSL, LSR, ASRD
e.g.
asr z0.h, p0/m, z0.h, #1
(active lanes of z0 shifted by #1)
- Unpredicated shift by immediate - ASR, LSL*, LSR*
e.g.
asr z0.h, z1.h, #1
(all lanes of z1 shifted by #1, stored in z0)
- Predicated shift by vector - ASR, LSL*, LSR*
e.g.
asr z0.h, p0/m, z0.h, z1.h
(active lanes of z0 shifted by z1, stored in z0)
- Predicated shift by vector, reversed form - ASRR, LSLR, LSRR
e.g.
lslr z0.h, p0/m, z0.h, z1.h
(active lanes of z1 shifted by z0, stored in z0)
- Predicated shift left/right by wide vector - ASR, LSL, LSR
e.g.
lsl z0.h, p0/m, z0.h, z1.d
(active lanes of z0 shifted by wide elements of vector z1)
- Unpredicated shift left/right by wide vector - ASR, LSL, LSR
e.g.
lsl z0.h, z1.h, z2.d
(all lanes of z1 shifted by wide elements of z2, stored in z0)
*Variants added in previous patches.
llvm-svn: 336547
2018-07-09 21:23:41 +08:00
|
|
|
multiclass sve_int_bin_pred_shift_wide<bits<3> opc, string asm> {
|
|
|
|
def _B : sve_int_bin_pred_shift<0b00, 0b1, opc, asm, ZPR8, ZPR64>;
|
|
|
|
def _H : sve_int_bin_pred_shift<0b01, 0b1, opc, asm, ZPR16, ZPR64>;
|
|
|
|
def _S : sve_int_bin_pred_shift<0b10, 0b1, opc, asm, ZPR32, ZPR64>;
|
|
|
|
}
|
[AArch64][SVE] Asm: Add support for SVE INDEX instructions.
Reviewers: rengolin, fhahn, javed.absar, SjoerdMeijer, huntergr, t.p.northover, echristo, evandro
Reviewed By: rengolin, fhahn
Subscribers: tschuett, llvm-commits, kristof.beyls
Differential Revision: https://reviews.llvm.org/D45370
llvm-svn: 329674
2018-04-10 15:01:53 +08:00
|
|
|
|
2018-01-10 01:01:27 +08:00
|
|
|
//===----------------------------------------------------------------------===//
|
[AArch64][SVE] Asm: Support for remaining shift instructions.
This patch completes support for shifts, which include:
- LSL - Logical Shift Left
- LSLR - Logical Shift Left, Reversed form
- LSR - Logical Shift Right
- LSRR - Logical Shift Right, Reversed form
- ASR - Arithmetic Shift Right
- ASRR - Arithmetic Shift Right, Reversed form
- ASRD - Arithmetic Shift Right for Divide
In the following variants:
- Predicated shift by immediate - ASR, LSL, LSR, ASRD
e.g.
asr z0.h, p0/m, z0.h, #1
(active lanes of z0 shifted by #1)
- Unpredicated shift by immediate - ASR, LSL*, LSR*
e.g.
asr z0.h, z1.h, #1
(all lanes of z1 shifted by #1, stored in z0)
- Predicated shift by vector - ASR, LSL*, LSR*
e.g.
asr z0.h, p0/m, z0.h, z1.h
(active lanes of z0 shifted by z1, stored in z0)
- Predicated shift by vector, reversed form - ASRR, LSLR, LSRR
e.g.
lslr z0.h, p0/m, z0.h, z1.h
(active lanes of z1 shifted by z0, stored in z0)
- Predicated shift left/right by wide vector - ASR, LSL, LSR
e.g.
lsl z0.h, p0/m, z0.h, z1.d
(active lanes of z0 shifted by wide elements of vector z1)
- Unpredicated shift left/right by wide vector - ASR, LSL, LSR
e.g.
lsl z0.h, z1.h, z2.d
(all lanes of z1 shifted by wide elements of z2, stored in z0)
*Variants added in previous patches.
llvm-svn: 336547
2018-07-09 21:23:41 +08:00
|
|
|
// SVE Shift - Unpredicated Group
|
[AArch64][SVE] Asm: Add support for unpredicated LSL/LSR (shift by immediate) instructions.
Reviewers: rengolin, fhahn, javed.absar, SjoerdMeijer, huntergr, t.p.northover, echristo, evandro
Reviewed By: rengolin, fhahn
Subscribers: tschuett, kristof.beyls, llvm-commits
Differential Revision: https://reviews.llvm.org/D45371
llvm-svn: 329681
2018-04-10 18:03:13 +08:00
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
|
[AArch64][SVE] Asm: Support for remaining shift instructions.
This patch completes support for shifts, which include:
- LSL - Logical Shift Left
- LSLR - Logical Shift Left, Reversed form
- LSR - Logical Shift Right
- LSRR - Logical Shift Right, Reversed form
- ASR - Arithmetic Shift Right
- ASRR - Arithmetic Shift Right, Reversed form
- ASRD - Arithmetic Shift Right for Divide
In the following variants:
- Predicated shift by immediate - ASR, LSL, LSR, ASRD
e.g.
asr z0.h, p0/m, z0.h, #1
(active lanes of z0 shifted by #1)
- Unpredicated shift by immediate - ASR, LSL*, LSR*
e.g.
asr z0.h, z1.h, #1
(all lanes of z1 shifted by #1, stored in z0)
- Predicated shift by vector - ASR, LSL*, LSR*
e.g.
asr z0.h, p0/m, z0.h, z1.h
(active lanes of z0 shifted by z1, stored in z0)
- Predicated shift by vector, reversed form - ASRR, LSLR, LSRR
e.g.
lslr z0.h, p0/m, z0.h, z1.h
(active lanes of z1 shifted by z0, stored in z0)
- Predicated shift left/right by wide vector - ASR, LSL, LSR
e.g.
lsl z0.h, p0/m, z0.h, z1.d
(active lanes of z0 shifted by wide elements of vector z1)
- Unpredicated shift left/right by wide vector - ASR, LSL, LSR
e.g.
lsl z0.h, z1.h, z2.d
(all lanes of z1 shifted by wide elements of z2, stored in z0)
*Variants added in previous patches.
llvm-svn: 336547
2018-07-09 21:23:41 +08:00
|
|
|
class sve_int_bin_cons_shift_wide<bits<2> sz8_64, bits<2> opc, string asm,
|
|
|
|
ZPRRegOp zprty>
|
|
|
|
: I<(outs zprty:$Zd), (ins zprty:$Zn, ZPR64:$Zm),
|
|
|
|
asm, "\t$Zd, $Zn, $Zm",
|
|
|
|
"",
|
|
|
|
[]>, Sched<[]> {
|
|
|
|
bits<5> Zd;
|
|
|
|
bits<5> Zm;
|
|
|
|
bits<5> Zn;
|
|
|
|
let Inst{31-24} = 0b00000100;
|
|
|
|
let Inst{23-22} = sz8_64;
|
|
|
|
let Inst{21} = 0b1;
|
|
|
|
let Inst{20-16} = Zm;
|
|
|
|
let Inst{15-12} = 0b1000;
|
|
|
|
let Inst{11-10} = opc;
|
|
|
|
let Inst{9-5} = Zn;
|
|
|
|
let Inst{4-0} = Zd;
|
|
|
|
}
|
|
|
|
|
|
|
|
multiclass sve_int_bin_cons_shift_wide<bits<2> opc, string asm> {
|
|
|
|
def _B : sve_int_bin_cons_shift_wide<0b00, opc, asm, ZPR8>;
|
|
|
|
def _H : sve_int_bin_cons_shift_wide<0b01, opc, asm, ZPR16>;
|
|
|
|
def _S : sve_int_bin_cons_shift_wide<0b10, opc, asm, ZPR32>;
|
|
|
|
}
|
|
|
|
|
|
|
|
class sve_int_bin_cons_shift_imm<bits<4> tsz8_64, bits<2> opc, string asm,
|
[AArch64][SVE] Asm: Add support for unpredicated LSL/LSR (shift by immediate) instructions.
Reviewers: rengolin, fhahn, javed.absar, SjoerdMeijer, huntergr, t.p.northover, echristo, evandro
Reviewed By: rengolin, fhahn
Subscribers: tschuett, kristof.beyls, llvm-commits
Differential Revision: https://reviews.llvm.org/D45371
llvm-svn: 329681
2018-04-10 18:03:13 +08:00
|
|
|
ZPRRegOp zprty, Operand immtype>
|
|
|
|
: I<(outs zprty:$Zd), (ins zprty:$Zn, immtype:$imm),
|
|
|
|
asm, "\t$Zd, $Zn, $imm",
|
|
|
|
"", []>, Sched<[]> {
|
|
|
|
bits<5> Zd;
|
|
|
|
bits<5> Zn;
|
|
|
|
bits<6> imm;
|
|
|
|
let Inst{31-24} = 0b00000100;
|
|
|
|
let Inst{23-22} = tsz8_64{3-2};
|
|
|
|
let Inst{21} = 0b1;
|
|
|
|
let Inst{20-19} = tsz8_64{1-0};
|
|
|
|
let Inst{18-16} = imm{2-0}; // imm3
|
|
|
|
let Inst{15-12} = 0b1001;
|
|
|
|
let Inst{11-10} = opc;
|
|
|
|
let Inst{9-5} = Zn;
|
|
|
|
let Inst{4-0} = Zd;
|
|
|
|
}
|
|
|
|
|
[AArch64][SVE] Asm: Support for remaining shift instructions.
This patch completes support for shifts, which include:
- LSL - Logical Shift Left
- LSLR - Logical Shift Left, Reversed form
- LSR - Logical Shift Right
- LSRR - Logical Shift Right, Reversed form
- ASR - Arithmetic Shift Right
- ASRR - Arithmetic Shift Right, Reversed form
- ASRD - Arithmetic Shift Right for Divide
In the following variants:
- Predicated shift by immediate - ASR, LSL, LSR, ASRD
e.g.
asr z0.h, p0/m, z0.h, #1
(active lanes of z0 shifted by #1)
- Unpredicated shift by immediate - ASR, LSL*, LSR*
e.g.
asr z0.h, z1.h, #1
(all lanes of z1 shifted by #1, stored in z0)
- Predicated shift by vector - ASR, LSL*, LSR*
e.g.
asr z0.h, p0/m, z0.h, z1.h
(active lanes of z0 shifted by z1, stored in z0)
- Predicated shift by vector, reversed form - ASRR, LSLR, LSRR
e.g.
lslr z0.h, p0/m, z0.h, z1.h
(active lanes of z1 shifted by z0, stored in z0)
- Predicated shift left/right by wide vector - ASR, LSL, LSR
e.g.
lsl z0.h, p0/m, z0.h, z1.d
(active lanes of z0 shifted by wide elements of vector z1)
- Unpredicated shift left/right by wide vector - ASR, LSL, LSR
e.g.
lsl z0.h, z1.h, z2.d
(all lanes of z1 shifted by wide elements of z2, stored in z0)
*Variants added in previous patches.
llvm-svn: 336547
2018-07-09 21:23:41 +08:00
|
|
|
multiclass sve_int_bin_cons_shift_imm_left<bits<2> opc, string asm> {
|
|
|
|
def _B : sve_int_bin_cons_shift_imm<{0,0,0,1}, opc, asm, ZPR8, vecshiftL8>;
|
|
|
|
def _H : sve_int_bin_cons_shift_imm<{0,0,1,?}, opc, asm, ZPR16, vecshiftL16> {
|
[AArch64][SVE] Asm: Add support for unpredicated LSL/LSR (shift by immediate) instructions.
Reviewers: rengolin, fhahn, javed.absar, SjoerdMeijer, huntergr, t.p.northover, echristo, evandro
Reviewed By: rengolin, fhahn
Subscribers: tschuett, kristof.beyls, llvm-commits
Differential Revision: https://reviews.llvm.org/D45371
llvm-svn: 329681
2018-04-10 18:03:13 +08:00
|
|
|
let Inst{19} = imm{3};
|
|
|
|
}
|
[AArch64][SVE] Asm: Support for remaining shift instructions.
This patch completes support for shifts, which include:
- LSL - Logical Shift Left
- LSLR - Logical Shift Left, Reversed form
- LSR - Logical Shift Right
- LSRR - Logical Shift Right, Reversed form
- ASR - Arithmetic Shift Right
- ASRR - Arithmetic Shift Right, Reversed form
- ASRD - Arithmetic Shift Right for Divide
In the following variants:
- Predicated shift by immediate - ASR, LSL, LSR, ASRD
e.g.
asr z0.h, p0/m, z0.h, #1
(active lanes of z0 shifted by #1)
- Unpredicated shift by immediate - ASR, LSL*, LSR*
e.g.
asr z0.h, z1.h, #1
(all lanes of z1 shifted by #1, stored in z0)
- Predicated shift by vector - ASR, LSL*, LSR*
e.g.
asr z0.h, p0/m, z0.h, z1.h
(active lanes of z0 shifted by z1, stored in z0)
- Predicated shift by vector, reversed form - ASRR, LSLR, LSRR
e.g.
lslr z0.h, p0/m, z0.h, z1.h
(active lanes of z1 shifted by z0, stored in z0)
- Predicated shift left/right by wide vector - ASR, LSL, LSR
e.g.
lsl z0.h, p0/m, z0.h, z1.d
(active lanes of z0 shifted by wide elements of vector z1)
- Unpredicated shift left/right by wide vector - ASR, LSL, LSR
e.g.
lsl z0.h, z1.h, z2.d
(all lanes of z1 shifted by wide elements of z2, stored in z0)
*Variants added in previous patches.
llvm-svn: 336547
2018-07-09 21:23:41 +08:00
|
|
|
def _S : sve_int_bin_cons_shift_imm<{0,1,?,?}, opc, asm, ZPR32, vecshiftL32> {
|
[AArch64][SVE] Asm: Add support for unpredicated LSL/LSR (shift by immediate) instructions.
Reviewers: rengolin, fhahn, javed.absar, SjoerdMeijer, huntergr, t.p.northover, echristo, evandro
Reviewed By: rengolin, fhahn
Subscribers: tschuett, kristof.beyls, llvm-commits
Differential Revision: https://reviews.llvm.org/D45371
llvm-svn: 329681
2018-04-10 18:03:13 +08:00
|
|
|
let Inst{20-19} = imm{4-3};
|
|
|
|
}
|
[AArch64][SVE] Asm: Support for remaining shift instructions.
This patch completes support for shifts, which include:
- LSL - Logical Shift Left
- LSLR - Logical Shift Left, Reversed form
- LSR - Logical Shift Right
- LSRR - Logical Shift Right, Reversed form
- ASR - Arithmetic Shift Right
- ASRR - Arithmetic Shift Right, Reversed form
- ASRD - Arithmetic Shift Right for Divide
In the following variants:
- Predicated shift by immediate - ASR, LSL, LSR, ASRD
e.g.
asr z0.h, p0/m, z0.h, #1
(active lanes of z0 shifted by #1)
- Unpredicated shift by immediate - ASR, LSL*, LSR*
e.g.
asr z0.h, z1.h, #1
(all lanes of z1 shifted by #1, stored in z0)
- Predicated shift by vector - ASR, LSL*, LSR*
e.g.
asr z0.h, p0/m, z0.h, z1.h
(active lanes of z0 shifted by z1, stored in z0)
- Predicated shift by vector, reversed form - ASRR, LSLR, LSRR
e.g.
lslr z0.h, p0/m, z0.h, z1.h
(active lanes of z1 shifted by z0, stored in z0)
- Predicated shift left/right by wide vector - ASR, LSL, LSR
e.g.
lsl z0.h, p0/m, z0.h, z1.d
(active lanes of z0 shifted by wide elements of vector z1)
- Unpredicated shift left/right by wide vector - ASR, LSL, LSR
e.g.
lsl z0.h, z1.h, z2.d
(all lanes of z1 shifted by wide elements of z2, stored in z0)
*Variants added in previous patches.
llvm-svn: 336547
2018-07-09 21:23:41 +08:00
|
|
|
def _D : sve_int_bin_cons_shift_imm<{1,?,?,?}, opc, asm, ZPR64, vecshiftL64> {
|
[AArch64][SVE] Asm: Add support for unpredicated LSL/LSR (shift by immediate) instructions.
Reviewers: rengolin, fhahn, javed.absar, SjoerdMeijer, huntergr, t.p.northover, echristo, evandro
Reviewed By: rengolin, fhahn
Subscribers: tschuett, kristof.beyls, llvm-commits
Differential Revision: https://reviews.llvm.org/D45371
llvm-svn: 329681
2018-04-10 18:03:13 +08:00
|
|
|
let Inst{22} = imm{5};
|
|
|
|
let Inst{20-19} = imm{4-3};
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
[AArch64][SVE] Asm: Support for remaining shift instructions.
This patch completes support for shifts, which include:
- LSL - Logical Shift Left
- LSLR - Logical Shift Left, Reversed form
- LSR - Logical Shift Right
- LSRR - Logical Shift Right, Reversed form
- ASR - Arithmetic Shift Right
- ASRR - Arithmetic Shift Right, Reversed form
- ASRD - Arithmetic Shift Right for Divide
In the following variants:
- Predicated shift by immediate - ASR, LSL, LSR, ASRD
e.g.
asr z0.h, p0/m, z0.h, #1
(active lanes of z0 shifted by #1)
- Unpredicated shift by immediate - ASR, LSL*, LSR*
e.g.
asr z0.h, z1.h, #1
(all lanes of z1 shifted by #1, stored in z0)
- Predicated shift by vector - ASR, LSL*, LSR*
e.g.
asr z0.h, p0/m, z0.h, z1.h
(active lanes of z0 shifted by z1, stored in z0)
- Predicated shift by vector, reversed form - ASRR, LSLR, LSRR
e.g.
lslr z0.h, p0/m, z0.h, z1.h
(active lanes of z1 shifted by z0, stored in z0)
- Predicated shift left/right by wide vector - ASR, LSL, LSR
e.g.
lsl z0.h, p0/m, z0.h, z1.d
(active lanes of z0 shifted by wide elements of vector z1)
- Unpredicated shift left/right by wide vector - ASR, LSL, LSR
e.g.
lsl z0.h, z1.h, z2.d
(all lanes of z1 shifted by wide elements of z2, stored in z0)
*Variants added in previous patches.
llvm-svn: 336547
2018-07-09 21:23:41 +08:00
|
|
|
multiclass sve_int_bin_cons_shift_imm_right<bits<2> opc, string asm> {
|
|
|
|
def _B : sve_int_bin_cons_shift_imm<{0,0,0,1}, opc, asm, ZPR8, vecshiftR8>;
|
|
|
|
def _H : sve_int_bin_cons_shift_imm<{0,0,1,?}, opc, asm, ZPR16, vecshiftR16> {
|
[AArch64][SVE] Asm: Add support for unpredicated LSL/LSR (shift by immediate) instructions.
Reviewers: rengolin, fhahn, javed.absar, SjoerdMeijer, huntergr, t.p.northover, echristo, evandro
Reviewed By: rengolin, fhahn
Subscribers: tschuett, kristof.beyls, llvm-commits
Differential Revision: https://reviews.llvm.org/D45371
llvm-svn: 329681
2018-04-10 18:03:13 +08:00
|
|
|
let Inst{19} = imm{3};
|
|
|
|
}
|
[AArch64][SVE] Asm: Support for remaining shift instructions.
This patch completes support for shifts, which include:
- LSL - Logical Shift Left
- LSLR - Logical Shift Left, Reversed form
- LSR - Logical Shift Right
- LSRR - Logical Shift Right, Reversed form
- ASR - Arithmetic Shift Right
- ASRR - Arithmetic Shift Right, Reversed form
- ASRD - Arithmetic Shift Right for Divide
In the following variants:
- Predicated shift by immediate - ASR, LSL, LSR, ASRD
e.g.
asr z0.h, p0/m, z0.h, #1
(active lanes of z0 shifted by #1)
- Unpredicated shift by immediate - ASR, LSL*, LSR*
e.g.
asr z0.h, z1.h, #1
(all lanes of z1 shifted by #1, stored in z0)
- Predicated shift by vector - ASR, LSL*, LSR*
e.g.
asr z0.h, p0/m, z0.h, z1.h
(active lanes of z0 shifted by z1, stored in z0)
- Predicated shift by vector, reversed form - ASRR, LSLR, LSRR
e.g.
lslr z0.h, p0/m, z0.h, z1.h
(active lanes of z1 shifted by z0, stored in z0)
- Predicated shift left/right by wide vector - ASR, LSL, LSR
e.g.
lsl z0.h, p0/m, z0.h, z1.d
(active lanes of z0 shifted by wide elements of vector z1)
- Unpredicated shift left/right by wide vector - ASR, LSL, LSR
e.g.
lsl z0.h, z1.h, z2.d
(all lanes of z1 shifted by wide elements of z2, stored in z0)
*Variants added in previous patches.
llvm-svn: 336547
2018-07-09 21:23:41 +08:00
|
|
|
def _S : sve_int_bin_cons_shift_imm<{0,1,?,?}, opc, asm, ZPR32, vecshiftR32> {
|
[AArch64][SVE] Asm: Add support for unpredicated LSL/LSR (shift by immediate) instructions.
Reviewers: rengolin, fhahn, javed.absar, SjoerdMeijer, huntergr, t.p.northover, echristo, evandro
Reviewed By: rengolin, fhahn
Subscribers: tschuett, kristof.beyls, llvm-commits
Differential Revision: https://reviews.llvm.org/D45371
llvm-svn: 329681
2018-04-10 18:03:13 +08:00
|
|
|
let Inst{20-19} = imm{4-3};
|
|
|
|
}
|
[AArch64][SVE] Asm: Support for remaining shift instructions.
This patch completes support for shifts, which include:
- LSL - Logical Shift Left
- LSLR - Logical Shift Left, Reversed form
- LSR - Logical Shift Right
- LSRR - Logical Shift Right, Reversed form
- ASR - Arithmetic Shift Right
- ASRR - Arithmetic Shift Right, Reversed form
- ASRD - Arithmetic Shift Right for Divide
In the following variants:
- Predicated shift by immediate - ASR, LSL, LSR, ASRD
e.g.
asr z0.h, p0/m, z0.h, #1
(active lanes of z0 shifted by #1)
- Unpredicated shift by immediate - ASR, LSL*, LSR*
e.g.
asr z0.h, z1.h, #1
(all lanes of z1 shifted by #1, stored in z0)
- Predicated shift by vector - ASR, LSL*, LSR*
e.g.
asr z0.h, p0/m, z0.h, z1.h
(active lanes of z0 shifted by z1, stored in z0)
- Predicated shift by vector, reversed form - ASRR, LSLR, LSRR
e.g.
lslr z0.h, p0/m, z0.h, z1.h
(active lanes of z1 shifted by z0, stored in z0)
- Predicated shift left/right by wide vector - ASR, LSL, LSR
e.g.
lsl z0.h, p0/m, z0.h, z1.d
(active lanes of z0 shifted by wide elements of vector z1)
- Unpredicated shift left/right by wide vector - ASR, LSL, LSR
e.g.
lsl z0.h, z1.h, z2.d
(all lanes of z1 shifted by wide elements of z2, stored in z0)
*Variants added in previous patches.
llvm-svn: 336547
2018-07-09 21:23:41 +08:00
|
|
|
def _D : sve_int_bin_cons_shift_imm<{1,?,?,?}, opc, asm, ZPR64, vecshiftR64> {
|
[AArch64][SVE] Asm: Add support for unpredicated LSL/LSR (shift by immediate) instructions.
Reviewers: rengolin, fhahn, javed.absar, SjoerdMeijer, huntergr, t.p.northover, echristo, evandro
Reviewed By: rengolin, fhahn
Subscribers: tschuett, kristof.beyls, llvm-commits
Differential Revision: https://reviews.llvm.org/D45371
llvm-svn: 329681
2018-04-10 18:03:13 +08:00
|
|
|
let Inst{22} = imm{5};
|
|
|
|
let Inst{20-19} = imm{4-3};
|
|
|
|
}
|
|
|
|
}
|
|
|
|
//===----------------------------------------------------------------------===//
|
[AArch64][SVE] Asm: Support for contiguous ST1 (scalar+imm) store instructions.
Summary:
Added instructions for contiguous stores, ST1, with scalar+imm addressing
modes and corresponding tests. The patch also adds parsing of
'mul vl' as needed for the VL-scaled immediate.
This is patch [6/6] in a series to add assembler/disassembler support for
SVE's contiguous ST1 (scalar+imm) instructions.
Reviewers: fhahn, rengolin, javed.absar, huntergr, SjoerdMeijer, t.p.northover, echristo, evandro
Reviewed By: rengolin
Subscribers: tschuett, llvm-commits, kristof.beyls
Differential Revision: https://reviews.llvm.org/D45432
llvm-svn: 330014
2018-04-13 20:56:14 +08:00
|
|
|
// SVE Memory - Store Group
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
|
|
|
|
class sve_mem_cst_si<bits<2> msz, bits<2> esz, string asm,
|
|
|
|
RegisterOperand VecList>
|
2018-04-30 02:18:21 +08:00
|
|
|
: I<(outs), (ins VecList:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, simm4s1:$imm4),
|
[AArch64][SVE] Asm: Support for contiguous ST1 (scalar+imm) store instructions.
Summary:
Added instructions for contiguous stores, ST1, with scalar+imm addressing
modes and corresponding tests. The patch also adds parsing of
'mul vl' as needed for the VL-scaled immediate.
This is patch [6/6] in a series to add assembler/disassembler support for
SVE's contiguous ST1 (scalar+imm) instructions.
Reviewers: fhahn, rengolin, javed.absar, huntergr, SjoerdMeijer, t.p.northover, echristo, evandro
Reviewed By: rengolin
Subscribers: tschuett, llvm-commits, kristof.beyls
Differential Revision: https://reviews.llvm.org/D45432
llvm-svn: 330014
2018-04-13 20:56:14 +08:00
|
|
|
asm, "\t$Zt, $Pg, [$Rn, $imm4, mul vl]",
|
|
|
|
"",
|
|
|
|
[]>, Sched<[]> {
|
|
|
|
bits<3> Pg;
|
|
|
|
bits<5> Rn;
|
|
|
|
bits<5> Zt;
|
|
|
|
bits<4> imm4;
|
|
|
|
let Inst{31-25} = 0b1110010;
|
|
|
|
let Inst{24-23} = msz;
|
|
|
|
let Inst{22-21} = esz;
|
|
|
|
let Inst{20} = 0;
|
|
|
|
let Inst{19-16} = imm4;
|
|
|
|
let Inst{15-13} = 0b111;
|
|
|
|
let Inst{12-10} = Pg;
|
|
|
|
let Inst{9-5} = Rn;
|
|
|
|
let Inst{4-0} = Zt;
|
|
|
|
|
|
|
|
let mayStore = 1;
|
|
|
|
}
|
|
|
|
|
|
|
|
multiclass sve_mem_cst_si<bits<2> msz, bits<2> esz, string asm,
|
|
|
|
RegisterOperand listty, ZPRRegOp zprty>
|
|
|
|
{
|
|
|
|
def NAME : sve_mem_cst_si<msz, esz, asm, listty>;
|
|
|
|
|
|
|
|
def : InstAlias<asm # "\t$Zt, $Pg, [$Rn, $imm4, mul vl]",
|
2018-04-30 02:18:21 +08:00
|
|
|
(!cast<Instruction>(NAME) zprty:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, simm4s1:$imm4), 0>;
|
[AArch64][SVE] Asm: Support for contiguous ST1 (scalar+imm) store instructions.
Summary:
Added instructions for contiguous stores, ST1, with scalar+imm addressing
modes and corresponding tests. The patch also adds parsing of
'mul vl' as needed for the VL-scaled immediate.
This is patch [6/6] in a series to add assembler/disassembler support for
SVE's contiguous ST1 (scalar+imm) instructions.
Reviewers: fhahn, rengolin, javed.absar, huntergr, SjoerdMeijer, t.p.northover, echristo, evandro
Reviewed By: rengolin
Subscribers: tschuett, llvm-commits, kristof.beyls
Differential Revision: https://reviews.llvm.org/D45432
llvm-svn: 330014
2018-04-13 20:56:14 +08:00
|
|
|
def : InstAlias<asm # "\t$Zt, $Pg, [$Rn]",
|
|
|
|
(!cast<Instruction>(NAME) zprty:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0), 0>;
|
|
|
|
def : InstAlias<asm # "\t$Zt, $Pg, [$Rn]",
|
|
|
|
(!cast<Instruction>(NAME) listty:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0), 1>;
|
|
|
|
}
|
|
|
|
|
[AArch64][SVE] Asm: Support for structured ST2, ST3 and ST4 (scalar+imm) store instructions.
Reviewers: fhahn, rengolin, javed.absar, SjoerdMeijer, t.p.northover, echristo, evandro, huntergr
Reviewed By: rengolin
Subscribers: tschuett, kristof.beyls, llvm-commits
Differential Revision: https://reviews.llvm.org/D45681
llvm-svn: 330565
2018-04-23 15:50:35 +08:00
|
|
|
class sve_mem_est_si<bits<2> sz, bits<2> nregs, RegisterOperand VecList,
|
|
|
|
string asm, Operand immtype>
|
|
|
|
: I<(outs), (ins VecList:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, immtype:$imm4),
|
|
|
|
asm, "\t$Zt, $Pg, [$Rn, $imm4, mul vl]",
|
|
|
|
"",
|
|
|
|
[]>, Sched<[]> {
|
|
|
|
bits<3> Pg;
|
|
|
|
bits<5> Rn;
|
|
|
|
bits<5> Zt;
|
|
|
|
bits<4> imm4;
|
|
|
|
let Inst{31-25} = 0b1110010;
|
|
|
|
let Inst{24-23} = sz;
|
|
|
|
let Inst{22-21} = nregs;
|
|
|
|
let Inst{20} = 1;
|
|
|
|
let Inst{19-16} = imm4;
|
|
|
|
let Inst{15-13} = 0b111;
|
|
|
|
let Inst{12-10} = Pg;
|
|
|
|
let Inst{9-5} = Rn;
|
|
|
|
let Inst{4-0} = Zt;
|
|
|
|
|
|
|
|
let mayStore = 1;
|
|
|
|
}
|
|
|
|
|
|
|
|
multiclass sve_mem_est_si<bits<2> sz, bits<2> nregs, RegisterOperand VecList,
|
|
|
|
string asm, Operand immtype> {
|
|
|
|
def NAME : sve_mem_est_si<sz, nregs, VecList, asm, immtype>;
|
|
|
|
|
|
|
|
def : InstAlias<asm # "\t$Zt, $Pg, [$Rn]",
|
|
|
|
(!cast<Instruction>(NAME) VecList:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0), 1>;
|
|
|
|
}
|
|
|
|
|
2018-05-17 17:05:41 +08:00
|
|
|
class sve_mem_est_ss<bits<2> sz, bits<2> nregs, RegisterOperand VecList,
|
|
|
|
string asm, RegisterOperand gprty>
|
|
|
|
: I<(outs), (ins VecList:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, gprty:$Rm),
|
|
|
|
asm, "\t$Zt, $Pg, [$Rn, $Rm]",
|
|
|
|
"",
|
|
|
|
[]>, Sched<[]> {
|
|
|
|
bits<3> Pg;
|
|
|
|
bits<5> Rm;
|
|
|
|
bits<5> Rn;
|
|
|
|
bits<5> Zt;
|
|
|
|
let Inst{31-25} = 0b1110010;
|
|
|
|
let Inst{24-23} = sz;
|
|
|
|
let Inst{22-21} = nregs;
|
|
|
|
let Inst{20-16} = Rm;
|
|
|
|
let Inst{15-13} = 0b011;
|
|
|
|
let Inst{12-10} = Pg;
|
|
|
|
let Inst{9-5} = Rn;
|
|
|
|
let Inst{4-0} = Zt;
|
|
|
|
|
|
|
|
let mayStore = 1;
|
|
|
|
}
|
|
|
|
|
2018-05-01 21:36:03 +08:00
|
|
|
class sve_mem_cst_ss_base<bits<4> dtype, string asm,
|
|
|
|
RegisterOperand listty, RegisterOperand gprty>
|
|
|
|
: I<(outs), (ins listty:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, gprty:$Rm),
|
|
|
|
asm, "\t$Zt, $Pg, [$Rn, $Rm]",
|
|
|
|
"",
|
|
|
|
[]>, Sched<[]> {
|
|
|
|
bits<3> Pg;
|
|
|
|
bits<5> Rm;
|
|
|
|
bits<5> Rn;
|
|
|
|
bits<5> Zt;
|
|
|
|
let Inst{31-25} = 0b1110010;
|
|
|
|
let Inst{24-21} = dtype;
|
|
|
|
let Inst{20-16} = Rm;
|
|
|
|
let Inst{15-13} = 0b010;
|
|
|
|
let Inst{12-10} = Pg;
|
|
|
|
let Inst{9-5} = Rn;
|
|
|
|
let Inst{4-0} = Zt;
|
|
|
|
|
|
|
|
let mayStore = 1;
|
|
|
|
}
|
|
|
|
|
|
|
|
multiclass sve_mem_cst_ss<bits<4> dtype, string asm,
|
|
|
|
RegisterOperand listty, ZPRRegOp zprty,
|
|
|
|
RegisterOperand gprty> {
|
|
|
|
def NAME : sve_mem_cst_ss_base<dtype, asm, listty, gprty>;
|
|
|
|
|
|
|
|
def : InstAlias<asm # "\t$Zt, $Pg, [$Rn, $Rm]",
|
|
|
|
(!cast<Instruction>(NAME) zprty:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, gprty:$Rm), 0>;
|
|
|
|
}
|
|
|
|
|
2018-05-02 19:48:49 +08:00
|
|
|
class sve_mem_cstnt_si<bits<2> msz, string asm, RegisterOperand VecList>
|
|
|
|
: I<(outs), (ins VecList:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, simm4s1:$imm4),
|
|
|
|
asm, "\t$Zt, $Pg, [$Rn, $imm4, mul vl]",
|
|
|
|
"",
|
|
|
|
[]>, Sched<[]> {
|
|
|
|
bits<3> Pg;
|
|
|
|
bits<5> Rn;
|
|
|
|
bits<5> Zt;
|
|
|
|
bits<4> imm4;
|
|
|
|
let Inst{31-25} = 0b1110010;
|
|
|
|
let Inst{24-23} = msz;
|
|
|
|
let Inst{22-20} = 0b001;
|
|
|
|
let Inst{19-16} = imm4;
|
|
|
|
let Inst{15-13} = 0b111;
|
|
|
|
let Inst{12-10} = Pg;
|
|
|
|
let Inst{9-5} = Rn;
|
|
|
|
let Inst{4-0} = Zt;
|
|
|
|
|
|
|
|
let mayStore = 1;
|
|
|
|
}
|
|
|
|
|
|
|
|
multiclass sve_mem_cstnt_si<bits<2> msz, string asm, RegisterOperand listty,
|
|
|
|
ZPRRegOp zprty> {
|
|
|
|
def NAME : sve_mem_cstnt_si<msz, asm, listty>;
|
|
|
|
|
|
|
|
def : InstAlias<asm # "\t$Zt, $Pg, [$Rn]",
|
|
|
|
(!cast<Instruction>(NAME) zprty:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0), 0>;
|
|
|
|
def : InstAlias<asm # "\t$Zt, $Pg, [$Rn, $imm4, mul vl]",
|
|
|
|
(!cast<Instruction>(NAME) zprty:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, simm4s1:$imm4), 0>;
|
|
|
|
def : InstAlias<asm # "\t$Zt, $Pg, [$Rn]",
|
|
|
|
(!cast<Instruction>(NAME) listty:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0), 1>;
|
|
|
|
}
|
|
|
|
|
|
|
|
class sve_mem_cstnt_ss_base<bits<2> msz, string asm, RegisterOperand listty,
|
|
|
|
RegisterOperand gprty>
|
|
|
|
: I<(outs), (ins listty:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, gprty:$Rm),
|
|
|
|
asm, "\t$Zt, $Pg, [$Rn, $Rm]",
|
|
|
|
"",
|
|
|
|
[]>, Sched<[]> {
|
|
|
|
bits<3> Pg;
|
|
|
|
bits<5> Rm;
|
|
|
|
bits<5> Rn;
|
|
|
|
bits<5> Zt;
|
|
|
|
let Inst{31-25} = 0b1110010;
|
|
|
|
let Inst{24-23} = msz;
|
|
|
|
let Inst{22-21} = 0b00;
|
|
|
|
let Inst{20-16} = Rm;
|
|
|
|
let Inst{15-13} = 0b011;
|
|
|
|
let Inst{12-10} = Pg;
|
|
|
|
let Inst{9-5} = Rn;
|
|
|
|
let Inst{4-0} = Zt;
|
|
|
|
|
|
|
|
let mayStore = 1;
|
|
|
|
}
|
|
|
|
|
|
|
|
multiclass sve_mem_cstnt_ss<bits<2> msz, string asm, RegisterOperand listty,
|
|
|
|
ZPRRegOp zprty, RegisterOperand gprty> {
|
|
|
|
def NAME : sve_mem_cstnt_ss_base<msz, asm, listty, gprty>;
|
|
|
|
|
|
|
|
def : InstAlias<asm # "\t$Zt, $Pg, [$Rn, $Rm]",
|
|
|
|
(!cast<Instruction>(NAME) zprty:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, gprty:$Rm), 0>;
|
|
|
|
}
|
|
|
|
|
2018-05-02 21:00:30 +08:00
|
|
|
class sve_mem_sst_sv<bits<3> opc, bit xs, bit scaled, string asm,
|
|
|
|
RegisterOperand VecList, RegisterOperand zprext>
|
|
|
|
: I<(outs), (ins VecList:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, zprext:$Zm),
|
|
|
|
asm, "\t$Zt, $Pg, [$Rn, $Zm]",
|
|
|
|
"",
|
|
|
|
[]>, Sched<[]> {
|
|
|
|
bits<3> Pg;
|
|
|
|
bits<5> Rn;
|
|
|
|
bits<5> Zm;
|
|
|
|
bits<5> Zt;
|
|
|
|
let Inst{31-25} = 0b1110010;
|
|
|
|
let Inst{24-22} = opc;
|
|
|
|
let Inst{21} = scaled;
|
|
|
|
let Inst{20-16} = Zm;
|
|
|
|
let Inst{15} = 0b1;
|
|
|
|
let Inst{14} = xs;
|
|
|
|
let Inst{13} = 0;
|
|
|
|
let Inst{12-10} = Pg;
|
|
|
|
let Inst{9-5} = Rn;
|
|
|
|
let Inst{4-0} = Zt;
|
|
|
|
|
|
|
|
let mayStore = 1;
|
|
|
|
}
|
|
|
|
|
|
|
|
multiclass sve_mem_sst_sv_32_scaled<bits<3> opc, string asm,
|
|
|
|
RegisterOperand listty,
|
|
|
|
ZPRRegOp zprty,
|
|
|
|
RegisterOperand sxtw_opnd,
|
|
|
|
RegisterOperand uxtw_opnd > {
|
|
|
|
def _UXTW_SCALED : sve_mem_sst_sv<opc, 0, 1, asm, listty, uxtw_opnd>;
|
|
|
|
def _SXTW_SCALED : sve_mem_sst_sv<opc, 1, 1, asm, listty, sxtw_opnd>;
|
|
|
|
|
|
|
|
def : InstAlias<asm # "\t$Zt, $Pg, [$Rn, $Zm]",
|
|
|
|
(!cast<Instruction>(NAME # _UXTW_SCALED) zprty:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, uxtw_opnd:$Zm), 0>;
|
|
|
|
def : InstAlias<asm # "\t$Zt, $Pg, [$Rn, $Zm]",
|
|
|
|
(!cast<Instruction>(NAME # _SXTW_SCALED) zprty:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, sxtw_opnd:$Zm), 0>;
|
|
|
|
}
|
|
|
|
|
|
|
|
multiclass sve_mem_sst_sv_32_unscaled<bits<3> opc, string asm,
|
|
|
|
RegisterOperand listty,
|
|
|
|
ZPRRegOp zprty,
|
|
|
|
RegisterOperand sxtw_opnd,
|
|
|
|
RegisterOperand uxtw_opnd> {
|
|
|
|
def _UXTW : sve_mem_sst_sv<opc, 0, 0, asm, listty, uxtw_opnd>;
|
|
|
|
def _SXTW : sve_mem_sst_sv<opc, 1, 0, asm, listty, sxtw_opnd>;
|
|
|
|
|
|
|
|
def : InstAlias<asm # "\t$Zt, $Pg, [$Rn, $Zm]",
|
|
|
|
(!cast<Instruction>(NAME # _UXTW) zprty:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, uxtw_opnd:$Zm), 0>;
|
|
|
|
def : InstAlias<asm # "\t$Zt, $Pg, [$Rn, $Zm]",
|
|
|
|
(!cast<Instruction>(NAME # _SXTW) zprty:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, sxtw_opnd:$Zm), 0>;
|
|
|
|
}
|
|
|
|
|
|
|
|
class sve_mem_sst_sv2<bits<2> msz, bit scaled, string asm,
|
|
|
|
RegisterOperand zprext>
|
|
|
|
: I<(outs), (ins Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, zprext:$Zm),
|
|
|
|
asm, "\t$Zt, $Pg, [$Rn, $Zm]",
|
|
|
|
"",
|
|
|
|
[]>, Sched<[]> {
|
|
|
|
bits<3> Pg;
|
|
|
|
bits<5> Rn;
|
|
|
|
bits<5> Zm;
|
|
|
|
bits<5> Zt;
|
|
|
|
let Inst{31-25} = 0b1110010;
|
|
|
|
let Inst{24-23} = msz;
|
|
|
|
let Inst{22} = 0b0;
|
|
|
|
let Inst{21} = scaled;
|
|
|
|
let Inst{20-16} = Zm;
|
|
|
|
let Inst{15-13} = 0b101;
|
|
|
|
let Inst{12-10} = Pg;
|
|
|
|
let Inst{9-5} = Rn;
|
|
|
|
let Inst{4-0} = Zt;
|
|
|
|
|
|
|
|
let mayStore = 1;
|
|
|
|
}
|
|
|
|
|
|
|
|
multiclass sve_mem_sst_sv_64_scaled<bits<2> msz, string asm,
|
|
|
|
RegisterOperand zprext> {
|
|
|
|
def "" : sve_mem_sst_sv2<msz, 1, asm, zprext>;
|
|
|
|
|
|
|
|
def : InstAlias<asm # "\t$Zt, $Pg, [$Rn, $Zm]",
|
|
|
|
(!cast<Instruction>(NAME) ZPR64:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, zprext:$Zm), 0>;
|
|
|
|
|
|
|
|
}
|
|
|
|
|
|
|
|
multiclass sve_mem_sst_sv_64_unscaled<bits<2> msz, string asm> {
|
|
|
|
def "" : sve_mem_sst_sv2<msz, 0, asm, ZPR64ExtLSL8>;
|
|
|
|
|
|
|
|
def : InstAlias<asm # "\t$Zt, $Pg, [$Rn, $Zm]",
|
|
|
|
(!cast<Instruction>(NAME) ZPR64:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, ZPR64ExtLSL8:$Zm), 0>;
|
|
|
|
}
|
|
|
|
|
|
|
|
class sve_mem_sst_vi<bits<3> opc, string asm, ZPRRegOp zprty,
|
|
|
|
RegisterOperand VecList, Operand imm_ty>
|
|
|
|
: I<(outs), (ins VecList:$Zt, PPR3bAny:$Pg, zprty:$Zn, imm_ty:$imm5),
|
|
|
|
asm, "\t$Zt, $Pg, [$Zn, $imm5]",
|
|
|
|
"",
|
|
|
|
[]>, Sched<[]> {
|
|
|
|
bits<3> Pg;
|
|
|
|
bits<5> imm5;
|
|
|
|
bits<5> Zn;
|
|
|
|
bits<5> Zt;
|
|
|
|
let Inst{31-25} = 0b1110010;
|
|
|
|
let Inst{24-23} = opc{2-1};
|
|
|
|
let Inst{22} = 0b1;
|
|
|
|
let Inst{21} = opc{0};
|
|
|
|
let Inst{20-16} = imm5;
|
|
|
|
let Inst{15-13} = 0b101;
|
|
|
|
let Inst{12-10} = Pg;
|
|
|
|
let Inst{9-5} = Zn;
|
|
|
|
let Inst{4-0} = Zt;
|
|
|
|
|
|
|
|
let mayStore = 1;
|
|
|
|
}
|
|
|
|
|
|
|
|
multiclass sve_mem_sst_vi_ptrs<bits<3> opc, string asm, RegisterOperand listty,
|
|
|
|
ZPRRegOp zprty, Operand imm_ty> {
|
|
|
|
def _IMM : sve_mem_sst_vi<opc, asm, zprty, listty, imm_ty>;
|
|
|
|
|
|
|
|
def : InstAlias<asm # "\t$Zt, $Pg, [$Zn]",
|
|
|
|
(!cast<Instruction>(NAME # _IMM) zprty:$Zt, PPR3bAny:$Pg, zprty:$Zn, 0), 0>;
|
|
|
|
def : InstAlias<asm # "\t$Zt, $Pg, [$Zn, $imm5]",
|
|
|
|
(!cast<Instruction>(NAME # _IMM) zprty:$Zt, PPR3bAny:$Pg, zprty:$Zn, imm_ty:$imm5), 0>;
|
|
|
|
def : InstAlias<asm # "\t$Zt, $Pg, [$Zn]",
|
|
|
|
(!cast<Instruction>(NAME # _IMM) listty:$Zt, PPR3bAny:$Pg, zprty:$Zn, 0), 1>;
|
|
|
|
}
|
|
|
|
|
2018-05-02 21:32:39 +08:00
|
|
|
class sve_mem_z_spill<string asm>
|
|
|
|
: I<(outs), (ins ZPRAny:$Zt, GPR64sp:$Rn, simm9:$imm9),
|
|
|
|
asm, "\t$Zt, [$Rn, $imm9, mul vl]",
|
|
|
|
"",
|
|
|
|
[]>, Sched<[]> {
|
|
|
|
bits<5> Rn;
|
|
|
|
bits<5> Zt;
|
|
|
|
bits<9> imm9;
|
|
|
|
let Inst{31-22} = 0b1110010110;
|
|
|
|
let Inst{21-16} = imm9{8-3};
|
|
|
|
let Inst{15-13} = 0b010;
|
|
|
|
let Inst{12-10} = imm9{2-0};
|
|
|
|
let Inst{9-5} = Rn;
|
|
|
|
let Inst{4-0} = Zt;
|
|
|
|
|
|
|
|
let mayStore = 1;
|
|
|
|
}
|
|
|
|
|
|
|
|
multiclass sve_mem_z_spill<string asm> {
|
|
|
|
def NAME : sve_mem_z_spill<asm>;
|
|
|
|
|
|
|
|
def : InstAlias<asm # "\t$Zt, [$Rn]",
|
|
|
|
(!cast<Instruction>(NAME) ZPRAny:$Zt, GPR64sp:$Rn, 0), 1>;
|
|
|
|
}
|
|
|
|
|
|
|
|
class sve_mem_p_spill<string asm>
|
|
|
|
: I<(outs), (ins PPRAny:$Pt, GPR64sp:$Rn, simm9:$imm9),
|
|
|
|
asm, "\t$Pt, [$Rn, $imm9, mul vl]",
|
|
|
|
"",
|
|
|
|
[]>, Sched<[]> {
|
|
|
|
bits<4> Pt;
|
|
|
|
bits<5> Rn;
|
|
|
|
bits<9> imm9;
|
|
|
|
let Inst{31-22} = 0b1110010110;
|
|
|
|
let Inst{21-16} = imm9{8-3};
|
|
|
|
let Inst{15-13} = 0b000;
|
|
|
|
let Inst{12-10} = imm9{2-0};
|
|
|
|
let Inst{9-5} = Rn;
|
|
|
|
let Inst{4} = 0b0;
|
|
|
|
let Inst{3-0} = Pt;
|
|
|
|
|
|
|
|
let mayStore = 1;
|
|
|
|
}
|
|
|
|
|
|
|
|
multiclass sve_mem_p_spill<string asm> {
|
|
|
|
def NAME : sve_mem_p_spill<asm>;
|
|
|
|
|
|
|
|
def : InstAlias<asm # "\t$Pt, [$Rn]",
|
|
|
|
(!cast<Instruction>(NAME) PPRAny:$Pt, GPR64sp:$Rn, 0), 1>;
|
|
|
|
}
|
|
|
|
|
[AArch64][SVE] Asm: Support for contiguous ST1 (scalar+imm) store instructions.
Summary:
Added instructions for contiguous stores, ST1, with scalar+imm addressing
modes and corresponding tests. The patch also adds parsing of
'mul vl' as needed for the VL-scaled immediate.
This is patch [6/6] in a series to add assembler/disassembler support for
SVE's contiguous ST1 (scalar+imm) instructions.
Reviewers: fhahn, rengolin, javed.absar, huntergr, SjoerdMeijer, t.p.northover, echristo, evandro
Reviewed By: rengolin
Subscribers: tschuett, llvm-commits, kristof.beyls
Differential Revision: https://reviews.llvm.org/D45432
llvm-svn: 330014
2018-04-13 20:56:14 +08:00
|
|
|
//===----------------------------------------------------------------------===//
|
2017-12-20 19:02:42 +08:00
|
|
|
// SVE Permute - Predicates Group
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
|
|
|
|
class sve_int_perm_bin_perm_pp<bits<3> opc, bits<2> sz8_64, string asm,
|
|
|
|
PPRRegOp pprty>
|
|
|
|
: I<(outs pprty:$Pd), (ins pprty:$Pn, pprty:$Pm),
|
|
|
|
asm, "\t$Pd, $Pn, $Pm",
|
|
|
|
"",
|
|
|
|
[]>, Sched<[]> {
|
|
|
|
bits<4> Pd;
|
|
|
|
bits<4> Pm;
|
|
|
|
bits<4> Pn;
|
|
|
|
let Inst{31-24} = 0b00000101;
|
|
|
|
let Inst{23-22} = sz8_64;
|
|
|
|
let Inst{21-20} = 0b10;
|
|
|
|
let Inst{19-16} = Pm;
|
|
|
|
let Inst{15-13} = 0b010;
|
|
|
|
let Inst{12-10} = opc;
|
|
|
|
let Inst{9} = 0b0;
|
|
|
|
let Inst{8-5} = Pn;
|
|
|
|
let Inst{4} = 0b0;
|
|
|
|
let Inst{3-0} = Pd;
|
|
|
|
}
|
|
|
|
|
|
|
|
multiclass sve_int_perm_bin_perm_pp<bits<3> opc, string asm> {
|
|
|
|
def _B : sve_int_perm_bin_perm_pp<opc, 0b00, asm, PPR8>;
|
|
|
|
def _H : sve_int_perm_bin_perm_pp<opc, 0b01, asm, PPR16>;
|
|
|
|
def _S : sve_int_perm_bin_perm_pp<opc, 0b10, asm, PPR32>;
|
|
|
|
def _D : sve_int_perm_bin_perm_pp<opc, 0b11, asm, PPR64>;
|
[AArch64][SVE] Asm: Add support for RDVL/ADDVL/ADDPL instructions
Reviewers: fhahn, rengolin, t.p.northover, echristo, olista01, SjoerdMeijer
Reviewed By: SjoerdMeijer
Subscribers: SjoerdMeijer, aemerson, javed.absar, tschuett, kristof.beyls, llvm-commits
Differential Revision: https://reviews.llvm.org/D41900
llvm-svn: 322951
2018-01-19 23:22:00 +08:00
|
|
|
}
|
2018-04-13 22:41:36 +08:00
|
|
|
|
2018-07-13 17:25:43 +08:00
|
|
|
class sve_int_perm_punpk<bit opc, string asm>
|
|
|
|
: I<(outs PPR16:$Pd), (ins PPR8:$Pn),
|
|
|
|
asm, "\t$Pd, $Pn",
|
|
|
|
"",
|
|
|
|
[]>, Sched<[]> {
|
|
|
|
bits<4> Pd;
|
|
|
|
bits<4> Pn;
|
|
|
|
let Inst{31-17} = 0b000001010011000;
|
|
|
|
let Inst{16} = opc;
|
|
|
|
let Inst{15-9} = 0b0100000;
|
|
|
|
let Inst{8-5} = Pn;
|
|
|
|
let Inst{4} = 0b0;
|
|
|
|
let Inst{3-0} = Pd;
|
|
|
|
}
|
|
|
|
|
2018-07-04 20:58:46 +08:00
|
|
|
class sve_int_rdffr_pred<bit s, string asm>
|
|
|
|
: I<(outs PPR8:$Pd), (ins PPRAny:$Pg),
|
|
|
|
asm, "\t$Pd, $Pg/z",
|
|
|
|
"",
|
|
|
|
[]>, Sched<[]> {
|
|
|
|
bits<4> Pd;
|
|
|
|
bits<4> Pg;
|
|
|
|
let Inst{31-23} = 0b001001010;
|
|
|
|
let Inst{22} = s;
|
|
|
|
let Inst{21-9} = 0b0110001111000;
|
|
|
|
let Inst{8-5} = Pg;
|
|
|
|
let Inst{4} = 0;
|
|
|
|
let Inst{3-0} = Pd;
|
|
|
|
|
|
|
|
let Defs = !if(!eq (s, 1), [NZCV], []);
|
|
|
|
let Uses = [FFR];
|
|
|
|
}
|
|
|
|
|
|
|
|
class sve_int_rdffr_unpred<string asm> : I<
|
|
|
|
(outs PPR8:$Pd), (ins),
|
|
|
|
asm, "\t$Pd",
|
|
|
|
"",
|
|
|
|
[]>, Sched<[]> {
|
|
|
|
bits<4> Pd;
|
|
|
|
let Inst{31-4} = 0b0010010100011001111100000000;
|
|
|
|
let Inst{3-0} = Pd;
|
|
|
|
|
|
|
|
let Uses = [FFR];
|
|
|
|
}
|
|
|
|
|
|
|
|
class sve_int_wrffr<string asm>
|
|
|
|
: I<(outs), (ins PPR8:$Pn),
|
|
|
|
asm, "\t$Pn",
|
|
|
|
"",
|
|
|
|
[]>, Sched<[]> {
|
|
|
|
bits<4> Pn;
|
|
|
|
let Inst{31-9} = 0b00100101001010001001000;
|
|
|
|
let Inst{8-5} = Pn;
|
|
|
|
let Inst{4-0} = 0b00000;
|
|
|
|
|
|
|
|
let hasSideEffects = 1;
|
|
|
|
let Defs = [FFR];
|
|
|
|
}
|
|
|
|
|
|
|
|
class sve_int_setffr<string asm>
|
|
|
|
: I<(outs), (ins),
|
|
|
|
asm, "",
|
|
|
|
"",
|
|
|
|
[]>, Sched<[]> {
|
|
|
|
let Inst{31-0} = 0b00100101001011001001000000000000;
|
|
|
|
|
|
|
|
let hasSideEffects = 1;
|
|
|
|
let Defs = [FFR];
|
|
|
|
}
|
2018-06-16 00:39:46 +08:00
|
|
|
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
// SVE Permute Vector - Predicated Group
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
|
[AArch64][SVE] Asm: Support for LAST(A|B) and CLAST(A|B) instructions.
The LASTB and LASTA instructions extract the last active element,
or element after the last active, from the source vector.
The added variants are:
Scalar:
last(a|b) w0, p0, z0.b
last(a|b) w0, p0, z0.h
last(a|b) w0, p0, z0.s
last(a|b) x0, p0, z0.d
SIMD & FP Scalar:
last(a|b) b0, p0, z0.b
last(a|b) h0, p0, z0.h
last(a|b) s0, p0, z0.s
last(a|b) d0, p0, z0.d
The CLASTB and CLASTA conditionally extract the last or element after
the last active element from the source vector.
The added variants are:
Scalar:
clast(a|b) w0, p0, w0, z0.b
clast(a|b) w0, p0, w0, z0.h
clast(a|b) w0, p0, w0, z0.s
clast(a|b) x0, p0, x0, z0.d
SIMD & FP Scalar:
clast(a|b) b0, p0, b0, z0.b
clast(a|b) h0, p0, h0, z0.h
clast(a|b) s0, p0, s0, z0.s
clast(a|b) d0, p0, d0, z0.d
Vector:
clast(a|b) z0.b, p0, z0.b, z1.b
clast(a|b) z0.h, p0, z0.h, z1.h
clast(a|b) z0.s, p0, z0.s, z1.s
clast(a|b) z0.d, p0, z0.d, z1.d
Please refer to the architecture specification for more details on
the semantics of the added instructions.
llvm-svn: 336783
2018-07-11 18:08:00 +08:00
|
|
|
class sve_int_perm_clast_rz<bits<2> sz8_64, bit ab, string asm,
|
|
|
|
ZPRRegOp zprty, RegisterClass rt>
|
|
|
|
: I<(outs rt:$Rdn), (ins PPR3bAny:$Pg, rt:$_Rdn, zprty:$Zm),
|
|
|
|
asm, "\t$Rdn, $Pg, $_Rdn, $Zm",
|
|
|
|
"",
|
|
|
|
[]>, Sched<[]> {
|
|
|
|
bits<3> Pg;
|
|
|
|
bits<5> Rdn;
|
|
|
|
bits<5> Zm;
|
|
|
|
let Inst{31-24} = 0b00000101;
|
|
|
|
let Inst{23-22} = sz8_64;
|
|
|
|
let Inst{21-17} = 0b11000;
|
|
|
|
let Inst{16} = ab;
|
|
|
|
let Inst{15-13} = 0b101;
|
|
|
|
let Inst{12-10} = Pg;
|
|
|
|
let Inst{9-5} = Zm;
|
|
|
|
let Inst{4-0} = Rdn;
|
|
|
|
|
|
|
|
let Constraints = "$Rdn = $_Rdn";
|
|
|
|
}
|
|
|
|
|
|
|
|
multiclass sve_int_perm_clast_rz<bit ab, string asm> {
|
|
|
|
def _B : sve_int_perm_clast_rz<0b00, ab, asm, ZPR8, GPR32>;
|
|
|
|
def _H : sve_int_perm_clast_rz<0b01, ab, asm, ZPR16, GPR32>;
|
|
|
|
def _S : sve_int_perm_clast_rz<0b10, ab, asm, ZPR32, GPR32>;
|
|
|
|
def _D : sve_int_perm_clast_rz<0b11, ab, asm, ZPR64, GPR64>;
|
|
|
|
}
|
|
|
|
|
|
|
|
class sve_int_perm_clast_vz<bits<2> sz8_64, bit ab, string asm,
|
|
|
|
ZPRRegOp zprty, RegisterClass rt>
|
|
|
|
: I<(outs rt:$Vdn), (ins PPR3bAny:$Pg, rt:$_Vdn, zprty:$Zm),
|
|
|
|
asm, "\t$Vdn, $Pg, $_Vdn, $Zm",
|
|
|
|
"",
|
|
|
|
[]>, Sched<[]> {
|
|
|
|
bits<3> Pg;
|
|
|
|
bits<5> Vdn;
|
|
|
|
bits<5> Zm;
|
|
|
|
let Inst{31-24} = 0b00000101;
|
|
|
|
let Inst{23-22} = sz8_64;
|
|
|
|
let Inst{21-17} = 0b10101;
|
|
|
|
let Inst{16} = ab;
|
|
|
|
let Inst{15-13} = 0b100;
|
|
|
|
let Inst{12-10} = Pg;
|
|
|
|
let Inst{9-5} = Zm;
|
|
|
|
let Inst{4-0} = Vdn;
|
|
|
|
|
|
|
|
let Constraints = "$Vdn = $_Vdn";
|
|
|
|
}
|
|
|
|
|
|
|
|
multiclass sve_int_perm_clast_vz<bit ab, string asm> {
|
|
|
|
def _B : sve_int_perm_clast_vz<0b00, ab, asm, ZPR8, FPR8>;
|
|
|
|
def _H : sve_int_perm_clast_vz<0b01, ab, asm, ZPR16, FPR16>;
|
|
|
|
def _S : sve_int_perm_clast_vz<0b10, ab, asm, ZPR32, FPR32>;
|
|
|
|
def _D : sve_int_perm_clast_vz<0b11, ab, asm, ZPR64, FPR64>;
|
|
|
|
}
|
|
|
|
|
|
|
|
class sve_int_perm_clast_zz<bits<2> sz8_64, bit ab, string asm,
|
|
|
|
ZPRRegOp zprty>
|
|
|
|
: I<(outs zprty:$Zdn), (ins PPR3bAny:$Pg, zprty:$_Zdn, zprty:$Zm),
|
|
|
|
asm, "\t$Zdn, $Pg, $_Zdn, $Zm",
|
|
|
|
"",
|
|
|
|
[]>, Sched<[]> {
|
|
|
|
bits<3> Pg;
|
|
|
|
bits<5> Zdn;
|
|
|
|
bits<5> Zm;
|
|
|
|
let Inst{31-24} = 0b00000101;
|
|
|
|
let Inst{23-22} = sz8_64;
|
|
|
|
let Inst{21-17} = 0b10100;
|
|
|
|
let Inst{16} = ab;
|
|
|
|
let Inst{15-13} = 0b100;
|
|
|
|
let Inst{12-10} = Pg;
|
|
|
|
let Inst{9-5} = Zm;
|
|
|
|
let Inst{4-0} = Zdn;
|
|
|
|
|
|
|
|
let Constraints = "$Zdn = $_Zdn";
|
|
|
|
}
|
|
|
|
|
|
|
|
multiclass sve_int_perm_clast_zz<bit ab, string asm> {
|
|
|
|
def _B : sve_int_perm_clast_zz<0b00, ab, asm, ZPR8>;
|
|
|
|
def _H : sve_int_perm_clast_zz<0b01, ab, asm, ZPR16>;
|
|
|
|
def _S : sve_int_perm_clast_zz<0b10, ab, asm, ZPR32>;
|
|
|
|
def _D : sve_int_perm_clast_zz<0b11, ab, asm, ZPR64>;
|
|
|
|
}
|
|
|
|
|
|
|
|
class sve_int_perm_last_r<bits<2> sz8_64, bit ab, string asm,
|
|
|
|
ZPRRegOp zprty, RegisterClass resultRegType>
|
|
|
|
: I<(outs resultRegType:$Rd), (ins PPR3bAny:$Pg, zprty:$Zn),
|
|
|
|
asm, "\t$Rd, $Pg, $Zn",
|
|
|
|
"",
|
|
|
|
[]>, Sched<[]> {
|
|
|
|
bits<3> Pg;
|
|
|
|
bits<5> Rd;
|
|
|
|
bits<5> Zn;
|
|
|
|
let Inst{31-24} = 0b00000101;
|
|
|
|
let Inst{23-22} = sz8_64;
|
|
|
|
let Inst{21-17} = 0b10000;
|
|
|
|
let Inst{16} = ab;
|
|
|
|
let Inst{15-13} = 0b101;
|
|
|
|
let Inst{12-10} = Pg;
|
|
|
|
let Inst{9-5} = Zn;
|
|
|
|
let Inst{4-0} = Rd;
|
|
|
|
}
|
|
|
|
|
|
|
|
multiclass sve_int_perm_last_r<bit ab, string asm> {
|
|
|
|
def _B : sve_int_perm_last_r<0b00, ab, asm, ZPR8, GPR32>;
|
|
|
|
def _H : sve_int_perm_last_r<0b01, ab, asm, ZPR16, GPR32>;
|
|
|
|
def _S : sve_int_perm_last_r<0b10, ab, asm, ZPR32, GPR32>;
|
|
|
|
def _D : sve_int_perm_last_r<0b11, ab, asm, ZPR64, GPR64>;
|
|
|
|
}
|
|
|
|
|
|
|
|
class sve_int_perm_last_v<bits<2> sz8_64, bit ab, string asm,
|
|
|
|
ZPRRegOp zprty, RegisterClass dstRegtype>
|
|
|
|
: I<(outs dstRegtype:$Vd), (ins PPR3bAny:$Pg, zprty:$Zn),
|
|
|
|
asm, "\t$Vd, $Pg, $Zn",
|
|
|
|
"",
|
|
|
|
[]>, Sched<[]> {
|
|
|
|
bits<3> Pg;
|
|
|
|
bits<5> Vd;
|
|
|
|
bits<5> Zn;
|
|
|
|
let Inst{31-24} = 0b00000101;
|
|
|
|
let Inst{23-22} = sz8_64;
|
|
|
|
let Inst{21-17} = 0b10001;
|
|
|
|
let Inst{16} = ab;
|
|
|
|
let Inst{15-13} = 0b100;
|
|
|
|
let Inst{12-10} = Pg;
|
|
|
|
let Inst{9-5} = Zn;
|
|
|
|
let Inst{4-0} = Vd;
|
|
|
|
}
|
|
|
|
|
|
|
|
multiclass sve_int_perm_last_v<bit ab, string asm> {
|
|
|
|
def _B : sve_int_perm_last_v<0b00, ab, asm, ZPR8, FPR8>;
|
|
|
|
def _H : sve_int_perm_last_v<0b01, ab, asm, ZPR16, FPR16>;
|
|
|
|
def _S : sve_int_perm_last_v<0b10, ab, asm, ZPR32, FPR32>;
|
|
|
|
def _D : sve_int_perm_last_v<0b11, ab, asm, ZPR64, FPR64>;
|
|
|
|
}
|
|
|
|
|
2018-07-17 16:52:45 +08:00
|
|
|
class sve_int_perm_splice<bits<2> sz8_64, string asm, ZPRRegOp zprty>
|
|
|
|
: I<(outs zprty:$Zdn), (ins PPR3bAny:$Pg, zprty:$_Zdn, zprty:$Zm),
|
|
|
|
asm, "\t$Zdn, $Pg, $_Zdn, $Zm",
|
|
|
|
"",
|
|
|
|
[]>, Sched<[]> {
|
|
|
|
bits<3> Pg;
|
|
|
|
bits<5> Zdn;
|
|
|
|
bits<5> Zm;
|
|
|
|
let Inst{31-24} = 0b00000101;
|
|
|
|
let Inst{23-22} = sz8_64;
|
|
|
|
let Inst{21-13} = 0b101100100;
|
|
|
|
let Inst{12-10} = Pg;
|
|
|
|
let Inst{9-5} = Zm;
|
|
|
|
let Inst{4-0} = Zdn;
|
|
|
|
|
|
|
|
let Constraints = "$Zdn = $_Zdn";
|
|
|
|
}
|
|
|
|
|
|
|
|
multiclass sve_int_perm_splice<string asm> {
|
|
|
|
def _B : sve_int_perm_splice<0b00, asm, ZPR8>;
|
|
|
|
def _H : sve_int_perm_splice<0b01, asm, ZPR16>;
|
|
|
|
def _S : sve_int_perm_splice<0b10, asm, ZPR32>;
|
|
|
|
def _D : sve_int_perm_splice<0b11, asm, ZPR64>;
|
|
|
|
}
|
|
|
|
|
2018-06-16 00:39:46 +08:00
|
|
|
class sve_int_perm_cpy_r<bits<2> sz8_64, string asm, ZPRRegOp zprty,
|
|
|
|
RegisterClass srcRegType>
|
|
|
|
: I<(outs zprty:$Zd), (ins zprty:$_Zd, PPR3bAny:$Pg, srcRegType:$Rn),
|
|
|
|
asm, "\t$Zd, $Pg/m, $Rn",
|
|
|
|
"",
|
|
|
|
[]>, Sched<[]> {
|
|
|
|
bits<3> Pg;
|
|
|
|
bits<5> Rn;
|
|
|
|
bits<5> Zd;
|
|
|
|
let Inst{31-24} = 0b00000101;
|
|
|
|
let Inst{23-22} = sz8_64;
|
|
|
|
let Inst{21-13} = 0b101000101;
|
|
|
|
let Inst{12-10} = Pg;
|
|
|
|
let Inst{9-5} = Rn;
|
|
|
|
let Inst{4-0} = Zd;
|
|
|
|
|
|
|
|
let Constraints = "$Zd = $_Zd";
|
|
|
|
}
|
|
|
|
|
|
|
|
multiclass sve_int_perm_cpy_r<string asm> {
|
|
|
|
def _B : sve_int_perm_cpy_r<0b00, asm, ZPR8, GPR32sp>;
|
|
|
|
def _H : sve_int_perm_cpy_r<0b01, asm, ZPR16, GPR32sp>;
|
|
|
|
def _S : sve_int_perm_cpy_r<0b10, asm, ZPR32, GPR32sp>;
|
|
|
|
def _D : sve_int_perm_cpy_r<0b11, asm, ZPR64, GPR64sp>;
|
|
|
|
|
|
|
|
def : InstAlias<"mov $Zd, $Pg/m, $Rn",
|
|
|
|
(!cast<Instruction>(NAME # _B) ZPR8:$Zd, PPR3bAny:$Pg, GPR32sp:$Rn), 1>;
|
|
|
|
def : InstAlias<"mov $Zd, $Pg/m, $Rn",
|
|
|
|
(!cast<Instruction>(NAME # _H) ZPR16:$Zd, PPR3bAny:$Pg, GPR32sp:$Rn), 1>;
|
|
|
|
def : InstAlias<"mov $Zd, $Pg/m, $Rn",
|
|
|
|
(!cast<Instruction>(NAME # _S) ZPR32:$Zd, PPR3bAny:$Pg, GPR32sp:$Rn), 1>;
|
|
|
|
def : InstAlias<"mov $Zd, $Pg/m, $Rn",
|
|
|
|
(!cast<Instruction>(NAME # _D) ZPR64:$Zd, PPR3bAny:$Pg, GPR64sp:$Rn), 1>;
|
|
|
|
}
|
|
|
|
|
|
|
|
class sve_int_perm_cpy_v<bits<2> sz8_64, string asm, ZPRRegOp zprty,
|
|
|
|
RegisterClass srcRegtype>
|
|
|
|
: I<(outs zprty:$Zd), (ins zprty:$_Zd, PPR3bAny:$Pg, srcRegtype:$Vn),
|
|
|
|
asm, "\t$Zd, $Pg/m, $Vn",
|
|
|
|
"",
|
|
|
|
[]>, Sched<[]> {
|
|
|
|
bits<3> Pg;
|
|
|
|
bits<5> Vn;
|
|
|
|
bits<5> Zd;
|
|
|
|
let Inst{31-24} = 0b00000101;
|
|
|
|
let Inst{23-22} = sz8_64;
|
|
|
|
let Inst{21-13} = 0b100000100;
|
|
|
|
let Inst{12-10} = Pg;
|
|
|
|
let Inst{9-5} = Vn;
|
|
|
|
let Inst{4-0} = Zd;
|
|
|
|
|
|
|
|
let Constraints = "$Zd = $_Zd";
|
|
|
|
}
|
|
|
|
|
|
|
|
multiclass sve_int_perm_cpy_v<string asm> {
|
|
|
|
def _B : sve_int_perm_cpy_v<0b00, asm, ZPR8, FPR8>;
|
|
|
|
def _H : sve_int_perm_cpy_v<0b01, asm, ZPR16, FPR16>;
|
|
|
|
def _S : sve_int_perm_cpy_v<0b10, asm, ZPR32, FPR32>;
|
|
|
|
def _D : sve_int_perm_cpy_v<0b11, asm, ZPR64, FPR64>;
|
|
|
|
|
|
|
|
def : InstAlias<"mov $Zd, $Pg/m, $Vn",
|
|
|
|
(!cast<Instruction>(NAME # _B) ZPR8:$Zd, PPR3bAny:$Pg, FPR8:$Vn), 1>;
|
|
|
|
def : InstAlias<"mov $Zd, $Pg/m, $Vn",
|
|
|
|
(!cast<Instruction>(NAME # _H) ZPR16:$Zd, PPR3bAny:$Pg, FPR16:$Vn), 1>;
|
|
|
|
def : InstAlias<"mov $Zd, $Pg/m, $Vn",
|
|
|
|
(!cast<Instruction>(NAME # _S) ZPR32:$Zd, PPR3bAny:$Pg, FPR32:$Vn), 1>;
|
|
|
|
def : InstAlias<"mov $Zd, $Pg/m, $Vn",
|
|
|
|
(!cast<Instruction>(NAME # _D) ZPR64:$Zd, PPR3bAny:$Pg, FPR64:$Vn), 1>;
|
|
|
|
}
|
|
|
|
|
2018-07-11 19:22:26 +08:00
|
|
|
class sve_int_perm_compact<bit sz, string asm, ZPRRegOp zprty>
|
|
|
|
: I<(outs zprty:$Zd), (ins PPR3bAny:$Pg, zprty:$Zn),
|
|
|
|
asm, "\t$Zd, $Pg, $Zn",
|
|
|
|
"",
|
|
|
|
[]>, Sched<[]> {
|
|
|
|
bits<3> Pg;
|
|
|
|
bits<5> Zd;
|
|
|
|
bits<5> Zn;
|
|
|
|
let Inst{31-23} = 0b000001011;
|
|
|
|
let Inst{22} = sz;
|
|
|
|
let Inst{21-13} = 0b100001100;
|
|
|
|
let Inst{12-10} = Pg;
|
|
|
|
let Inst{9-5} = Zn;
|
|
|
|
let Inst{4-0} = Zd;
|
|
|
|
}
|
|
|
|
|
|
|
|
multiclass sve_int_perm_compact<string asm> {
|
|
|
|
def _S : sve_int_perm_compact<0b0, asm, ZPR32>;
|
|
|
|
def _D : sve_int_perm_compact<0b1, asm, ZPR64>;
|
|
|
|
}
|
|
|
|
|
|
|
|
|
2018-04-13 22:41:36 +08:00
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
// SVE Memory - Contiguous Load Group
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
|
|
|
|
class sve_mem_cld_si_base<bits<4> dtype, bit nf, string asm,
|
|
|
|
RegisterOperand VecList>
|
2018-04-30 02:18:21 +08:00
|
|
|
: I<(outs VecList:$Zt), (ins PPR3bAny:$Pg, GPR64sp:$Rn, simm4s1:$imm4),
|
2018-04-13 22:41:36 +08:00
|
|
|
asm, "\t$Zt, $Pg/z, [$Rn, $imm4, mul vl]",
|
|
|
|
"",
|
|
|
|
[]>, Sched<[]> {
|
|
|
|
bits<3> Pg;
|
|
|
|
bits<5> Rn;
|
|
|
|
bits<5> Zt;
|
|
|
|
bits<4> imm4;
|
|
|
|
let Inst{31-25} = 0b1010010;
|
|
|
|
let Inst{24-21} = dtype;
|
|
|
|
let Inst{20} = nf;
|
|
|
|
let Inst{19-16} = imm4;
|
|
|
|
let Inst{15-13} = 0b101;
|
|
|
|
let Inst{12-10} = Pg;
|
|
|
|
let Inst{9-5} = Rn;
|
|
|
|
let Inst{4-0} = Zt;
|
|
|
|
|
|
|
|
let mayLoad = 1;
|
|
|
|
let Uses = !if(!eq(nf, 1), [FFR], []);
|
|
|
|
let Defs = !if(!eq(nf, 1), [FFR], []);
|
|
|
|
}
|
|
|
|
|
|
|
|
multiclass sve_mem_cld_si_base<bits<4> dtype, bit nf, string asm,
|
|
|
|
RegisterOperand listty, ZPRRegOp zprty> {
|
|
|
|
def _REAL : sve_mem_cld_si_base<dtype, nf, asm, listty>;
|
|
|
|
|
|
|
|
def : InstAlias<asm # "\t$Zt, $Pg/z, [$Rn]",
|
|
|
|
(!cast<Instruction>(NAME # _REAL) zprty:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0), 0>;
|
|
|
|
def : InstAlias<asm # "\t$Zt, $Pg/z, [$Rn, $imm4, mul vl]",
|
2018-04-30 02:18:21 +08:00
|
|
|
(!cast<Instruction>(NAME # _REAL) zprty:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, simm4s1:$imm4), 0>;
|
2018-04-13 22:41:36 +08:00
|
|
|
def : InstAlias<asm # "\t$Zt, $Pg/z, [$Rn]",
|
|
|
|
(!cast<Instruction>(NAME # _REAL) listty:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0), 1>;
|
|
|
|
}
|
|
|
|
|
|
|
|
multiclass sve_mem_cld_si<bits<4> dtype, string asm, RegisterOperand listty,
|
|
|
|
ZPRRegOp zprty>
|
2018-04-16 15:09:29 +08:00
|
|
|
: sve_mem_cld_si_base<dtype, 0, asm, listty, zprty>;
|
|
|
|
|
2018-05-02 19:48:49 +08:00
|
|
|
class sve_mem_cldnt_si_base<bits<2> msz, string asm, RegisterOperand VecList>
|
|
|
|
: I<(outs VecList:$Zt), (ins PPR3bAny:$Pg, GPR64sp:$Rn, simm4s1:$imm4),
|
|
|
|
asm, "\t$Zt, $Pg/z, [$Rn, $imm4, mul vl]",
|
|
|
|
"",
|
|
|
|
[]>, Sched<[]> {
|
|
|
|
bits<5> Zt;
|
|
|
|
bits<3> Pg;
|
|
|
|
bits<5> Rn;
|
|
|
|
bits<4> imm4;
|
|
|
|
let Inst{31-25} = 0b1010010;
|
|
|
|
let Inst{24-23} = msz;
|
|
|
|
let Inst{22-20} = 0b000;
|
|
|
|
let Inst{19-16} = imm4;
|
|
|
|
let Inst{15-13} = 0b111;
|
|
|
|
let Inst{12-10} = Pg;
|
|
|
|
let Inst{9-5} = Rn;
|
|
|
|
let Inst{4-0} = Zt;
|
|
|
|
|
|
|
|
let mayLoad = 1;
|
|
|
|
}
|
|
|
|
|
|
|
|
multiclass sve_mem_cldnt_si<bits<2> msz, string asm, RegisterOperand listty,
|
|
|
|
ZPRRegOp zprty> {
|
|
|
|
def NAME : sve_mem_cldnt_si_base<msz, asm, listty>;
|
|
|
|
|
|
|
|
def : InstAlias<asm # "\t$Zt, $Pg/z, [$Rn]",
|
|
|
|
(!cast<Instruction>(NAME) zprty:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0), 0>;
|
|
|
|
def : InstAlias<asm # "\t$Zt, $Pg/z, [$Rn, $imm4, mul vl]",
|
|
|
|
(!cast<Instruction>(NAME) zprty:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, simm4s1:$imm4), 0>;
|
|
|
|
def : InstAlias<asm # "\t$Zt, $Pg/z, [$Rn]",
|
|
|
|
(!cast<Instruction>(NAME) listty:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0), 1>;
|
|
|
|
}
|
|
|
|
|
|
|
|
class sve_mem_cldnt_ss_base<bits<2> msz, string asm, RegisterOperand VecList,
|
|
|
|
RegisterOperand gprty>
|
|
|
|
: I<(outs VecList:$Zt), (ins PPR3bAny:$Pg, GPR64sp:$Rn, gprty:$Rm),
|
|
|
|
asm, "\t$Zt, $Pg/z, [$Rn, $Rm]",
|
|
|
|
"",
|
|
|
|
[]>, Sched<[]> {
|
|
|
|
bits<3> Pg;
|
|
|
|
bits<5> Rm;
|
|
|
|
bits<5> Rn;
|
|
|
|
bits<5> Zt;
|
|
|
|
let Inst{31-25} = 0b1010010;
|
|
|
|
let Inst{24-23} = msz;
|
|
|
|
let Inst{22-21} = 0b00;
|
|
|
|
let Inst{20-16} = Rm;
|
|
|
|
let Inst{15-13} = 0b110;
|
|
|
|
let Inst{12-10} = Pg;
|
|
|
|
let Inst{9-5} = Rn;
|
|
|
|
let Inst{4-0} = Zt;
|
|
|
|
|
|
|
|
let mayLoad = 1;
|
|
|
|
}
|
|
|
|
|
|
|
|
multiclass sve_mem_cldnt_ss<bits<2> msz, string asm, RegisterOperand listty,
|
|
|
|
ZPRRegOp zprty, RegisterOperand gprty> {
|
|
|
|
def NAME : sve_mem_cldnt_ss_base<msz, asm, listty, gprty>;
|
|
|
|
|
|
|
|
def : InstAlias<asm # "\t$Zt, $Pg/z, [$Rn, $Rm]",
|
|
|
|
(!cast<Instruction>(NAME) zprty:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, gprty:$Rm), 0>;
|
|
|
|
}
|
|
|
|
|
2018-05-02 16:49:08 +08:00
|
|
|
class sve_mem_ldqr_si<bits<2> sz, string asm, RegisterOperand VecList>
|
|
|
|
: I<(outs VecList:$Zt), (ins PPR3bAny:$Pg, GPR64sp:$Rn, simm4s16:$imm4),
|
|
|
|
asm, "\t$Zt, $Pg/z, [$Rn, $imm4]", "", []>, Sched<[]> {
|
|
|
|
bits<5> Zt;
|
|
|
|
bits<5> Rn;
|
|
|
|
bits<3> Pg;
|
|
|
|
bits<4> imm4;
|
|
|
|
let Inst{31-25} = 0b1010010;
|
|
|
|
let Inst{24-23} = sz;
|
|
|
|
let Inst{22-20} = 0;
|
|
|
|
let Inst{19-16} = imm4;
|
|
|
|
let Inst{15-13} = 0b001;
|
|
|
|
let Inst{12-10} = Pg;
|
|
|
|
let Inst{9-5} = Rn;
|
|
|
|
let Inst{4-0} = Zt;
|
|
|
|
|
|
|
|
let mayLoad = 1;
|
|
|
|
}
|
|
|
|
|
|
|
|
multiclass sve_mem_ldqr_si<bits<2> sz, string asm, RegisterOperand listty,
|
|
|
|
ZPRRegOp zprty> {
|
|
|
|
def NAME : sve_mem_ldqr_si<sz, asm, listty>;
|
|
|
|
def : InstAlias<asm # "\t$Zt, $Pg/z, [$Rn]",
|
|
|
|
(!cast<Instruction>(NAME) listty:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0), 1>;
|
|
|
|
def : InstAlias<asm # "\t$Zt, $Pg/z, [$Rn]",
|
|
|
|
(!cast<Instruction>(NAME) zprty:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0), 0>;
|
|
|
|
def : InstAlias<asm # "\t$Zt, $Pg/z, [$Rn, $imm4]",
|
|
|
|
(!cast<Instruction>(NAME) zprty:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, simm4s16:$imm4), 0>;
|
|
|
|
}
|
|
|
|
|
|
|
|
class sve_mem_ldqr_ss<bits<2> sz, string asm, RegisterOperand VecList,
|
|
|
|
RegisterOperand gprty>
|
|
|
|
: I<(outs VecList:$Zt), (ins PPR3bAny:$Pg, GPR64sp:$Rn, gprty:$Rm),
|
|
|
|
asm, "\t$Zt, $Pg/z, [$Rn, $Rm]", "", []>, Sched<[]> {
|
|
|
|
bits<5> Zt;
|
|
|
|
bits<3> Pg;
|
|
|
|
bits<5> Rn;
|
|
|
|
bits<5> Rm;
|
|
|
|
let Inst{31-25} = 0b1010010;
|
|
|
|
let Inst{24-23} = sz;
|
|
|
|
let Inst{22-21} = 0;
|
|
|
|
let Inst{20-16} = Rm;
|
|
|
|
let Inst{15-13} = 0;
|
|
|
|
let Inst{12-10} = Pg;
|
|
|
|
let Inst{9-5} = Rn;
|
|
|
|
let Inst{4-0} = Zt;
|
|
|
|
|
|
|
|
let mayLoad = 1;
|
|
|
|
}
|
|
|
|
|
|
|
|
multiclass sve_mem_ldqr_ss<bits<2> sz, string asm, RegisterOperand listty,
|
|
|
|
ZPRRegOp zprty, RegisterOperand gprty> {
|
|
|
|
def NAME : sve_mem_ldqr_ss<sz, asm, listty, gprty>;
|
|
|
|
|
|
|
|
def : InstAlias<asm # "\t$Zt, $Pg/z, [$Rn, $Rm]",
|
|
|
|
(!cast<Instruction>(NAME) zprty:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, gprty:$Rm), 0>;
|
|
|
|
}
|
|
|
|
|
2018-05-08 18:46:55 +08:00
|
|
|
class sve_mem_ld_dup<bits<2> dtypeh, bits<2> dtypel, string asm,
|
|
|
|
RegisterOperand VecList, Operand immtype>
|
|
|
|
: I<(outs VecList:$Zt), (ins PPR3bAny:$Pg, GPR64sp:$Rn, immtype:$imm6),
|
|
|
|
asm, "\t$Zt, $Pg/z, [$Rn, $imm6]",
|
|
|
|
"",
|
|
|
|
[]>, Sched<[]> {
|
|
|
|
bits<3> Pg;
|
|
|
|
bits<5> Rn;
|
|
|
|
bits<5> Zt;
|
|
|
|
bits<6> imm6;
|
|
|
|
let Inst{31-25} = 0b1000010;
|
|
|
|
let Inst{24-23} = dtypeh;
|
|
|
|
let Inst{22} = 1;
|
|
|
|
let Inst{21-16} = imm6;
|
|
|
|
let Inst{15} = 0b1;
|
|
|
|
let Inst{14-13} = dtypel;
|
|
|
|
let Inst{12-10} = Pg;
|
|
|
|
let Inst{9-5} = Rn;
|
|
|
|
let Inst{4-0} = Zt;
|
|
|
|
|
|
|
|
let mayLoad = 1;
|
|
|
|
}
|
|
|
|
|
|
|
|
multiclass sve_mem_ld_dup<bits<2> dtypeh, bits<2> dtypel, string asm,
|
|
|
|
RegisterOperand zlistty, ZPRRegOp zprty, Operand immtype> {
|
|
|
|
def NAME : sve_mem_ld_dup<dtypeh, dtypel, asm, zlistty, immtype>;
|
|
|
|
|
|
|
|
def : InstAlias<asm # "\t$Zt, $Pg/z, [$Rn]",
|
|
|
|
(!cast<Instruction>(NAME) zprty:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0), 0>;
|
|
|
|
def : InstAlias<asm # "\t$Zt, $Pg/z, [$Rn, $imm6]",
|
|
|
|
(!cast<Instruction>(NAME) zprty:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, immtype:$imm6), 0>;
|
|
|
|
def : InstAlias<asm # "\t$Zt, $Pg/z, [$Rn]",
|
|
|
|
(!cast<Instruction>(NAME) zlistty:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0), 1>;
|
|
|
|
}
|
|
|
|
|
2018-04-20 20:52:01 +08:00
|
|
|
class sve_mem_cld_ss_base<bits<4> dtype, bit ff, dag iops, string asm,
|
|
|
|
RegisterOperand VecList>
|
|
|
|
: I<(outs VecList:$Zt), iops,
|
|
|
|
asm, "\t$Zt, $Pg/z, [$Rn, $Rm]",
|
|
|
|
"",
|
|
|
|
[]>, Sched<[]> {
|
|
|
|
bits<5> Zt;
|
|
|
|
bits<3> Pg;
|
|
|
|
bits<5> Rm;
|
|
|
|
bits<5> Rn;
|
|
|
|
let Inst{31-25} = 0b1010010;
|
|
|
|
let Inst{24-21} = dtype;
|
|
|
|
let Inst{20-16} = Rm;
|
|
|
|
let Inst{15-14} = 0b01;
|
|
|
|
let Inst{13} = ff;
|
|
|
|
let Inst{12-10} = Pg;
|
|
|
|
let Inst{9-5} = Rn;
|
|
|
|
let Inst{4-0} = Zt;
|
|
|
|
|
|
|
|
let mayLoad = 1;
|
|
|
|
let Uses = !if(!eq(ff, 1), [FFR], []);
|
|
|
|
let Defs = !if(!eq(ff, 1), [FFR], []);
|
|
|
|
}
|
|
|
|
|
|
|
|
multiclass sve_mem_cld_ss<bits<4> dtype, string asm, RegisterOperand listty,
|
|
|
|
ZPRRegOp zprty, RegisterOperand gprty> {
|
|
|
|
def "" : sve_mem_cld_ss_base<dtype, 0, (ins PPR3bAny:$Pg, GPR64sp:$Rn, gprty:$Rm),
|
|
|
|
asm, listty>;
|
|
|
|
|
|
|
|
def : InstAlias<asm # "\t$Zt, $Pg/z, [$Rn, $Rm]",
|
|
|
|
(!cast<Instruction>(NAME) zprty:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, gprty:$Rm), 0>;
|
|
|
|
}
|
|
|
|
|
[AArch64][SVE] Asm: Support for contiguous, first-faulting LDFF1 (scalar+scalar) load instructions.
Reviewers: fhahn, rengolin, samparker, SjoerdMeijer, t.p.northover, echristo, evandro, javed.absar
Reviewed By: rengolin
Subscribers: tschuett, kristof.beyls, llvm-commits
Differential Revision: https://reviews.llvm.org/D45946
llvm-svn: 330697
2018-04-24 16:59:08 +08:00
|
|
|
multiclass sve_mem_cldff_ss<bits<4> dtype, string asm, RegisterOperand listty,
|
|
|
|
ZPRRegOp zprty, RegisterOperand gprty> {
|
|
|
|
def _REAL : sve_mem_cld_ss_base<dtype, 1, (ins PPR3bAny:$Pg, GPR64sp:$Rn, gprty:$Rm),
|
|
|
|
asm, listty>;
|
|
|
|
|
|
|
|
def : InstAlias<asm # "\t$Zt, $Pg/z, [$Rn, $Rm]",
|
|
|
|
(!cast<Instruction>(NAME # _REAL) zprty:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, gprty:$Rm), 0>;
|
|
|
|
|
|
|
|
def : InstAlias<asm # "\t$Zt, $Pg/z, [$Rn]",
|
|
|
|
(!cast<Instruction>(NAME # _REAL) listty:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, XZR), 1>;
|
|
|
|
|
|
|
|
def : InstAlias<asm # "\t$Zt, $Pg/z, [$Rn]",
|
|
|
|
(!cast<Instruction>(NAME # _REAL) zprty:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, XZR), 0>;
|
|
|
|
}
|
2018-04-20 20:52:01 +08:00
|
|
|
|
[AArch64][SVE] Asm: Support for contiguous, non-faulting LDNF1 (scalar+imm) load instructions
Reviewers: fhahn, rengolin, javed.absar, huntergr, SjoerdMeijer, t.p.northover, echristo, evandro
Reviewed By: rengolin
Subscribers: tschuett, kristof.beyls, llvm-commits
Differential Revision: https://reviews.llvm.org/D45684
llvm-svn: 330583
2018-04-23 20:43:19 +08:00
|
|
|
multiclass sve_mem_cldnf_si<bits<4> dtype, string asm, RegisterOperand listty,
|
|
|
|
ZPRRegOp zprty>
|
|
|
|
: sve_mem_cld_si_base<dtype, 1, asm, listty, zprty>;
|
|
|
|
|
2018-04-16 15:09:29 +08:00
|
|
|
class sve_mem_eld_si<bits<2> sz, bits<2> nregs, RegisterOperand VecList,
|
|
|
|
string asm, Operand immtype>
|
|
|
|
: I<(outs VecList:$Zt), (ins PPR3bAny:$Pg, GPR64sp:$Rn, immtype:$imm4),
|
|
|
|
asm, "\t$Zt, $Pg/z, [$Rn, $imm4, mul vl]",
|
|
|
|
"",
|
|
|
|
[]>, Sched<[]> {
|
|
|
|
bits<5> Zt;
|
|
|
|
bits<3> Pg;
|
|
|
|
bits<5> Rn;
|
|
|
|
bits<4> imm4;
|
|
|
|
let Inst{31-25} = 0b1010010;
|
|
|
|
let Inst{24-23} = sz;
|
|
|
|
let Inst{22-21} = nregs;
|
|
|
|
let Inst{20} = 0;
|
|
|
|
let Inst{19-16} = imm4;
|
|
|
|
let Inst{15-13} = 0b111;
|
|
|
|
let Inst{12-10} = Pg;
|
|
|
|
let Inst{9-5} = Rn;
|
|
|
|
let Inst{4-0} = Zt;
|
|
|
|
|
|
|
|
let mayLoad = 1;
|
|
|
|
}
|
|
|
|
|
|
|
|
multiclass sve_mem_eld_si<bits<2> sz, bits<2> nregs, RegisterOperand VecList,
|
|
|
|
string asm, Operand immtype> {
|
|
|
|
def NAME : sve_mem_eld_si<sz, nregs, VecList, asm, immtype>;
|
|
|
|
|
|
|
|
def : InstAlias<asm # "\t$Zt, $Pg/z, [$Rn]",
|
|
|
|
(!cast<Instruction>(NAME) VecList:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0), 1>;
|
[AArch64][SVE] Asm: Support for contiguous, first-faulting LDFF1 (scalar+scalar) load instructions.
Reviewers: fhahn, rengolin, samparker, SjoerdMeijer, t.p.northover, echristo, evandro, javed.absar
Reviewed By: rengolin
Subscribers: tschuett, kristof.beyls, llvm-commits
Differential Revision: https://reviews.llvm.org/D45946
llvm-svn: 330697
2018-04-24 16:59:08 +08:00
|
|
|
}
|
2018-04-26 16:19:53 +08:00
|
|
|
|
2018-05-16 17:16:20 +08:00
|
|
|
class sve_mem_eld_ss<bits<2> sz, bits<2> nregs, RegisterOperand VecList,
|
|
|
|
string asm, RegisterOperand gprty>
|
|
|
|
: I<(outs VecList:$Zt), (ins PPR3bAny:$Pg, GPR64sp:$Rn, gprty:$Rm),
|
|
|
|
asm, "\t$Zt, $Pg/z, [$Rn, $Rm]",
|
|
|
|
"",
|
|
|
|
[]>, Sched<[]> {
|
|
|
|
bits<3> Pg;
|
|
|
|
bits<5> Rm;
|
|
|
|
bits<5> Rn;
|
|
|
|
bits<5> Zt;
|
|
|
|
let Inst{31-25} = 0b1010010;
|
|
|
|
let Inst{24-23} = sz;
|
|
|
|
let Inst{22-21} = nregs;
|
|
|
|
let Inst{20-16} = Rm;
|
|
|
|
let Inst{15-13} = 0b110;
|
|
|
|
let Inst{12-10} = Pg;
|
|
|
|
let Inst{9-5} = Rn;
|
|
|
|
let Inst{4-0} = Zt;
|
|
|
|
|
|
|
|
let mayLoad = 1;
|
|
|
|
}
|
|
|
|
|
2018-04-26 16:19:53 +08:00
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
// SVE Memory - 32-bit Gather and Unsized Contiguous Group
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
|
|
|
|
// bit xs is '1' if offsets are signed
|
|
|
|
// bit scaled is '1' if the offsets are scaled
|
|
|
|
class sve_mem_32b_gld_sv<bits<4> opc, bit xs, bit scaled, string asm,
|
|
|
|
RegisterOperand zprext>
|
|
|
|
: I<(outs Z_s:$Zt), (ins PPR3bAny:$Pg, GPR64sp:$Rn, zprext:$Zm),
|
|
|
|
asm, "\t$Zt, $Pg/z, [$Rn, $Zm]",
|
|
|
|
"",
|
|
|
|
[]>, Sched<[]> {
|
|
|
|
bits<3> Pg;
|
|
|
|
bits<5> Rn;
|
|
|
|
bits<5> Zm;
|
|
|
|
bits<5> Zt;
|
|
|
|
let Inst{31-25} = 0b1000010;
|
|
|
|
let Inst{24-23} = opc{3-2};
|
|
|
|
let Inst{22} = xs;
|
|
|
|
let Inst{21} = scaled;
|
|
|
|
let Inst{20-16} = Zm;
|
|
|
|
let Inst{15} = 0b0;
|
|
|
|
let Inst{14-13} = opc{1-0};
|
|
|
|
let Inst{12-10} = Pg;
|
|
|
|
let Inst{9-5} = Rn;
|
|
|
|
let Inst{4-0} = Zt;
|
|
|
|
|
|
|
|
let mayLoad = 1;
|
|
|
|
let Defs = !if(!eq(opc{0}, 1), [FFR], []);
|
|
|
|
let Uses = !if(!eq(opc{0}, 1), [FFR], []);
|
|
|
|
}
|
|
|
|
|
|
|
|
multiclass sve_mem_32b_gld_sv_32_scaled<bits<4> opc, string asm,
|
|
|
|
RegisterOperand sxtw_opnd,
|
|
|
|
RegisterOperand uxtw_opnd> {
|
|
|
|
def _UXTW_SCALED_REAL : sve_mem_32b_gld_sv<opc, 0, 1, asm, uxtw_opnd>;
|
|
|
|
def _SXTW_SCALED_REAL : sve_mem_32b_gld_sv<opc, 1, 1, asm, sxtw_opnd>;
|
|
|
|
|
|
|
|
def : InstAlias<asm # "\t$Zt, $Pg/z, [$Rn, $Zm]",
|
|
|
|
(!cast<Instruction>(NAME # _UXTW_SCALED_REAL) ZPR32:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, uxtw_opnd:$Zm), 0>;
|
|
|
|
def : InstAlias<asm # "\t$Zt, $Pg/z, [$Rn, $Zm]",
|
|
|
|
(!cast<Instruction>(NAME # _SXTW_SCALED_REAL) ZPR32:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, sxtw_opnd:$Zm), 0>;
|
|
|
|
}
|
|
|
|
|
|
|
|
multiclass sve_mem_32b_gld_vs_32_unscaled<bits<4> opc, string asm,
|
|
|
|
RegisterOperand sxtw_opnd,
|
|
|
|
RegisterOperand uxtw_opnd> {
|
|
|
|
def _UXTW_REAL : sve_mem_32b_gld_sv<opc, 0, 0, asm, uxtw_opnd>;
|
|
|
|
def _SXTW_REAL : sve_mem_32b_gld_sv<opc, 1, 0, asm, sxtw_opnd>;
|
|
|
|
|
|
|
|
def : InstAlias<asm # "\t$Zt, $Pg/z, [$Rn, $Zm]",
|
|
|
|
(!cast<Instruction>(NAME # _UXTW_REAL) ZPR32:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, uxtw_opnd:$Zm), 0>;
|
|
|
|
def : InstAlias<asm # "\t$Zt, $Pg/z, [$Rn, $Zm]",
|
|
|
|
(!cast<Instruction>(NAME # _SXTW_REAL) ZPR32:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, sxtw_opnd:$Zm), 0>;
|
|
|
|
}
|
|
|
|
|
|
|
|
|
2018-04-30 01:33:38 +08:00
|
|
|
class sve_mem_32b_gld_vi<bits<4> opc, string asm, Operand imm_ty>
|
|
|
|
: I<(outs Z_s:$Zt), (ins PPR3bAny:$Pg, ZPR32:$Zn, imm_ty:$imm5),
|
|
|
|
asm, "\t$Zt, $Pg/z, [$Zn, $imm5]",
|
|
|
|
"",
|
|
|
|
[]>, Sched<[]> {
|
|
|
|
bits<3> Pg;
|
|
|
|
bits<5> Zn;
|
|
|
|
bits<5> Zt;
|
|
|
|
bits<5> imm5;
|
|
|
|
let Inst{31-25} = 0b1000010;
|
|
|
|
let Inst{24-23} = opc{3-2};
|
|
|
|
let Inst{22-21} = 0b01;
|
|
|
|
let Inst{20-16} = imm5;
|
|
|
|
let Inst{15} = 0b1;
|
|
|
|
let Inst{14-13} = opc{1-0};
|
|
|
|
let Inst{12-10} = Pg;
|
|
|
|
let Inst{9-5} = Zn;
|
|
|
|
let Inst{4-0} = Zt;
|
|
|
|
|
|
|
|
let mayLoad = 1;
|
|
|
|
let Defs = !if(!eq(opc{0}, 1), [FFR], []);
|
|
|
|
let Uses = !if(!eq(opc{0}, 1), [FFR], []);
|
|
|
|
}
|
|
|
|
|
|
|
|
multiclass sve_mem_32b_gld_vi_32_ptrs<bits<4> opc, string asm, Operand imm_ty> {
|
|
|
|
def _IMM_REAL : sve_mem_32b_gld_vi<opc, asm, imm_ty>;
|
|
|
|
|
|
|
|
def : InstAlias<asm # "\t$Zt, $Pg/z, [$Zn]",
|
|
|
|
(!cast<Instruction>(NAME # _IMM_REAL) ZPR32:$Zt, PPR3bAny:$Pg, ZPR32:$Zn, 0), 0>;
|
|
|
|
def : InstAlias<asm # "\t$Zt, $Pg/z, [$Zn, $imm5]",
|
|
|
|
(!cast<Instruction>(NAME # _IMM_REAL) ZPR32:$Zt, PPR3bAny:$Pg, ZPR32:$Zn, imm_ty:$imm5), 0>;
|
|
|
|
def : InstAlias<asm # "\t$Zt, $Pg/z, [$Zn]",
|
|
|
|
(!cast<Instruction>(NAME # _IMM_REAL) Z_s:$Zt, PPR3bAny:$Pg, ZPR32:$Zn, 0), 1>;
|
|
|
|
}
|
|
|
|
|
2018-05-16 15:50:09 +08:00
|
|
|
class sve_mem_prfm_si<bits<2> msz, string asm>
|
|
|
|
: I<(outs), (ins sve_prfop:$prfop, PPR3bAny:$Pg, GPR64sp:$Rn, simm6s1:$imm6),
|
|
|
|
asm, "\t$prfop, $Pg, [$Rn, $imm6, mul vl]",
|
|
|
|
"",
|
|
|
|
[]>, Sched<[]> {
|
|
|
|
bits<5> Rn;
|
|
|
|
bits<3> Pg;
|
|
|
|
bits<6> imm6;
|
|
|
|
bits<4> prfop;
|
|
|
|
let Inst{31-22} = 0b1000010111;
|
|
|
|
let Inst{21-16} = imm6;
|
|
|
|
let Inst{15} = 0b0;
|
|
|
|
let Inst{14-13} = msz;
|
|
|
|
let Inst{12-10} = Pg;
|
|
|
|
let Inst{9-5} = Rn;
|
|
|
|
let Inst{4} = 0b0;
|
|
|
|
let Inst{3-0} = prfop;
|
|
|
|
|
|
|
|
let hasSideEffects = 1;
|
|
|
|
}
|
|
|
|
|
|
|
|
multiclass sve_mem_prfm_si<bits<2> msz, string asm> {
|
|
|
|
def NAME : sve_mem_prfm_si<msz, asm>;
|
|
|
|
|
|
|
|
def : InstAlias<asm # "\t$prfop, $Pg, [$Rn]",
|
|
|
|
(!cast<Instruction>(NAME) sve_prfop:$prfop, PPR3bAny:$Pg, GPR64sp:$Rn, 0), 1>;
|
|
|
|
}
|
|
|
|
|
|
|
|
class sve_mem_prfm_ss<bits<3> opc, string asm, RegisterOperand gprty>
|
|
|
|
: I<(outs), (ins sve_prfop:$prfop, PPR3bAny:$Pg, GPR64sp:$Rn, gprty:$Rm),
|
|
|
|
asm, "\t$prfop, $Pg, [$Rn, $Rm]",
|
|
|
|
"",
|
|
|
|
[]>, Sched<[]> {
|
|
|
|
bits<5> Rm;
|
|
|
|
bits<5> Rn;
|
|
|
|
bits<3> Pg;
|
|
|
|
bits<4> prfop;
|
|
|
|
let Inst{31-25} = 0b1000010;
|
|
|
|
let Inst{24-23} = opc{2-1};
|
|
|
|
let Inst{22-21} = 0b00;
|
|
|
|
let Inst{20-16} = Rm;
|
|
|
|
let Inst{15} = 0b1;
|
|
|
|
let Inst{14} = opc{0};
|
|
|
|
let Inst{13} = 0b0;
|
|
|
|
let Inst{12-10} = Pg;
|
|
|
|
let Inst{9-5} = Rn;
|
|
|
|
let Inst{4} = 0b0;
|
|
|
|
let Inst{3-0} = prfop;
|
|
|
|
|
|
|
|
let hasSideEffects = 1;
|
|
|
|
}
|
|
|
|
|
2018-05-16 22:16:01 +08:00
|
|
|
class sve_mem_32b_prfm_sv<bits<2> msz, bit xs, string asm,
|
|
|
|
RegisterOperand zprext>
|
|
|
|
: I<(outs), (ins sve_prfop:$prfop, PPR3bAny:$Pg, GPR64sp:$Rn, zprext:$Zm),
|
|
|
|
asm, "\t$prfop, $Pg, [$Rn, $Zm]",
|
|
|
|
"",
|
|
|
|
[]>, Sched<[]> {
|
|
|
|
bits<3> Pg;
|
|
|
|
bits<5> Rn;
|
|
|
|
bits<5> Zm;
|
|
|
|
bits<4> prfop;
|
|
|
|
let Inst{31-23} = 0b100001000;
|
|
|
|
let Inst{22} = xs;
|
|
|
|
let Inst{21} = 0b1;
|
|
|
|
let Inst{20-16} = Zm;
|
|
|
|
let Inst{15} = 0b0;
|
|
|
|
let Inst{14-13} = msz;
|
|
|
|
let Inst{12-10} = Pg;
|
|
|
|
let Inst{9-5} = Rn;
|
|
|
|
let Inst{4} = 0b0;
|
|
|
|
let Inst{3-0} = prfop;
|
|
|
|
|
|
|
|
let hasSideEffects = 1;
|
|
|
|
}
|
|
|
|
|
|
|
|
multiclass sve_mem_32b_prfm_sv_scaled<bits<2> msz, string asm,
|
|
|
|
RegisterOperand sxtw_opnd,
|
|
|
|
RegisterOperand uxtw_opnd> {
|
|
|
|
def _UXTW_SCALED : sve_mem_32b_prfm_sv<msz, 0, asm, uxtw_opnd>;
|
|
|
|
def _SXTW_SCALED : sve_mem_32b_prfm_sv<msz, 1, asm, sxtw_opnd>;
|
|
|
|
}
|
|
|
|
|
|
|
|
class sve_mem_32b_prfm_vi<bits<2> msz, string asm, Operand imm_ty>
|
|
|
|
: I<(outs), (ins sve_prfop:$prfop, PPR3bAny:$Pg, ZPR32:$Zn, imm_ty:$imm5),
|
|
|
|
asm, "\t$prfop, $Pg, [$Zn, $imm5]",
|
|
|
|
"",
|
|
|
|
[]>, Sched<[]> {
|
|
|
|
bits<3> Pg;
|
|
|
|
bits<5> Zn;
|
|
|
|
bits<5> imm5;
|
|
|
|
bits<4> prfop;
|
|
|
|
let Inst{31-25} = 0b1000010;
|
|
|
|
let Inst{24-23} = msz;
|
|
|
|
let Inst{22-21} = 0b00;
|
|
|
|
let Inst{20-16} = imm5;
|
|
|
|
let Inst{15-13} = 0b111;
|
|
|
|
let Inst{12-10} = Pg;
|
|
|
|
let Inst{9-5} = Zn;
|
|
|
|
let Inst{4} = 0b0;
|
|
|
|
let Inst{3-0} = prfop;
|
|
|
|
}
|
|
|
|
|
|
|
|
multiclass sve_mem_32b_prfm_vi<bits<2> msz, string asm, Operand imm_ty> {
|
|
|
|
def NAME : sve_mem_32b_prfm_vi<msz, asm, imm_ty>;
|
|
|
|
|
|
|
|
def : InstAlias<asm # "\t$prfop, $Pg, [$Zn]",
|
|
|
|
(!cast<Instruction>(NAME) sve_prfop:$prfop, PPR3bAny:$Pg, ZPR32:$Zn, 0), 1>;
|
|
|
|
}
|
|
|
|
|
2018-05-02 21:32:39 +08:00
|
|
|
class sve_mem_z_fill<string asm>
|
|
|
|
: I<(outs ZPRAny:$Zt), (ins GPR64sp:$Rn, simm9:$imm9),
|
|
|
|
asm, "\t$Zt, [$Rn, $imm9, mul vl]",
|
|
|
|
"",
|
|
|
|
[]>, Sched<[]> {
|
|
|
|
bits<5> Rn;
|
|
|
|
bits<5> Zt;
|
|
|
|
bits<9> imm9;
|
|
|
|
let Inst{31-22} = 0b1000010110;
|
|
|
|
let Inst{21-16} = imm9{8-3};
|
|
|
|
let Inst{15-13} = 0b010;
|
|
|
|
let Inst{12-10} = imm9{2-0};
|
|
|
|
let Inst{9-5} = Rn;
|
|
|
|
let Inst{4-0} = Zt;
|
|
|
|
|
|
|
|
let mayLoad = 1;
|
|
|
|
}
|
|
|
|
|
|
|
|
multiclass sve_mem_z_fill<string asm> {
|
|
|
|
def NAME : sve_mem_z_fill<asm>;
|
|
|
|
|
|
|
|
def : InstAlias<asm # "\t$Zt, [$Rn]",
|
|
|
|
(!cast<Instruction>(NAME) ZPRAny:$Zt, GPR64sp:$Rn, 0), 1>;
|
|
|
|
}
|
|
|
|
|
|
|
|
class sve_mem_p_fill<string asm>
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|
|
|
: I<(outs PPRAny:$Pt), (ins GPR64sp:$Rn, simm9:$imm9),
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|
|
asm, "\t$Pt, [$Rn, $imm9, mul vl]",
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|
|
|
"",
|
|
|
|
[]>, Sched<[]> {
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|
|
|
bits<4> Pt;
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|
|
|
bits<5> Rn;
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|
|
bits<9> imm9;
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|
|
let Inst{31-22} = 0b1000010110;
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|
|
let Inst{21-16} = imm9{8-3};
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|
|
|
let Inst{15-13} = 0b000;
|
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|
|
let Inst{12-10} = imm9{2-0};
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|
|
let Inst{9-5} = Rn;
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|
|
let Inst{4} = 0b0;
|
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|
|
let Inst{3-0} = Pt;
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|
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|
let mayLoad = 1;
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|
|
}
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|
|
multiclass sve_mem_p_fill<string asm> {
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|
def NAME : sve_mem_p_fill<asm>;
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|
def : InstAlias<asm # "\t$Pt, [$Rn]",
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|
|
(!cast<Instruction>(NAME) PPRAny:$Pt, GPR64sp:$Rn, 0), 1>;
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|
}
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|
2018-04-26 16:19:53 +08:00
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|
|
//===----------------------------------------------------------------------===//
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|
|
// SVE Memory - 64-bit Gather Group
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|
|
//===----------------------------------------------------------------------===//
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// bit xs is '1' if offsets are signed
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|
|
// bit scaled is '1' if the offsets are scaled
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|
// bit lsl is '0' if the offsets are extended (uxtw/sxtw), '1' if shifted (lsl)
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|
|
class sve_mem_64b_gld_sv<bits<4> opc, bit xs, bit scaled, bit lsl, string asm,
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|
RegisterOperand zprext>
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|
: I<(outs Z_d:$Zt), (ins PPR3bAny:$Pg, GPR64sp:$Rn, zprext:$Zm),
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|
|
asm, "\t$Zt, $Pg/z, [$Rn, $Zm]",
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|
|
|
"",
|
|
|
|
[]>, Sched<[]> {
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|
|
|
bits<3> Pg;
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|
|
bits<5> Rn;
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|
|
bits<5> Zm;
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|
|
bits<5> Zt;
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|
|
let Inst{31-25} = 0b1100010;
|
|
|
|
let Inst{24-23} = opc{3-2};
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|
|
let Inst{22} = xs;
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|
|
let Inst{21} = scaled;
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|
|
|
let Inst{20-16} = Zm;
|
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|
|
let Inst{15} = lsl;
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|
|
let Inst{14-13} = opc{1-0};
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|
|
let Inst{12-10} = Pg;
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|
|
let Inst{9-5} = Rn;
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|
|
let Inst{4-0} = Zt;
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|
|
let mayLoad = 1;
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|
let Defs = !if(!eq(opc{0}, 1), [FFR], []);
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|
|
let Uses = !if(!eq(opc{0}, 1), [FFR], []);
|
|
|
|
}
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|
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|
multiclass sve_mem_64b_gld_sv_32_scaled<bits<4> opc, string asm,
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|
|
RegisterOperand sxtw_opnd,
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|
|
RegisterOperand uxtw_opnd> {
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|
|
def _UXTW_SCALED_REAL : sve_mem_64b_gld_sv<opc, 0, 1, 0, asm, uxtw_opnd>;
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|
|
def _SXTW_SCALED_REAL : sve_mem_64b_gld_sv<opc, 1, 1, 0, asm, sxtw_opnd>;
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|
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|
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|
|
def : InstAlias<asm # "\t$Zt, $Pg/z, [$Rn, $Zm]",
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|
|
|
(!cast<Instruction>(NAME # _UXTW_SCALED_REAL) ZPR64:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, uxtw_opnd:$Zm), 0>;
|
|
|
|
def : InstAlias<asm # "\t$Zt, $Pg/z, [$Rn, $Zm]",
|
|
|
|
(!cast<Instruction>(NAME # _SXTW_SCALED_REAL) ZPR64:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, sxtw_opnd:$Zm), 0>;
|
|
|
|
}
|
|
|
|
|
|
|
|
multiclass sve_mem_64b_gld_vs_32_unscaled<bits<4> opc, string asm,
|
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|
|
RegisterOperand sxtw_opnd,
|
|
|
|
RegisterOperand uxtw_opnd> {
|
|
|
|
def _UXTW_REAL : sve_mem_64b_gld_sv<opc, 0, 0, 0, asm, uxtw_opnd>;
|
|
|
|
def _SXTW_REAL : sve_mem_64b_gld_sv<opc, 1, 0, 0, asm, sxtw_opnd>;
|
|
|
|
|
|
|
|
def : InstAlias<asm # "\t$Zt, $Pg/z, [$Rn, $Zm]",
|
|
|
|
(!cast<Instruction>(NAME # _UXTW_REAL) ZPR64:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, uxtw_opnd:$Zm), 0>;
|
|
|
|
def : InstAlias<asm # "\t$Zt, $Pg/z, [$Rn, $Zm]",
|
|
|
|
(!cast<Instruction>(NAME # _SXTW_REAL) ZPR64:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, sxtw_opnd:$Zm), 0>;
|
|
|
|
}
|
|
|
|
|
|
|
|
multiclass sve_mem_64b_gld_sv2_64_scaled<bits<4> opc, string asm,
|
|
|
|
RegisterOperand zprext> {
|
|
|
|
def _SCALED_REAL : sve_mem_64b_gld_sv<opc, 1, 1, 1, asm, zprext>;
|
|
|
|
|
|
|
|
def : InstAlias<asm # "\t$Zt, $Pg/z, [$Rn, $Zm]",
|
|
|
|
(!cast<Instruction>(NAME # _SCALED_REAL) ZPR64:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, zprext:$Zm), 0>;
|
|
|
|
}
|
|
|
|
|
|
|
|
multiclass sve_mem_64b_gld_vs2_64_unscaled<bits<4> opc, string asm> {
|
|
|
|
def _REAL : sve_mem_64b_gld_sv<opc, 1, 0, 1, asm, ZPR64ExtLSL8>;
|
|
|
|
|
|
|
|
def : InstAlias<asm # "\t$Zt, $Pg/z, [$Rn, $Zm]",
|
|
|
|
(!cast<Instruction>(NAME # _REAL) ZPR64:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, ZPR64ExtLSL8:$Zm), 0>;
|
|
|
|
}
|
2018-04-30 01:33:38 +08:00
|
|
|
|
|
|
|
class sve_mem_64b_gld_vi<bits<4> opc, string asm, Operand imm_ty>
|
|
|
|
: I<(outs Z_d:$Zt), (ins PPR3bAny:$Pg, ZPR64:$Zn, imm_ty:$imm5),
|
|
|
|
asm, "\t$Zt, $Pg/z, [$Zn, $imm5]",
|
|
|
|
"",
|
|
|
|
[]>, Sched<[]> {
|
|
|
|
bits<3> Pg;
|
|
|
|
bits<5> Zn;
|
|
|
|
bits<5> Zt;
|
|
|
|
bits<5> imm5;
|
|
|
|
let Inst{31-25} = 0b1100010;
|
|
|
|
let Inst{24-23} = opc{3-2};
|
|
|
|
let Inst{22-21} = 0b01;
|
|
|
|
let Inst{20-16} = imm5;
|
|
|
|
let Inst{15} = 0b1;
|
|
|
|
let Inst{14-13} = opc{1-0};
|
|
|
|
let Inst{12-10} = Pg;
|
|
|
|
let Inst{9-5} = Zn;
|
|
|
|
let Inst{4-0} = Zt;
|
|
|
|
|
|
|
|
let mayLoad = 1;
|
|
|
|
let Defs = !if(!eq(opc{0}, 1), [FFR], []);
|
|
|
|
let Uses = !if(!eq(opc{0}, 1), [FFR], []);
|
|
|
|
}
|
|
|
|
|
|
|
|
multiclass sve_mem_64b_gld_vi_64_ptrs<bits<4> opc, string asm, Operand imm_ty> {
|
|
|
|
def _IMM_REAL : sve_mem_64b_gld_vi<opc, asm, imm_ty>;
|
|
|
|
|
|
|
|
def : InstAlias<asm # "\t$Zt, $Pg/z, [$Zn]",
|
|
|
|
(!cast<Instruction>(NAME # _IMM_REAL) ZPR64:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, 0), 0>;
|
|
|
|
def : InstAlias<asm # "\t$Zt, $Pg/z, [$Zn, $imm5]",
|
|
|
|
(!cast<Instruction>(NAME # _IMM_REAL) ZPR64:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, imm_ty:$imm5), 0>;
|
|
|
|
def : InstAlias<asm # "\t$Zt, $Pg/z, [$Zn]",
|
|
|
|
(!cast<Instruction>(NAME # _IMM_REAL) Z_d:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, 0), 1>;
|
2018-05-08 18:46:55 +08:00
|
|
|
}
|
2018-05-16 22:16:01 +08:00
|
|
|
|
|
|
|
// bit lsl is '0' if the offsets are extended (uxtw/sxtw), '1' if shifted (lsl)
|
|
|
|
class sve_mem_64b_prfm_sv<bits<2> msz, bit xs, bit lsl, string asm,
|
|
|
|
RegisterOperand zprext>
|
|
|
|
: I<(outs), (ins sve_prfop:$prfop, PPR3bAny:$Pg, GPR64sp:$Rn, zprext:$Zm),
|
|
|
|
asm, "\t$prfop, $Pg, [$Rn, $Zm]",
|
|
|
|
"",
|
|
|
|
[]>, Sched<[]> {
|
|
|
|
bits<3> Pg;
|
|
|
|
bits<5> Rn;
|
|
|
|
bits<5> Zm;
|
|
|
|
bits<4> prfop;
|
|
|
|
let Inst{31-23} = 0b110001000;
|
|
|
|
let Inst{22} = xs;
|
|
|
|
let Inst{21} = 0b1;
|
|
|
|
let Inst{20-16} = Zm;
|
|
|
|
let Inst{15} = lsl;
|
|
|
|
let Inst{14-13} = msz;
|
|
|
|
let Inst{12-10} = Pg;
|
|
|
|
let Inst{9-5} = Rn;
|
|
|
|
let Inst{4} = 0b0;
|
|
|
|
let Inst{3-0} = prfop;
|
|
|
|
|
|
|
|
let hasSideEffects = 1;
|
|
|
|
}
|
|
|
|
|
|
|
|
multiclass sve_mem_64b_prfm_sv_ext_scaled<bits<2> msz, string asm,
|
|
|
|
RegisterOperand sxtw_opnd,
|
|
|
|
RegisterOperand uxtw_opnd> {
|
|
|
|
def _UXTW_SCALED : sve_mem_64b_prfm_sv<msz, 0, 0, asm, uxtw_opnd>;
|
|
|
|
def _SXTW_SCALED : sve_mem_64b_prfm_sv<msz, 1, 0, asm, sxtw_opnd>;
|
|
|
|
}
|
|
|
|
|
|
|
|
multiclass sve_mem_64b_prfm_sv_lsl_scaled<bits<2> msz, string asm,
|
|
|
|
RegisterOperand zprext> {
|
|
|
|
def NAME : sve_mem_64b_prfm_sv<msz, 1, 1, asm, zprext>;
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
class sve_mem_64b_prfm_vi<bits<2> msz, string asm, Operand imm_ty>
|
|
|
|
: I<(outs), (ins sve_prfop:$prfop, PPR3bAny:$Pg, ZPR64:$Zn, imm_ty:$imm5),
|
|
|
|
asm, "\t$prfop, $Pg, [$Zn, $imm5]",
|
|
|
|
"",
|
|
|
|
[]>, Sched<[]> {
|
|
|
|
bits<3> Pg;
|
|
|
|
bits<5> Zn;
|
|
|
|
bits<5> imm5;
|
|
|
|
bits<4> prfop;
|
|
|
|
let Inst{31-25} = 0b1100010;
|
|
|
|
let Inst{24-23} = msz;
|
|
|
|
let Inst{22-21} = 0b00;
|
|
|
|
let Inst{20-16} = imm5;
|
|
|
|
let Inst{15-13} = 0b111;
|
|
|
|
let Inst{12-10} = Pg;
|
|
|
|
let Inst{9-5} = Zn;
|
|
|
|
let Inst{4} = 0b0;
|
|
|
|
let Inst{3-0} = prfop;
|
|
|
|
|
|
|
|
let hasSideEffects = 1;
|
|
|
|
}
|
|
|
|
|
|
|
|
multiclass sve_mem_64b_prfm_vi<bits<2> msz, string asm, Operand imm_ty> {
|
|
|
|
def NAME : sve_mem_64b_prfm_vi<msz, asm, imm_ty>;
|
|
|
|
|
|
|
|
def : InstAlias<asm # "\t$prfop, $Pg, [$Zn]",
|
|
|
|
(!cast<Instruction>(NAME) sve_prfop:$prfop, PPR3bAny:$Pg, ZPR64:$Zn, 0), 1>;
|
|
|
|
}
|
[AArch64][SVE] Asm: Support for ADR instruction.
Supporting various addressing modes:
- adr z0.s, [z0.s, z0.s]
- adr z0.s, [z0.s, z0.s, lsl #<shift>]
- adr z0.d, [z0.d, z0.d]
- adr z0.d, [z0.d, z0.d, lsl #<shift>]
- adr z0.d, [z0.d, z0.d, uxtw #<shift>]
- adr z0.d, [z0.d, z0.d, sxtw #<shift>]
Reviewers: rengolin, fhahn, SjoerdMeijer, samparker, javed.absar
Reviewed By: SjoerdMeijer
Differential Revision: https://reviews.llvm.org/D48870
llvm-svn: 336533
2018-07-09 17:58:24 +08:00
|
|
|
|
|
|
|
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
// SVE Compute Vector Address Group
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
|
|
|
|
class sve_int_bin_cons_misc_0_a<bits<2> opc, bits<2> msz, string asm,
|
|
|
|
ZPRRegOp zprty, RegisterOperand zprext>
|
|
|
|
: I<(outs zprty:$Zd), (ins zprty:$Zn, zprext:$Zm),
|
|
|
|
asm, "\t$Zd, [$Zn, $Zm]",
|
|
|
|
"",
|
|
|
|
[]>, Sched<[]> {
|
|
|
|
bits<5> Zd;
|
|
|
|
bits<5> Zn;
|
|
|
|
bits<5> Zm;
|
|
|
|
let Inst{31-24} = 0b00000100;
|
|
|
|
let Inst{23-22} = opc;
|
|
|
|
let Inst{21} = 0b1;
|
|
|
|
let Inst{20-16} = Zm;
|
|
|
|
let Inst{15-12} = 0b1010;
|
|
|
|
let Inst{11-10} = msz;
|
|
|
|
let Inst{9-5} = Zn;
|
|
|
|
let Inst{4-0} = Zd;
|
|
|
|
}
|
|
|
|
|
|
|
|
multiclass sve_int_bin_cons_misc_0_a_uxtw<bits<2> opc, string asm> {
|
|
|
|
def _0 : sve_int_bin_cons_misc_0_a<opc, 0b00, asm, ZPR64, ZPR64ExtUXTW8>;
|
|
|
|
def _1 : sve_int_bin_cons_misc_0_a<opc, 0b01, asm, ZPR64, ZPR64ExtUXTW16>;
|
|
|
|
def _2 : sve_int_bin_cons_misc_0_a<opc, 0b10, asm, ZPR64, ZPR64ExtUXTW32>;
|
|
|
|
def _3 : sve_int_bin_cons_misc_0_a<opc, 0b11, asm, ZPR64, ZPR64ExtUXTW64>;
|
|
|
|
}
|
|
|
|
|
|
|
|
multiclass sve_int_bin_cons_misc_0_a_sxtw<bits<2> opc, string asm> {
|
|
|
|
def _0 : sve_int_bin_cons_misc_0_a<opc, 0b00, asm, ZPR64, ZPR64ExtSXTW8>;
|
|
|
|
def _1 : sve_int_bin_cons_misc_0_a<opc, 0b01, asm, ZPR64, ZPR64ExtSXTW16>;
|
|
|
|
def _2 : sve_int_bin_cons_misc_0_a<opc, 0b10, asm, ZPR64, ZPR64ExtSXTW32>;
|
|
|
|
def _3 : sve_int_bin_cons_misc_0_a<opc, 0b11, asm, ZPR64, ZPR64ExtSXTW64>;
|
|
|
|
}
|
|
|
|
|
|
|
|
multiclass sve_int_bin_cons_misc_0_a_32_lsl<bits<2> opc, string asm> {
|
|
|
|
def _0 : sve_int_bin_cons_misc_0_a<opc, 0b00, asm, ZPR32, ZPR32ExtLSL8>;
|
|
|
|
def _1 : sve_int_bin_cons_misc_0_a<opc, 0b01, asm, ZPR32, ZPR32ExtLSL16>;
|
|
|
|
def _2 : sve_int_bin_cons_misc_0_a<opc, 0b10, asm, ZPR32, ZPR32ExtLSL32>;
|
|
|
|
def _3 : sve_int_bin_cons_misc_0_a<opc, 0b11, asm, ZPR32, ZPR32ExtLSL64>;
|
|
|
|
}
|
|
|
|
|
|
|
|
multiclass sve_int_bin_cons_misc_0_a_64_lsl<bits<2> opc, string asm> {
|
|
|
|
def _0 : sve_int_bin_cons_misc_0_a<opc, 0b00, asm, ZPR64, ZPR64ExtLSL8>;
|
|
|
|
def _1 : sve_int_bin_cons_misc_0_a<opc, 0b01, asm, ZPR64, ZPR64ExtLSL16>;
|
|
|
|
def _2 : sve_int_bin_cons_misc_0_a<opc, 0b10, asm, ZPR64, ZPR64ExtLSL32>;
|
|
|
|
def _3 : sve_int_bin_cons_misc_0_a<opc, 0b11, asm, ZPR64, ZPR64ExtLSL64>;
|
|
|
|
}
|