2017-05-10 17:42:49 +08:00
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//===--- ExpandReductions.cpp - Expand experimental reduction intrinsics --===//
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//
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2019-01-19 16:50:56 +08:00
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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2017-05-10 17:42:49 +08:00
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//
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//===----------------------------------------------------------------------===//
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//
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// This pass implements IR expansion for reduction intrinsics, allowing targets
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// to enable the experimental intrinsics until just before codegen.
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//
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//===----------------------------------------------------------------------===//
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#include "llvm/CodeGen/ExpandReductions.h"
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2017-06-06 19:49:48 +08:00
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#include "llvm/Analysis/TargetTransformInfo.h"
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2017-05-10 17:42:49 +08:00
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#include "llvm/CodeGen/Passes.h"
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#include "llvm/IR/Function.h"
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#include "llvm/IR/IRBuilder.h"
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#include "llvm/IR/InstIterator.h"
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#include "llvm/IR/IntrinsicInst.h"
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2017-06-06 19:49:48 +08:00
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#include "llvm/IR/Intrinsics.h"
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2017-05-10 17:42:49 +08:00
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#include "llvm/IR/Module.h"
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#include "llvm/Pass.h"
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2017-06-06 19:49:48 +08:00
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#include "llvm/Transforms/Utils/LoopUtils.h"
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2017-05-10 17:42:49 +08:00
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using namespace llvm;
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namespace {
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unsigned getOpcode(Intrinsic::ID ID) {
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switch (ID) {
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case Intrinsic::experimental_vector_reduce_fadd:
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return Instruction::FAdd;
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case Intrinsic::experimental_vector_reduce_fmul:
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return Instruction::FMul;
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case Intrinsic::experimental_vector_reduce_add:
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return Instruction::Add;
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case Intrinsic::experimental_vector_reduce_mul:
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return Instruction::Mul;
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case Intrinsic::experimental_vector_reduce_and:
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return Instruction::And;
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case Intrinsic::experimental_vector_reduce_or:
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return Instruction::Or;
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case Intrinsic::experimental_vector_reduce_xor:
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return Instruction::Xor;
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case Intrinsic::experimental_vector_reduce_smax:
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case Intrinsic::experimental_vector_reduce_smin:
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case Intrinsic::experimental_vector_reduce_umax:
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case Intrinsic::experimental_vector_reduce_umin:
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return Instruction::ICmp;
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case Intrinsic::experimental_vector_reduce_fmax:
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case Intrinsic::experimental_vector_reduce_fmin:
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return Instruction::FCmp;
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default:
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llvm_unreachable("Unexpected ID");
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}
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}
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RecurrenceDescriptor::MinMaxRecurrenceKind getMRK(Intrinsic::ID ID) {
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switch (ID) {
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case Intrinsic::experimental_vector_reduce_smax:
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return RecurrenceDescriptor::MRK_SIntMax;
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case Intrinsic::experimental_vector_reduce_smin:
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return RecurrenceDescriptor::MRK_SIntMin;
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case Intrinsic::experimental_vector_reduce_umax:
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return RecurrenceDescriptor::MRK_UIntMax;
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case Intrinsic::experimental_vector_reduce_umin:
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return RecurrenceDescriptor::MRK_UIntMin;
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case Intrinsic::experimental_vector_reduce_fmax:
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return RecurrenceDescriptor::MRK_FloatMax;
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case Intrinsic::experimental_vector_reduce_fmin:
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return RecurrenceDescriptor::MRK_FloatMin;
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default:
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return RecurrenceDescriptor::MRK_Invalid;
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}
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}
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bool expandReductions(Function &F, const TargetTransformInfo *TTI) {
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bool Changed = false;
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2018-04-09 23:44:20 +08:00
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SmallVector<IntrinsicInst *, 4> Worklist;
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2017-05-10 17:42:49 +08:00
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for (inst_iterator I = inst_begin(F), E = inst_end(F); I != E; ++I)
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if (auto II = dyn_cast<IntrinsicInst>(&*I))
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Worklist.push_back(II);
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for (auto *II : Worklist) {
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IRBuilder<> Builder(II);
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2018-04-09 23:44:20 +08:00
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bool IsOrdered = false;
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Value *Acc = nullptr;
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2017-05-10 17:42:49 +08:00
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Value *Vec = nullptr;
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auto ID = II->getIntrinsicID();
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auto MRK = RecurrenceDescriptor::MRK_Invalid;
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switch (ID) {
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case Intrinsic::experimental_vector_reduce_fadd:
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case Intrinsic::experimental_vector_reduce_fmul:
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// FMFs must be attached to the call, otherwise it's an ordered reduction
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2018-04-09 23:44:20 +08:00
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// and it can't be handled by generating a shuffle sequence.
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[IR] redefine 'UnsafeAlgebra' / 'reassoc' fast-math-flags and add 'trans' fast-math-flag
As discussed on llvm-dev:
http://lists.llvm.org/pipermail/llvm-dev/2016-November/107104.html
and again more recently:
http://lists.llvm.org/pipermail/llvm-dev/2017-October/118118.html
...this is a step in cleaning up our fast-math-flags implementation in IR to better match
the capabilities of both clang's user-visible flags and the backend's flags for SDNode.
As proposed in the above threads, we're replacing the 'UnsafeAlgebra' bit (which had the
'umbrella' meaning that all flags are set) with a new bit that only applies to algebraic
reassociation - 'AllowReassoc'.
We're also adding a bit to allow approximations for library functions called 'ApproxFunc'
(this was initially proposed as 'libm' or similar).
...and we're out of bits. 7 bits ought to be enough for anyone, right? :) FWIW, I did
look at getting this out of SubclassOptionalData via SubclassData (spacious 16-bits),
but that's apparently already used for other purposes. Also, I don't think we can just
add a field to FPMathOperator because Operator is not intended to be instantiated.
We'll defer movement of FMF to another day.
We keep the 'fast' keyword. I thought about removing that, but seeing IR like this:
%f.fast = fadd reassoc nnan ninf nsz arcp contract afn float %op1, %op2
...made me think we want to keep the shortcut synonym.
Finally, this change is binary incompatible with existing IR as seen in the
compatibility tests. This statement:
"Newer releases can ignore features from older releases, but they cannot miscompile
them. For example, if nsw is ever replaced with something else, dropping it would be
a valid way to upgrade the IR."
( http://llvm.org/docs/DeveloperPolicy.html#ir-backwards-compatibility )
...provides the flexibility we want to make this change without requiring a new IR
version. Ie, we're not loosening the FP strictness of existing IR. At worst, we will
fail to optimize some previously 'fast' code because it's no longer recognized as
'fast'. This should get fixed as we audit/squash all of the uses of 'isFast()'.
Note: an inter-dependent clang commit to use the new API name should closely follow
commit.
Differential Revision: https://reviews.llvm.org/D39304
llvm-svn: 317488
2017-11-07 00:27:15 +08:00
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if (!II->getFastMathFlags().isFast())
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2018-04-09 23:44:20 +08:00
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IsOrdered = true;
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Acc = II->getArgOperand(0);
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2017-05-10 17:42:49 +08:00
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Vec = II->getArgOperand(1);
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break;
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case Intrinsic::experimental_vector_reduce_add:
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case Intrinsic::experimental_vector_reduce_mul:
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case Intrinsic::experimental_vector_reduce_and:
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case Intrinsic::experimental_vector_reduce_or:
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case Intrinsic::experimental_vector_reduce_xor:
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case Intrinsic::experimental_vector_reduce_smax:
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case Intrinsic::experimental_vector_reduce_smin:
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case Intrinsic::experimental_vector_reduce_umax:
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case Intrinsic::experimental_vector_reduce_umin:
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case Intrinsic::experimental_vector_reduce_fmax:
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case Intrinsic::experimental_vector_reduce_fmin:
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Vec = II->getArgOperand(0);
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MRK = getMRK(ID);
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break;
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default:
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continue;
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}
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if (!TTI->shouldExpandReduction(II))
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continue;
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2019-06-05 22:58:04 +08:00
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// Propagate FMF using the builder.
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Reland "Relax constraints for reduction vectorization"
Change from original commit: move test (that uses an X86 triple) into the X86
subdirectory.
Original description:
Gating vectorizing reductions on *all* fastmath flags seems unnecessary;
`reassoc` should be sufficient.
Reviewers: tvvikram, mkuper, kristof.beyls, sdesmalen, Ayal
Reviewed By: sdesmalen
Subscribers: dcaballe, huntergr, jmolloy, mcrosier, jlebar, bixia, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D57728
llvm-svn: 355889
2019-03-12 09:31:44 +08:00
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FastMathFlags FMF =
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isa<FPMathOperator>(II) ? II->getFastMathFlags() : FastMathFlags{};
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2019-06-05 22:58:04 +08:00
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IRBuilder<>::FastMathFlagGuard FMFGuard(Builder);
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Builder.setFastMathFlags(FMF);
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2018-04-09 23:44:20 +08:00
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Value *Rdx =
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IsOrdered ? getOrderedReduction(Builder, Acc, Vec, getOpcode(ID), MRK)
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2019-06-05 22:58:04 +08:00
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: getShuffleReduction(Builder, Vec, getOpcode(ID), MRK);
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2017-05-10 17:42:49 +08:00
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II->replaceAllUsesWith(Rdx);
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II->eraseFromParent();
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Changed = true;
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}
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return Changed;
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}
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class ExpandReductions : public FunctionPass {
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public:
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static char ID;
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ExpandReductions() : FunctionPass(ID) {
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initializeExpandReductionsPass(*PassRegistry::getPassRegistry());
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}
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bool runOnFunction(Function &F) override {
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const auto *TTI =&getAnalysis<TargetTransformInfoWrapperPass>().getTTI(F);
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return expandReductions(F, TTI);
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}
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void getAnalysisUsage(AnalysisUsage &AU) const override {
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AU.addRequired<TargetTransformInfoWrapperPass>();
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AU.setPreservesCFG();
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}
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};
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}
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char ExpandReductions::ID;
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INITIALIZE_PASS_BEGIN(ExpandReductions, "expand-reductions",
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"Expand reduction intrinsics", false, false)
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INITIALIZE_PASS_DEPENDENCY(TargetTransformInfoWrapperPass)
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INITIALIZE_PASS_END(ExpandReductions, "expand-reductions",
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"Expand reduction intrinsics", false, false)
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FunctionPass *llvm::createExpandReductionsPass() {
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return new ExpandReductions();
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}
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PreservedAnalyses ExpandReductionsPass::run(Function &F,
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FunctionAnalysisManager &AM) {
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const auto &TTI = AM.getResult<TargetIRAnalysis>(F);
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if (!expandReductions(F, &TTI))
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return PreservedAnalyses::all();
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PreservedAnalyses PA;
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PA.preserveSet<CFGAnalyses>();
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return PA;
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}
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