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llvm-project/llvm/lib/Target/Mips/Mips64InstrInfo.td

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Add .td file. llvm-svn: 140446
2011-09-24 09:40:18 +08:00
//===- Mips64InstrInfo.td - Mips64 Instruction Information -*- tablegen -*-===//
//
// The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
//
// This file describes Mips64 instructions.
//
//===----------------------------------------------------------------------===//
Mips64 predicate definitions. Patch by Liu. llvm-svn: 140703
2011-09-29 01:50:27 +08:00
Mips64 arithmetic and logical instructions with one source register and immediate. llvm-svn: 140839
2011-09-30 10:08:54 +08:00
//===----------------------------------------------------------------------===//
// Mips Operand, Complex Patterns and Transformations Definitions.
//===----------------------------------------------------------------------===//
// Unsigned Operand
def uimm16_64 : Operand<i64> {
let PrintMethod = "printUnsignedImm";
}
[mips] Add Octeon cnMips instructions seqi/snei and v3mulu/vmm0/vmulu. This patch adds the Octeon cnMips instructions seqi/snei and v3mulu/vmm0/vmulu. It is only for the assembler. Test case is included. Reviewed by: Daniel.Sanders@imgtec.com llvm-svn: 205631
2014-04-05 00:21:59 +08:00
// Signed Operand
def simm10_64 : Operand<i64>;
Mips64 shift instructions. llvm-svn: 140841
2011-09-30 11:18:46 +08:00
// Transformation Function - get Imm - 32.
def Subtract32 : SDNodeXForm<imm, [{
Fix 64-bit immediate patterns. llvm-svn: 146059
2011-12-08 04:10:24 +08:00
return getImm(N, (unsigned)N->getZExtValue() - 32);
Mips64 shift instructions. llvm-svn: 140841
2011-09-30 11:18:46 +08:00
}]>;
Remove definitions of double word shift plus 32 instructions. Assembler or direct-object emitter should emit the appropriate shift instruction depending on the shift amount. llvm-svn: 146893
2011-12-20 03:44:09 +08:00
// shamt must fit in 6 bits.
def immZExt6 : ImmLeaf<i32, [{return Imm == (Imm & 0x3f);}]>;
Mips64 shift instructions. llvm-svn: 140841
2011-09-30 11:18:46 +08:00
[mips] Add Octeon cnMips instructions seqi/snei and v3mulu/vmm0/vmulu. This patch adds the Octeon cnMips instructions seqi/snei and v3mulu/vmm0/vmulu. It is only for the assembler. Test case is included. Reviewed by: Daniel.Sanders@imgtec.com llvm-svn: 205631
2014-04-05 00:21:59 +08:00
// Node immediate fits as 10-bit sign extended on target immediate.
// e.g. seqi, snei
def immSExt10_64 : PatLeaf<(i64 imm),
[{ return isInt<10>(N->getSExtValue()); }]>;
[mips][mips64r6] c.cond.fmt, mov[fntz], and mov[fntz].[ds] are not available on MIPS32r6/MIPS64r6 Summary: c.cond.fmt has been replaced by cmp.cond.fmt. Where c.cond.fmt wrote to dedicated condition registers, cmp.cond.fmt writes 1 or 0 to normal FGR's (like the GPR comparisons). mov[fntz] have been replaced by seleqz and selnez. These instructions conditionally zero a register based on a bool in a GPR. The results can then be or'd together to act as a select without, for example, requiring a third register read port. mov[fntz].[ds] have been replaced with sel.[ds] MIPS64r6 currently generates unnecessary sign-extensions for most selects. This is because the result of a SETCC is currently an i32. Bits 32-63 are undefined in i32 and the behaviour of seleqz/selnez would otherwise depend on undefined bits. Later, we will fix this by making the result of SETCC an i64 on MIPS64 targets. Depends on D3958 Reviewers: jkolek, vmedic, zoran.jovanovic Reviewed By: vmedic, zoran.jovanovic Differential Revision: http://reviews.llvm.org/D4003 llvm-svn: 210777
2014-06-12 21:39:06 +08:00
def immZExt16_64 : PatLeaf<(i64 imm),
[{ return isInt<16>(N->getZExtValue()); }]>;
Mips64 arithmetic and logical instructions with two source registers. llvm-svn: 140806
2011-09-30 04:37:56 +08:00
//===----------------------------------------------------------------------===//
// Instructions specific format
//===----------------------------------------------------------------------===//
[mips] Resolve register classes dynamically using ptr_rc to reduce the number of load/store instructions defined. Previously, we were defining load/store instructions for each pointer size (32 and 64-bit), but now we need just one definition. llvm-svn: 188830
2013-08-21 05:08:22 +08:00
let usesCustomInserter = 1 in {
def ATOMIC_LOAD_ADD_I64 : Atomic2Ops<atomic_load_add_64, GPR64>;
def ATOMIC_LOAD_SUB_I64 : Atomic2Ops<atomic_load_sub_64, GPR64>;
def ATOMIC_LOAD_AND_I64 : Atomic2Ops<atomic_load_and_64, GPR64>;
def ATOMIC_LOAD_OR_I64 : Atomic2Ops<atomic_load_or_64, GPR64>;
def ATOMIC_LOAD_XOR_I64 : Atomic2Ops<atomic_load_xor_64, GPR64>;
def ATOMIC_LOAD_NAND_I64 : Atomic2Ops<atomic_load_nand_64, GPR64>;
def ATOMIC_SWAP_I64 : Atomic2Ops<atomic_swap_64, GPR64>;
def ATOMIC_CMP_SWAP_I64 : AtomicCmpSwap<atomic_cmp_swap_64, GPR64>;
64-bit atomic instructions. llvm-svn: 144372
2011-11-11 12:14:30 +08:00
}
[mips] Fix handling of instructions which copy to/from accumulator registers. Expand copy instructions between two accumulator registers before callee-saved scan is done. Handle copies between integer GPR and hi/lo registers in MipsSEInstrInfo::copyPhysReg. Delete pseudo-copy instructions that are not needed. llvm-svn: 180827
2013-05-01 07:22:09 +08:00
/// Pseudo instructions for loading and storing accumulator registers.
[mips] Make load/store accumulator pseudo instructions codeGenOnly. Also, remove lines that are setting DecoderNamespace for pseudo atomic instructions. No intended functionality change. llvm-svn: 187632
2013-08-02 07:14:16 +08:00
let isPseudo = 1, isCodeGenOnly = 1 in {
[mips] Resolve register classes dynamically using ptr_rc to reduce the number of load/store instructions defined. Previously, we were defining load/store instructions for each pointer size (32 and 64-bit), but now we need just one definition. llvm-svn: 188830
2013-08-21 05:08:22 +08:00
def LOAD_ACC128 : Load<"", ACC128>;
def STORE_ACC128 : Store<"", ACC128>;
[mips] Define pseudo instructions for spilling and copying accumulator registers. llvm-svn: 178390
2013-03-30 08:54:52 +08:00
}
Mips64 arithmetic and logical instructions with two source registers. llvm-svn: 140806
2011-09-30 04:37:56 +08:00
//===----------------------------------------------------------------------===//
// Instruction definition
//===----------------------------------------------------------------------===//
Add disassembler to MIPS. Patch by Vladimir Medic. llvm-svn: 154935
2012-04-18 02:03:21 +08:00
let DecoderNamespace = "Mips64" in {
Mips64 arithmetic and logical instructions with one source register and immediate. llvm-svn: 140839
2011-09-30 10:08:54 +08:00
/// Arithmetic Instructions (ALU Immediate)
[mips] Marked up instructions added in MIPS-III and tested that IAS for -mcpu=mips[12] does not accept them Summary: This required a new instruction group representing the 32-bit subset of MIPS-III that was available in MIPS32 A small number of instructions are correctly rejected but with the wrong error message. These have been placed in a separate test for now. There's some obvious InstAlias's that ought to be marked MIPS-III but arent. This is because they are not currently tested. I intend to catch these with a final pass through the tablegen records to find tablegen records without ISA annotations. Depends on D3674 Reviewers: vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3675 llvm-svn: 208408
2014-05-09 21:02:27 +08:00
def DADDi : ArithLogicI<"daddi", simm16_64, GPR64Opnd>, ADDI_FM<0x18>,
ISA_MIPS3;
[mips][sched] Split IIArith in preparation for the first scheduler targeting a specific MIPS CPU. IIArith -> II_ADD, II_ADDU, II_AND, II_CL[ZO], II_DADDIU, II_DADDU, II_DROTR, II_DROTR32, II_DROTRV, II_DSLL, II_DSLL32, II_DSLLV, II_DSR[AL], II_DSR[AL]32, II_DSR[AL]V, II_DSUBU, II_LUI, II_MOV[ZFNT], II_NOR, II_OR, II_RDHWR, II_ROTR, II_ROTRV, II_SLL, II_SLLV, II_SR[AL], II_SR[AL]V, II_SUBU, II_XOR No functional change since the InstrItinData's have been duplicated. This is necessary because the classes are shared between all schedulers. Once this patch series is committed there will be an InstrItinClass for each mnemonic with minimal grouping. This does increase the size of the itinerary tables for each MIPS scheduler but we have a few options for dealing with that later. These options include reducing the number of classes once we see the best way to simplify them, or by extending tablegen to be able to compress the table by eliminating duplicates entries, etc. llvm-svn: 199391
2014-01-16 22:27:20 +08:00
def DADDiu : ArithLogicI<"daddiu", simm16_64, GPR64Opnd, II_DADDIU,
[mips] Define instruction itineraries IIArith and IILogic. No functionality change. llvm-svn: 187468
2013-07-31 08:55:34 +08:00
immSExt16, add>,
[mips] Marked up instructions added in MIPS-III and tested that IAS for -mcpu=mips[12] does not accept them Summary: This required a new instruction group representing the 32-bit subset of MIPS-III that was available in MIPS32 A small number of instructions are correctly rejected but with the wrong error message. These have been placed in a separate test for now. There's some obvious InstAlias's that ought to be marked MIPS-III but arent. This is because they are not currently tested. I intend to catch these with a final pass through the tablegen records to find tablegen records without ISA annotations. Depends on D3674 Reviewers: vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3675 llvm-svn: 208408
2014-05-09 21:02:27 +08:00
ADDI_FM<0x19>, IsAsCheapAsAMove, ISA_MIPS3;
[mips] Mark instructions defined in Mips64InstrInfo.td that are duplicates of instructions defined in MipsInstrInfo.td as codegen-only instructions. llvm-svn: 187828
2013-08-07 07:01:10 +08:00
let isCodeGenOnly = 1 in {
[mips] Rename register classes CPURegs and CPU64Regs. llvm-svn: 187832
2013-08-07 07:08:38 +08:00
def SLTi64 : SetCC_I<"slti", setlt, simm16_64, immSExt16, GPR64Opnd>,
[mips] Refactor SLT (set on less than) instructions. Separate encoding information from the rest. llvm-svn: 170664
2012-12-20 12:27:52 +08:00
SLTI_FM<0xa>;
[mips] Rename register classes CPURegs and CPU64Regs. llvm-svn: 187832
2013-08-07 07:08:38 +08:00
def SLTiu64 : SetCC_I<"sltiu", setult, simm16_64, immSExt16, GPR64Opnd>,
[mips] Refactor SLT (set on less than) instructions. Separate encoding information from the rest. llvm-svn: 170664
2012-12-20 12:27:52 +08:00
SLTI_FM<0xb>;
[mips][sched] Split IILogic into II_AND, II_OR, II_XOR, II_ANDI, II_ORI, II_XORI This is necessary because the classes are shared between all implementations. No functional change since the InstrItinData's have been duplicated. llvm-svn: 199394
2014-01-16 23:57:05 +08:00
def ANDi64 : ArithLogicI<"andi", uimm16_64, GPR64Opnd, II_AND, immZExt16, and>,
[mips] Rename instruction DANDi to ANDi64. No functionality change. llvm-svn: 187469
2013-07-31 08:57:41 +08:00
ADDI_FM<0xc>;
[mips][sched] Split IILogic into II_AND, II_OR, II_XOR, II_ANDI, II_ORI, II_XORI This is necessary because the classes are shared between all implementations. No functional change since the InstrItinData's have been duplicated. llvm-svn: 199394
2014-01-16 23:57:05 +08:00
def ORi64 : ArithLogicI<"ori", uimm16_64, GPR64Opnd, II_OR, immZExt16, or>,
[mips] Refactor arithmetic and logic instructions with immediate operands. Separate encoding information from the rest. llvm-svn: 170648
2012-12-20 11:40:03 +08:00
ADDI_FM<0xd>;
[mips][sched] Split IILogic into II_AND, II_OR, II_XOR, II_ANDI, II_ORI, II_XORI This is necessary because the classes are shared between all implementations. No functional change since the InstrItinData's have been duplicated. llvm-svn: 199394
2014-01-16 23:57:05 +08:00
def XORi64 : ArithLogicI<"xori", uimm16_64, GPR64Opnd, II_XOR, immZExt16, xor>,
[mips] Refactor arithmetic and logic instructions with immediate operands. Separate encoding information from the rest. llvm-svn: 170648
2012-12-20 11:40:03 +08:00
ADDI_FM<0xe>;
[mips] Rename register classes CPURegs and CPU64Regs. llvm-svn: 187832
2013-08-07 07:08:38 +08:00
def LUi64 : LoadUpper<"lui", GPR64Opnd, uimm16_64>, LUI_FM;
[mips] Mark instructions defined in Mips64InstrInfo.td that are duplicates of instructions defined in MipsInstrInfo.td as codegen-only instructions. llvm-svn: 187828
2013-08-07 07:01:10 +08:00
}
Mips64 arithmetic and logical instructions with one source register and immediate. llvm-svn: 140839
2011-09-30 10:08:54 +08:00
Mips64 arithmetic and logical instructions with two source registers. llvm-svn: 140806
2011-09-30 04:37:56 +08:00
/// Arithmetic Instructions (3-Operand, R-Type)
[mips] Marked up instructions added in MIPS-III and tested that IAS for -mcpu=mips[12] does not accept them Summary: This required a new instruction group representing the 32-bit subset of MIPS-III that was available in MIPS32 A small number of instructions are correctly rejected but with the wrong error message. These have been placed in a separate test for now. There's some obvious InstAlias's that ought to be marked MIPS-III but arent. This is because they are not currently tested. I intend to catch these with a final pass through the tablegen records to find tablegen records without ISA annotations. Depends on D3674 Reviewers: vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3675 llvm-svn: 208408
2014-05-09 21:02:27 +08:00
def DADD : ArithLogicR<"dadd", GPR64Opnd, 1, II_DADD>, ADD_FM<0, 0x2c>,
ISA_MIPS3;
def DADDu : ArithLogicR<"daddu", GPR64Opnd, 1, II_DADDU, add>, ADD_FM<0, 0x2d>,
ISA_MIPS3;
def DSUBu : ArithLogicR<"dsubu", GPR64Opnd, 0, II_DSUBU, sub>, ADD_FM<0, 0x2f>,
ISA_MIPS3;
def DSUB : ArithLogicR<"dsub", GPR64Opnd, 0, II_DSUB>, ADD_FM<0, 0x2e>,
ISA_MIPS3;
[mips] Delete unnecessary InstAliases. Also, clear some of the InstAlias' EmitAlias flag and have MipsInstPrinter::printAlias print the aliases. llvm-svn: 187824
2013-08-07 06:35:29 +08:00
let isCodeGenOnly = 1 in {
[mips] Rename register classes CPURegs and CPU64Regs. llvm-svn: 187832
2013-08-07 07:08:38 +08:00
def SLT64 : SetCC_R<"slt", setlt, GPR64Opnd>, ADD_FM<0, 0x2a>;
def SLTu64 : SetCC_R<"sltu", setult, GPR64Opnd>, ADD_FM<0, 0x2b>;
[mips][sched] Split IIArith in preparation for the first scheduler targeting a specific MIPS CPU. IIArith -> II_ADD, II_ADDU, II_AND, II_CL[ZO], II_DADDIU, II_DADDU, II_DROTR, II_DROTR32, II_DROTRV, II_DSLL, II_DSLL32, II_DSLLV, II_DSR[AL], II_DSR[AL]32, II_DSR[AL]V, II_DSUBU, II_LUI, II_MOV[ZFNT], II_NOR, II_OR, II_RDHWR, II_ROTR, II_ROTRV, II_SLL, II_SLLV, II_SR[AL], II_SR[AL]V, II_SUBU, II_XOR No functional change since the InstrItinData's have been duplicated. This is necessary because the classes are shared between all schedulers. Once this patch series is committed there will be an InstrItinClass for each mnemonic with minimal grouping. This does increase the size of the itinerary tables for each MIPS scheduler but we have a few options for dealing with that later. These options include reducing the number of classes once we see the best way to simplify them, or by extending tablegen to be able to compress the table by eliminating duplicates entries, etc. llvm-svn: 199391
2014-01-16 22:27:20 +08:00
def AND64 : ArithLogicR<"and", GPR64Opnd, 1, II_AND, and>, ADD_FM<0, 0x24>;
def OR64 : ArithLogicR<"or", GPR64Opnd, 1, II_OR, or>, ADD_FM<0, 0x25>;
def XOR64 : ArithLogicR<"xor", GPR64Opnd, 1, II_XOR, xor>, ADD_FM<0, 0x26>;
[mips] Rename register classes CPURegs and CPU64Regs. llvm-svn: 187832
2013-08-07 07:08:38 +08:00
def NOR64 : LogicNOR<"nor", GPR64Opnd>, ADD_FM<0, 0x27>;
[mips] Delete unnecessary InstAliases. Also, clear some of the InstAlias' EmitAlias flag and have MipsInstPrinter::printAlias print the aliases. llvm-svn: 187824
2013-08-07 06:35:29 +08:00
}
Mips64 shift instructions. llvm-svn: 140841
2011-09-30 11:18:46 +08:00
/// Shift Instructions
[mips][sched] Split IIArith in preparation for the first scheduler targeting a specific MIPS CPU. IIArith -> II_ADD, II_ADDU, II_AND, II_CL[ZO], II_DADDIU, II_DADDU, II_DROTR, II_DROTR32, II_DROTRV, II_DSLL, II_DSLL32, II_DSLLV, II_DSR[AL], II_DSR[AL]32, II_DSR[AL]V, II_DSUBU, II_LUI, II_MOV[ZFNT], II_NOR, II_OR, II_RDHWR, II_ROTR, II_ROTRV, II_SLL, II_SLLV, II_SR[AL], II_SR[AL]V, II_SUBU, II_XOR No functional change since the InstrItinData's have been duplicated. This is necessary because the classes are shared between all schedulers. Once this patch series is committed there will be an InstrItinClass for each mnemonic with minimal grouping. This does increase the size of the itinerary tables for each MIPS scheduler but we have a few options for dealing with that later. These options include reducing the number of classes once we see the best way to simplify them, or by extending tablegen to be able to compress the table by eliminating duplicates entries, etc. llvm-svn: 199391
2014-01-16 22:27:20 +08:00
def DSLL : shift_rotate_imm<"dsll", uimm6, GPR64Opnd, II_DSLL, shl, immZExt6>,
[mips] Marked up instructions added in MIPS-III and tested that IAS for -mcpu=mips[12] does not accept them Summary: This required a new instruction group representing the 32-bit subset of MIPS-III that was available in MIPS32 A small number of instructions are correctly rejected but with the wrong error message. These have been placed in a separate test for now. There's some obvious InstAlias's that ought to be marked MIPS-III but arent. This is because they are not currently tested. I intend to catch these with a final pass through the tablegen records to find tablegen records without ISA annotations. Depends on D3674 Reviewers: vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3675 llvm-svn: 208408
2014-05-09 21:02:27 +08:00
SRA_FM<0x38, 0>, ISA_MIPS3;
[mips][sched] Split IIArith in preparation for the first scheduler targeting a specific MIPS CPU. IIArith -> II_ADD, II_ADDU, II_AND, II_CL[ZO], II_DADDIU, II_DADDU, II_DROTR, II_DROTR32, II_DROTRV, II_DSLL, II_DSLL32, II_DSLLV, II_DSR[AL], II_DSR[AL]32, II_DSR[AL]V, II_DSUBU, II_LUI, II_MOV[ZFNT], II_NOR, II_OR, II_RDHWR, II_ROTR, II_ROTRV, II_SLL, II_SLLV, II_SR[AL], II_SR[AL]V, II_SUBU, II_XOR No functional change since the InstrItinData's have been duplicated. This is necessary because the classes are shared between all schedulers. Once this patch series is committed there will be an InstrItinClass for each mnemonic with minimal grouping. This does increase the size of the itinerary tables for each MIPS scheduler but we have a few options for dealing with that later. These options include reducing the number of classes once we see the best way to simplify them, or by extending tablegen to be able to compress the table by eliminating duplicates entries, etc. llvm-svn: 199391
2014-01-16 22:27:20 +08:00
def DSRL : shift_rotate_imm<"dsrl", uimm6, GPR64Opnd, II_DSRL, srl, immZExt6>,
[mips] Marked up instructions added in MIPS-III and tested that IAS for -mcpu=mips[12] does not accept them Summary: This required a new instruction group representing the 32-bit subset of MIPS-III that was available in MIPS32 A small number of instructions are correctly rejected but with the wrong error message. These have been placed in a separate test for now. There's some obvious InstAlias's that ought to be marked MIPS-III but arent. This is because they are not currently tested. I intend to catch these with a final pass through the tablegen records to find tablegen records without ISA annotations. Depends on D3674 Reviewers: vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3675 llvm-svn: 208408
2014-05-09 21:02:27 +08:00
SRA_FM<0x3a, 0>, ISA_MIPS3;
[mips][sched] Split IIArith in preparation for the first scheduler targeting a specific MIPS CPU. IIArith -> II_ADD, II_ADDU, II_AND, II_CL[ZO], II_DADDIU, II_DADDU, II_DROTR, II_DROTR32, II_DROTRV, II_DSLL, II_DSLL32, II_DSLLV, II_DSR[AL], II_DSR[AL]32, II_DSR[AL]V, II_DSUBU, II_LUI, II_MOV[ZFNT], II_NOR, II_OR, II_RDHWR, II_ROTR, II_ROTRV, II_SLL, II_SLLV, II_SR[AL], II_SR[AL]V, II_SUBU, II_XOR No functional change since the InstrItinData's have been duplicated. This is necessary because the classes are shared between all schedulers. Once this patch series is committed there will be an InstrItinClass for each mnemonic with minimal grouping. This does increase the size of the itinerary tables for each MIPS scheduler but we have a few options for dealing with that later. These options include reducing the number of classes once we see the best way to simplify them, or by extending tablegen to be able to compress the table by eliminating duplicates entries, etc. llvm-svn: 199391
2014-01-16 22:27:20 +08:00
def DSRA : shift_rotate_imm<"dsra", uimm6, GPR64Opnd, II_DSRA, sra, immZExt6>,
[mips] Marked up instructions added in MIPS-III and tested that IAS for -mcpu=mips[12] does not accept them Summary: This required a new instruction group representing the 32-bit subset of MIPS-III that was available in MIPS32 A small number of instructions are correctly rejected but with the wrong error message. These have been placed in a separate test for now. There's some obvious InstAlias's that ought to be marked MIPS-III but arent. This is because they are not currently tested. I intend to catch these with a final pass through the tablegen records to find tablegen records without ISA annotations. Depends on D3674 Reviewers: vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3675 llvm-svn: 208408
2014-05-09 21:02:27 +08:00
SRA_FM<0x3b, 0>, ISA_MIPS3;
[mips][sched] Split IIArith in preparation for the first scheduler targeting a specific MIPS CPU. IIArith -> II_ADD, II_ADDU, II_AND, II_CL[ZO], II_DADDIU, II_DADDU, II_DROTR, II_DROTR32, II_DROTRV, II_DSLL, II_DSLL32, II_DSLLV, II_DSR[AL], II_DSR[AL]32, II_DSR[AL]V, II_DSUBU, II_LUI, II_MOV[ZFNT], II_NOR, II_OR, II_RDHWR, II_ROTR, II_ROTRV, II_SLL, II_SLLV, II_SR[AL], II_SR[AL]V, II_SUBU, II_XOR No functional change since the InstrItinData's have been duplicated. This is necessary because the classes are shared between all schedulers. Once this patch series is committed there will be an InstrItinClass for each mnemonic with minimal grouping. This does increase the size of the itinerary tables for each MIPS scheduler but we have a few options for dealing with that later. These options include reducing the number of classes once we see the best way to simplify them, or by extending tablegen to be able to compress the table by eliminating duplicates entries, etc. llvm-svn: 199391
2014-01-16 22:27:20 +08:00
def DSLLV : shift_rotate_reg<"dsllv", GPR64Opnd, II_DSLLV, shl>,
[mips] Marked up instructions added in MIPS-III and tested that IAS for -mcpu=mips[12] does not accept them Summary: This required a new instruction group representing the 32-bit subset of MIPS-III that was available in MIPS32 A small number of instructions are correctly rejected but with the wrong error message. These have been placed in a separate test for now. There's some obvious InstAlias's that ought to be marked MIPS-III but arent. This is because they are not currently tested. I intend to catch these with a final pass through the tablegen records to find tablegen records without ISA annotations. Depends on D3674 Reviewers: vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3675 llvm-svn: 208408
2014-05-09 21:02:27 +08:00
SRLV_FM<0x14, 0>, ISA_MIPS3;
[mips][sched] Split IIArith in preparation for the first scheduler targeting a specific MIPS CPU. IIArith -> II_ADD, II_ADDU, II_AND, II_CL[ZO], II_DADDIU, II_DADDU, II_DROTR, II_DROTR32, II_DROTRV, II_DSLL, II_DSLL32, II_DSLLV, II_DSR[AL], II_DSR[AL]32, II_DSR[AL]V, II_DSUBU, II_LUI, II_MOV[ZFNT], II_NOR, II_OR, II_RDHWR, II_ROTR, II_ROTRV, II_SLL, II_SLLV, II_SR[AL], II_SR[AL]V, II_SUBU, II_XOR No functional change since the InstrItinData's have been duplicated. This is necessary because the classes are shared between all schedulers. Once this patch series is committed there will be an InstrItinClass for each mnemonic with minimal grouping. This does increase the size of the itinerary tables for each MIPS scheduler but we have a few options for dealing with that later. These options include reducing the number of classes once we see the best way to simplify them, or by extending tablegen to be able to compress the table by eliminating duplicates entries, etc. llvm-svn: 199391
2014-01-16 22:27:20 +08:00
def DSRLV : shift_rotate_reg<"dsrlv", GPR64Opnd, II_DSRLV, srl>,
[mips] Marked up instructions added in MIPS-III and tested that IAS for -mcpu=mips[12] does not accept them Summary: This required a new instruction group representing the 32-bit subset of MIPS-III that was available in MIPS32 A small number of instructions are correctly rejected but with the wrong error message. These have been placed in a separate test for now. There's some obvious InstAlias's that ought to be marked MIPS-III but arent. This is because they are not currently tested. I intend to catch these with a final pass through the tablegen records to find tablegen records without ISA annotations. Depends on D3674 Reviewers: vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3675 llvm-svn: 208408
2014-05-09 21:02:27 +08:00
SRLV_FM<0x16, 0>, ISA_MIPS3;
[mips][sched] Split IIArith in preparation for the first scheduler targeting a specific MIPS CPU. IIArith -> II_ADD, II_ADDU, II_AND, II_CL[ZO], II_DADDIU, II_DADDU, II_DROTR, II_DROTR32, II_DROTRV, II_DSLL, II_DSLL32, II_DSLLV, II_DSR[AL], II_DSR[AL]32, II_DSR[AL]V, II_DSUBU, II_LUI, II_MOV[ZFNT], II_NOR, II_OR, II_RDHWR, II_ROTR, II_ROTRV, II_SLL, II_SLLV, II_SR[AL], II_SR[AL]V, II_SUBU, II_XOR No functional change since the InstrItinData's have been duplicated. This is necessary because the classes are shared between all schedulers. Once this patch series is committed there will be an InstrItinClass for each mnemonic with minimal grouping. This does increase the size of the itinerary tables for each MIPS scheduler but we have a few options for dealing with that later. These options include reducing the number of classes once we see the best way to simplify them, or by extending tablegen to be able to compress the table by eliminating duplicates entries, etc. llvm-svn: 199391
2014-01-16 22:27:20 +08:00
def DSRAV : shift_rotate_reg<"dsrav", GPR64Opnd, II_DSRAV, sra>,
[mips] Marked up instructions added in MIPS-III and tested that IAS for -mcpu=mips[12] does not accept them Summary: This required a new instruction group representing the 32-bit subset of MIPS-III that was available in MIPS32 A small number of instructions are correctly rejected but with the wrong error message. These have been placed in a separate test for now. There's some obvious InstAlias's that ought to be marked MIPS-III but arent. This is because they are not currently tested. I intend to catch these with a final pass through the tablegen records to find tablegen records without ISA annotations. Depends on D3674 Reviewers: vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3675 llvm-svn: 208408
2014-05-09 21:02:27 +08:00
SRLV_FM<0x17, 0>, ISA_MIPS3;
[mips][sched] Split IIArith in preparation for the first scheduler targeting a specific MIPS CPU. IIArith -> II_ADD, II_ADDU, II_AND, II_CL[ZO], II_DADDIU, II_DADDU, II_DROTR, II_DROTR32, II_DROTRV, II_DSLL, II_DSLL32, II_DSLLV, II_DSR[AL], II_DSR[AL]32, II_DSR[AL]V, II_DSUBU, II_LUI, II_MOV[ZFNT], II_NOR, II_OR, II_RDHWR, II_ROTR, II_ROTRV, II_SLL, II_SLLV, II_SR[AL], II_SR[AL]V, II_SUBU, II_XOR No functional change since the InstrItinData's have been duplicated. This is necessary because the classes are shared between all schedulers. Once this patch series is committed there will be an InstrItinClass for each mnemonic with minimal grouping. This does increase the size of the itinerary tables for each MIPS scheduler but we have a few options for dealing with that later. These options include reducing the number of classes once we see the best way to simplify them, or by extending tablegen to be able to compress the table by eliminating duplicates entries, etc. llvm-svn: 199391
2014-01-16 22:27:20 +08:00
def DSLL32 : shift_rotate_imm<"dsll32", uimm5, GPR64Opnd, II_DSLL32>,
[mips] Marked up instructions added in MIPS-III and tested that IAS for -mcpu=mips[12] does not accept them Summary: This required a new instruction group representing the 32-bit subset of MIPS-III that was available in MIPS32 A small number of instructions are correctly rejected but with the wrong error message. These have been placed in a separate test for now. There's some obvious InstAlias's that ought to be marked MIPS-III but arent. This is because they are not currently tested. I intend to catch these with a final pass through the tablegen records to find tablegen records without ISA annotations. Depends on D3674 Reviewers: vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3675 llvm-svn: 208408
2014-05-09 21:02:27 +08:00
SRA_FM<0x3c, 0>, ISA_MIPS3;
[mips][sched] Split IIArith in preparation for the first scheduler targeting a specific MIPS CPU. IIArith -> II_ADD, II_ADDU, II_AND, II_CL[ZO], II_DADDIU, II_DADDU, II_DROTR, II_DROTR32, II_DROTRV, II_DSLL, II_DSLL32, II_DSLLV, II_DSR[AL], II_DSR[AL]32, II_DSR[AL]V, II_DSUBU, II_LUI, II_MOV[ZFNT], II_NOR, II_OR, II_RDHWR, II_ROTR, II_ROTRV, II_SLL, II_SLLV, II_SR[AL], II_SR[AL]V, II_SUBU, II_XOR No functional change since the InstrItinData's have been duplicated. This is necessary because the classes are shared between all schedulers. Once this patch series is committed there will be an InstrItinClass for each mnemonic with minimal grouping. This does increase the size of the itinerary tables for each MIPS scheduler but we have a few options for dealing with that later. These options include reducing the number of classes once we see the best way to simplify them, or by extending tablegen to be able to compress the table by eliminating duplicates entries, etc. llvm-svn: 199391
2014-01-16 22:27:20 +08:00
def DSRL32 : shift_rotate_imm<"dsrl32", uimm5, GPR64Opnd, II_DSRL32>,
[mips] Marked up instructions added in MIPS-III and tested that IAS for -mcpu=mips[12] does not accept them Summary: This required a new instruction group representing the 32-bit subset of MIPS-III that was available in MIPS32 A small number of instructions are correctly rejected but with the wrong error message. These have been placed in a separate test for now. There's some obvious InstAlias's that ought to be marked MIPS-III but arent. This is because they are not currently tested. I intend to catch these with a final pass through the tablegen records to find tablegen records without ISA annotations. Depends on D3674 Reviewers: vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3675 llvm-svn: 208408
2014-05-09 21:02:27 +08:00
SRA_FM<0x3e, 0>, ISA_MIPS3;
[mips][sched] Split IIArith in preparation for the first scheduler targeting a specific MIPS CPU. IIArith -> II_ADD, II_ADDU, II_AND, II_CL[ZO], II_DADDIU, II_DADDU, II_DROTR, II_DROTR32, II_DROTRV, II_DSLL, II_DSLL32, II_DSLLV, II_DSR[AL], II_DSR[AL]32, II_DSR[AL]V, II_DSUBU, II_LUI, II_MOV[ZFNT], II_NOR, II_OR, II_RDHWR, II_ROTR, II_ROTRV, II_SLL, II_SLLV, II_SR[AL], II_SR[AL]V, II_SUBU, II_XOR No functional change since the InstrItinData's have been duplicated. This is necessary because the classes are shared between all schedulers. Once this patch series is committed there will be an InstrItinClass for each mnemonic with minimal grouping. This does increase the size of the itinerary tables for each MIPS scheduler but we have a few options for dealing with that later. These options include reducing the number of classes once we see the best way to simplify them, or by extending tablegen to be able to compress the table by eliminating duplicates entries, etc. llvm-svn: 199391
2014-01-16 22:27:20 +08:00
def DSRA32 : shift_rotate_imm<"dsra32", uimm5, GPR64Opnd, II_DSRA32>,
[mips] Marked up instructions added in MIPS-III and tested that IAS for -mcpu=mips[12] does not accept them Summary: This required a new instruction group representing the 32-bit subset of MIPS-III that was available in MIPS32 A small number of instructions are correctly rejected but with the wrong error message. These have been placed in a separate test for now. There's some obvious InstAlias's that ought to be marked MIPS-III but arent. This is because they are not currently tested. I intend to catch these with a final pass through the tablegen records to find tablegen records without ISA annotations. Depends on D3674 Reviewers: vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3675 llvm-svn: 208408
2014-05-09 21:02:27 +08:00
SRA_FM<0x3f, 0>, ISA_MIPS3;
[mips] Mark instructions defined in Mips64InstrInfo.td that are duplicates of instructions defined in MipsInstrInfo.td as codegen-only instructions. llvm-svn: 187828
2013-08-07 07:01:10 +08:00
Add definitions of Mips64 rotate instructions. llvm-svn: 140870
2011-10-01 02:51:46 +08:00
// Rotate Instructions
[mips] Add ISA_<name> adverbs and start using them instead of AdditionalPredicates overrides Summary: One small functional change. The recently added PAUSE instruction now has the HasStdEnc predicate which was accidentally removed by a Requires<>. Depends on D3640 Reviewers: vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3641 llvm-svn: 208209
2014-05-07 21:57:22 +08:00
def DROTR : shift_rotate_imm<"drotr", uimm6, GPR64Opnd, II_DROTR, rotr,
immZExt6>,
SRA_FM<0x3a, 1>, ISA_MIPS64R2;
def DROTRV : shift_rotate_reg<"drotrv", GPR64Opnd, II_DROTRV, rotr>,
SRLV_FM<0x16, 1>, ISA_MIPS64R2;
def DROTR32 : shift_rotate_imm<"drotr32", uimm5, GPR64Opnd, II_DROTR32>,
SRA_FM<0x3e, 1>, ISA_MIPS64R2;
Add definitions of Mips64 rotate instructions. llvm-svn: 140870
2011-10-01 02:51:46 +08:00
Add definitions of 64-bit loads and stores. Add a patterns for unaligned zextloadi32 for which there is no corresponding pseudo or real instruction. llvm-svn: 141608
2011-10-11 08:27:28 +08:00
/// Load and Store Instructions
remove blanks, and some code format llvm-svn: 151625
2012-02-28 15:46:26 +08:00
/// aligned
[mips] Mark instructions defined in Mips64InstrInfo.td that are duplicates of instructions defined in MipsInstrInfo.td as codegen-only instructions. llvm-svn: 187828
2013-08-07 07:01:10 +08:00
let isCodeGenOnly = 1 in {
[mips][sched] Split IILoad into II_L[BHWD], II_L[BHW]U, II_L[WD][LR], and II_RESTORE No functional change since the InstrItinData's have been duplicated. llvm-svn: 199749
2014-01-21 23:21:14 +08:00
def LB64 : Load<"lb", GPR64Opnd, sextloadi8, II_LB>, LW_FM<0x20>;
def LBu64 : Load<"lbu", GPR64Opnd, zextloadi8, II_LBU>, LW_FM<0x24>;
def LH64 : Load<"lh", GPR64Opnd, sextloadi16, II_LH>, LW_FM<0x21>;
def LHu64 : Load<"lhu", GPR64Opnd, zextloadi16, II_LHU>, LW_FM<0x25>;
def LW64 : Load<"lw", GPR64Opnd, sextloadi32, II_LW>, LW_FM<0x23>;
[mips][sched] Split IIStore into II_S[BHWD], II_S[WD][LR], and II_SAVE No functional change since the InstrItinData's have been duplicated. llvm-svn: 199876
2014-01-23 18:31:31 +08:00
def SB64 : Store<"sb", GPR64Opnd, truncstorei8, II_SB>, LW_FM<0x28>;
def SH64 : Store<"sh", GPR64Opnd, truncstorei16, II_SH>, LW_FM<0x29>;
def SW64 : Store<"sw", GPR64Opnd, truncstorei32, II_SW>, LW_FM<0x2b>;
[mips] Mark instructions defined in Mips64InstrInfo.td that are duplicates of instructions defined in MipsInstrInfo.td as codegen-only instructions. llvm-svn: 187828
2013-08-07 07:01:10 +08:00
}
[mips] Marked up instructions added in MIPS-III and tested that IAS for -mcpu=mips[12] does not accept them Summary: This required a new instruction group representing the 32-bit subset of MIPS-III that was available in MIPS32 A small number of instructions are correctly rejected but with the wrong error message. These have been placed in a separate test for now. There's some obvious InstAlias's that ought to be marked MIPS-III but arent. This is because they are not currently tested. I intend to catch these with a final pass through the tablegen records to find tablegen records without ISA annotations. Depends on D3674 Reviewers: vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3675 llvm-svn: 208408
2014-05-09 21:02:27 +08:00
def LWu : Load<"lwu", GPR64Opnd, zextloadi32, II_LWU>, LW_FM<0x27>, ISA_MIPS3;
def LD : Load<"ld", GPR64Opnd, load, II_LD>, LW_FM<0x37>, ISA_MIPS3;
def SD : Store<"sd", GPR64Opnd, store, II_SD>, LW_FM<0x3f>, ISA_MIPS3;
Add definitions of 64-bit loads and stores. Add a patterns for unaligned zextloadi32 for which there is no corresponding pseudo or real instruction. llvm-svn: 141608
2011-10-11 08:27:28 +08:00
Add definitions of 32/64-bit unaligned load/store instructions for Mips. llvm-svn: 157865
2012-06-02 08:04:19 +08:00
/// load/store left/right
[mips] Mark instructions defined in Mips64InstrInfo.td that are duplicates of instructions defined in MipsInstrInfo.td as codegen-only instructions. llvm-svn: 187828
2013-08-07 07:01:10 +08:00
let isCodeGenOnly = 1 in {
[mips][sched] Split IILoad into II_L[BHWD], II_L[BHW]U, II_L[WD][LR], and II_RESTORE No functional change since the InstrItinData's have been duplicated. llvm-svn: 199749
2014-01-21 23:21:14 +08:00
def LWL64 : LoadLeftRight<"lwl", MipsLWL, GPR64Opnd, II_LWL>, LW_FM<0x22>;
def LWR64 : LoadLeftRight<"lwr", MipsLWR, GPR64Opnd, II_LWR>, LW_FM<0x26>;
[mips][sched] Split IIStore into II_S[BHWD], II_S[WD][LR], and II_SAVE No functional change since the InstrItinData's have been duplicated. llvm-svn: 199876
2014-01-23 18:31:31 +08:00
def SWL64 : StoreLeftRight<"swl", MipsSWL, GPR64Opnd, II_SWL>, LW_FM<0x2a>;
def SWR64 : StoreLeftRight<"swr", MipsSWR, GPR64Opnd, II_SWR>, LW_FM<0x2e>;
[mips] Mark instructions defined in Mips64InstrInfo.td that are duplicates of instructions defined in MipsInstrInfo.td as codegen-only instructions. llvm-svn: 187828
2013-08-07 07:01:10 +08:00
}
This patch tackles the problem of parsing Mips register names in the standalone assembler llvm-mc. Registers such as $A1 can represent either a 32 or 64 bit register based on the instruction using it. In addition, based on the abi, $T0 can represent different 32 bit registers. The problem is resolved by the Mips specific AsmParser td definitions changing to work together. Many cases of RegisterClass parameters are now RegisterOperand. Contributer: Vladimir Medic llvm-svn: 172284
2013-01-12 09:03:14 +08:00
[mips] Marked up instructions added in MIPS-III and tested that IAS for -mcpu=mips[12] does not accept them Summary: This required a new instruction group representing the 32-bit subset of MIPS-III that was available in MIPS32 A small number of instructions are correctly rejected but with the wrong error message. These have been placed in a separate test for now. There's some obvious InstAlias's that ought to be marked MIPS-III but arent. This is because they are not currently tested. I intend to catch these with a final pass through the tablegen records to find tablegen records without ISA annotations. Depends on D3674 Reviewers: vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3675 llvm-svn: 208408
2014-05-09 21:02:27 +08:00
def LDL : LoadLeftRight<"ldl", MipsLDL, GPR64Opnd, II_LDL>, LW_FM<0x1a>,
[mips][mips64r6] [ls][dw][lr] are not available in MIPS32r6/MIPS64r6 Summary: Instead the system is required to provide some means of handling unaligned load/store without special instructions. Options include full hardware support, full trap-and-emulate, and hybrids such as hardware support within a cache line and trap-and-emulate for multi-line accesses. MipsSETargetLowering::allowsUnalignedMemoryAccesses() has been configured to assume that unaligned accesses are 'fast' on the basis that I expect few hardware implementations will opt for pure-software handling of unaligned accesses. The ones that do handle it purely in software can override this. mips64-load-store-left-right.ll has been merged into load-store-left-right.ll The stricter testing revealed a Bits!=Bytes bug in passByValArg(). This has been fixed and the variables renamed to clarify the units they hold. Reviewers: zoran.jovanovic, jkolek, vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3872 llvm-svn: 209512
2014-05-23 21:18:02 +08:00
ISA_MIPS3_NOT_32R6_64R6;
[mips] Marked up instructions added in MIPS-III and tested that IAS for -mcpu=mips[12] does not accept them Summary: This required a new instruction group representing the 32-bit subset of MIPS-III that was available in MIPS32 A small number of instructions are correctly rejected but with the wrong error message. These have been placed in a separate test for now. There's some obvious InstAlias's that ought to be marked MIPS-III but arent. This is because they are not currently tested. I intend to catch these with a final pass through the tablegen records to find tablegen records without ISA annotations. Depends on D3674 Reviewers: vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3675 llvm-svn: 208408
2014-05-09 21:02:27 +08:00
def LDR : LoadLeftRight<"ldr", MipsLDR, GPR64Opnd, II_LDR>, LW_FM<0x1b>,
[mips][mips64r6] [ls][dw][lr] are not available in MIPS32r6/MIPS64r6 Summary: Instead the system is required to provide some means of handling unaligned load/store without special instructions. Options include full hardware support, full trap-and-emulate, and hybrids such as hardware support within a cache line and trap-and-emulate for multi-line accesses. MipsSETargetLowering::allowsUnalignedMemoryAccesses() has been configured to assume that unaligned accesses are 'fast' on the basis that I expect few hardware implementations will opt for pure-software handling of unaligned accesses. The ones that do handle it purely in software can override this. mips64-load-store-left-right.ll has been merged into load-store-left-right.ll The stricter testing revealed a Bits!=Bytes bug in passByValArg(). This has been fixed and the variables renamed to clarify the units they hold. Reviewers: zoran.jovanovic, jkolek, vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3872 llvm-svn: 209512
2014-05-23 21:18:02 +08:00
ISA_MIPS3_NOT_32R6_64R6;
[mips] Marked up instructions added in MIPS-III and tested that IAS for -mcpu=mips[12] does not accept them Summary: This required a new instruction group representing the 32-bit subset of MIPS-III that was available in MIPS32 A small number of instructions are correctly rejected but with the wrong error message. These have been placed in a separate test for now. There's some obvious InstAlias's that ought to be marked MIPS-III but arent. This is because they are not currently tested. I intend to catch these with a final pass through the tablegen records to find tablegen records without ISA annotations. Depends on D3674 Reviewers: vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3675 llvm-svn: 208408
2014-05-09 21:02:27 +08:00
def SDL : StoreLeftRight<"sdl", MipsSDL, GPR64Opnd, II_SDL>, LW_FM<0x2c>,
[mips][mips64r6] [ls][dw][lr] are not available in MIPS32r6/MIPS64r6 Summary: Instead the system is required to provide some means of handling unaligned load/store without special instructions. Options include full hardware support, full trap-and-emulate, and hybrids such as hardware support within a cache line and trap-and-emulate for multi-line accesses. MipsSETargetLowering::allowsUnalignedMemoryAccesses() has been configured to assume that unaligned accesses are 'fast' on the basis that I expect few hardware implementations will opt for pure-software handling of unaligned accesses. The ones that do handle it purely in software can override this. mips64-load-store-left-right.ll has been merged into load-store-left-right.ll The stricter testing revealed a Bits!=Bytes bug in passByValArg(). This has been fixed and the variables renamed to clarify the units they hold. Reviewers: zoran.jovanovic, jkolek, vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3872 llvm-svn: 209512
2014-05-23 21:18:02 +08:00
ISA_MIPS3_NOT_32R6_64R6;
[mips] Marked up instructions added in MIPS-III and tested that IAS for -mcpu=mips[12] does not accept them Summary: This required a new instruction group representing the 32-bit subset of MIPS-III that was available in MIPS32 A small number of instructions are correctly rejected but with the wrong error message. These have been placed in a separate test for now. There's some obvious InstAlias's that ought to be marked MIPS-III but arent. This is because they are not currently tested. I intend to catch these with a final pass through the tablegen records to find tablegen records without ISA annotations. Depends on D3674 Reviewers: vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3675 llvm-svn: 208408
2014-05-09 21:02:27 +08:00
def SDR : StoreLeftRight<"sdr", MipsSDR, GPR64Opnd, II_SDR>, LW_FM<0x2d>,
[mips][mips64r6] [ls][dw][lr] are not available in MIPS32r6/MIPS64r6 Summary: Instead the system is required to provide some means of handling unaligned load/store without special instructions. Options include full hardware support, full trap-and-emulate, and hybrids such as hardware support within a cache line and trap-and-emulate for multi-line accesses. MipsSETargetLowering::allowsUnalignedMemoryAccesses() has been configured to assume that unaligned accesses are 'fast' on the basis that I expect few hardware implementations will opt for pure-software handling of unaligned accesses. The ones that do handle it purely in software can override this. mips64-load-store-left-right.ll has been merged into load-store-left-right.ll The stricter testing revealed a Bits!=Bytes bug in passByValArg(). This has been fixed and the variables renamed to clarify the units they hold. Reviewers: zoran.jovanovic, jkolek, vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3872 llvm-svn: 209512
2014-05-23 21:18:02 +08:00
ISA_MIPS3_NOT_32R6_64R6;
Add definitions of 32/64-bit unaligned load/store instructions for Mips. llvm-svn: 157865
2012-06-02 08:04:19 +08:00
64-bit atomic instructions. llvm-svn: 144372
2011-11-11 12:14:30 +08:00
/// Load-linked, Store-conditional
[mips] Marked up instructions added in MIPS-III and tested that IAS for -mcpu=mips[12] does not accept them Summary: This required a new instruction group representing the 32-bit subset of MIPS-III that was available in MIPS32 A small number of instructions are correctly rejected but with the wrong error message. These have been placed in a separate test for now. There's some obvious InstAlias's that ought to be marked MIPS-III but arent. This is because they are not currently tested. I intend to catch these with a final pass through the tablegen records to find tablegen records without ISA annotations. Depends on D3674 Reviewers: vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3675 llvm-svn: 208408
2014-05-09 21:02:27 +08:00
def LLD : LLBase<"lld", GPR64Opnd>, LW_FM<0x34>, ISA_MIPS3;
def SCD : SCBase<"scd", GPR64Opnd>, LW_FM<0x3c>, ISA_MIPS3;
64-bit atomic instructions. llvm-svn: 144372
2011-11-11 12:14:30 +08:00
Add support for conditional branch instructions with 64-bit register operands. llvm-svn: 141694
2011-10-12 02:49:17 +08:00
/// Jump and Branch Instructions
[mips] Mark instructions defined in Mips64InstrInfo.td that are duplicates of instructions defined in MipsInstrInfo.td as codegen-only instructions. llvm-svn: 187828
2013-08-07 07:01:10 +08:00
let isCodeGenOnly = 1 in {
Support for microMIPS jump instructions llvm-svn: 193623
2013-10-30 00:38:59 +08:00
def JR64 : IndirectBranch<"jr", GPR64Opnd>, MTLO_FM<8>;
Support for microMIPS branch instructions. llvm-svn: 193992
2013-11-04 22:53:22 +08:00
def BEQ64 : CBranch<"beq", brtarget, seteq, GPR64Opnd>, BEQ_FM<4>;
def BNE64 : CBranch<"bne", brtarget, setne, GPR64Opnd>, BEQ_FM<5>;
def BGEZ64 : CBranchZero<"bgez", brtarget, setge, GPR64Opnd>, BGEZ_FM<1, 1>;
def BGTZ64 : CBranchZero<"bgtz", brtarget, setgt, GPR64Opnd>, BGEZ_FM<7, 0>;
def BLEZ64 : CBranchZero<"blez", brtarget, setle, GPR64Opnd>, BGEZ_FM<6, 0>;
def BLTZ64 : CBranchZero<"bltz", brtarget, setlt, GPR64Opnd>, BGEZ_FM<1, 0>;
[mips] Rename register classes CPURegs and CPU64Regs. llvm-svn: 187832
2013-08-07 07:08:38 +08:00
def JALR64 : JumpLinkReg<"jalr", GPR64Opnd>, JALR_FM;
def JALR64Pseudo : JumpLinkRegPseudo<GPR64Opnd, JALR, RA, GPR32Opnd>;
[mips] Redefine TAILCALL as a pseudo instruction. No functionality change. llvm-svn: 195896
2013-11-28 07:58:32 +08:00
def TAILCALL64_R : TailCallReg<GPR64Opnd, JR, GPR32Opnd>;
[mips] Mark instructions defined in Mips64InstrInfo.td that are duplicates of instructions defined in MipsInstrInfo.td as codegen-only instructions. llvm-svn: 187828
2013-08-07 07:01:10 +08:00
}
- Define base classes for Jump-and-link instructions and make 32-bit and 64-bit versions derive from them. - JALR64 is not needed since N64 does not emit jal. - Add template parameter to BranchLink that sets the rt field. - Fix the set of temporary registers for O32 and N64. llvm-svn: 147518
2012-01-04 11:02:47 +08:00
Add support for 64-bit integer multiply instructions. llvm-svn: 141017
2011-10-04 04:01:11 +08:00
/// Multiply and Divide Instructions.
[mips][sched] Split IIImul and IIImult into subclasses. IIImul -> II_MUL IIImult -> II_MULT, II_MULTU, II_MADD, II_MADDU, II_MSUB, II_MSUBU, II_DMULT, II_DMULTU No functional change since the InstrItinData's have been duplicated. llvm-svn: 199495
2014-01-17 22:32:41 +08:00
def DMULT : Mult<"dmult", II_DMULT, GPR64Opnd, [HI0_64, LO0_64]>,
[mips][mips64r6] Replace m[tf]hi, m[tf]lo, mult, multu, dmult, dmultu, div, ddiv, divu, ddivu for MIPS32r6/MIPS64. Summary: The accumulator-based (HI/LO) multiplies and divides from earlier ISA's have been removed and replaced with GPR-based equivalents. For example: div $1, $2 mflo $3 is now: div $3, $1, $2 This patch disables the accumulator-based multiplies and divides for MIPS32r6/MIPS64r6 and uses the GPR-based equivalents instead. Renamed expandPseudoDiv to insertDivByZeroTrap to better describe the behaviour of the function. MipsDelaySlotFiller now invalidates the liveness information when moving instructions to the delay slot. Without this, divrem.ll will abort since %GP ends up used before it is defined. Reviewers: vmedic, zoran.jovanovic, jkolek Reviewed By: jkolek Differential Revision: http://reviews.llvm.org/D3896 llvm-svn: 210760
2014-06-12 18:44:10 +08:00
MULT_FM<0, 0x1c>, ISA_MIPS3_NOT_32R6_64R6;
[mips][sched] Split IIImul and IIImult into subclasses. IIImul -> II_MUL IIImult -> II_MULT, II_MULTU, II_MADD, II_MADDU, II_MSUB, II_MSUBU, II_DMULT, II_DMULTU No functional change since the InstrItinData's have been duplicated. llvm-svn: 199495
2014-01-17 22:32:41 +08:00
def DMULTu : Mult<"dmultu", II_DMULTU, GPR64Opnd, [HI0_64, LO0_64]>,
[mips][mips64r6] Replace m[tf]hi, m[tf]lo, mult, multu, dmult, dmultu, div, ddiv, divu, ddivu for MIPS32r6/MIPS64. Summary: The accumulator-based (HI/LO) multiplies and divides from earlier ISA's have been removed and replaced with GPR-based equivalents. For example: div $1, $2 mflo $3 is now: div $3, $1, $2 This patch disables the accumulator-based multiplies and divides for MIPS32r6/MIPS64r6 and uses the GPR-based equivalents instead. Renamed expandPseudoDiv to insertDivByZeroTrap to better describe the behaviour of the function. MipsDelaySlotFiller now invalidates the liveness information when moving instructions to the delay slot. Without this, divrem.ll will abort since %GP ends up used before it is defined. Reviewers: vmedic, zoran.jovanovic, jkolek Reviewed By: jkolek Differential Revision: http://reviews.llvm.org/D3896 llvm-svn: 210760
2014-06-12 18:44:10 +08:00
MULT_FM<0, 0x1d>, ISA_MIPS3_NOT_32R6_64R6;
[mips] Rename accumulator register classes and FP register operands. llvm-svn: 188020
2013-08-09 05:54:26 +08:00
def PseudoDMULT : MultDivPseudo<DMULT, ACC128, GPR64Opnd, MipsMult,
[mips][mips64r6] Replace m[tf]hi, m[tf]lo, mult, multu, dmult, dmultu, div, ddiv, divu, ddivu for MIPS32r6/MIPS64. Summary: The accumulator-based (HI/LO) multiplies and divides from earlier ISA's have been removed and replaced with GPR-based equivalents. For example: div $1, $2 mflo $3 is now: div $3, $1, $2 This patch disables the accumulator-based multiplies and divides for MIPS32r6/MIPS64r6 and uses the GPR-based equivalents instead. Renamed expandPseudoDiv to insertDivByZeroTrap to better describe the behaviour of the function. MipsDelaySlotFiller now invalidates the liveness information when moving instructions to the delay slot. Without this, divrem.ll will abort since %GP ends up used before it is defined. Reviewers: vmedic, zoran.jovanovic, jkolek Reviewed By: jkolek Differential Revision: http://reviews.llvm.org/D3896 llvm-svn: 210760
2014-06-12 18:44:10 +08:00
II_DMULT>, ISA_MIPS3_NOT_32R6_64R6;
[mips] Rename accumulator register classes and FP register operands. llvm-svn: 188020
2013-08-09 05:54:26 +08:00
def PseudoDMULTu : MultDivPseudo<DMULTu, ACC128, GPR64Opnd, MipsMultu,
[mips][mips64r6] Replace m[tf]hi, m[tf]lo, mult, multu, dmult, dmultu, div, ddiv, divu, ddivu for MIPS32r6/MIPS64. Summary: The accumulator-based (HI/LO) multiplies and divides from earlier ISA's have been removed and replaced with GPR-based equivalents. For example: div $1, $2 mflo $3 is now: div $3, $1, $2 This patch disables the accumulator-based multiplies and divides for MIPS32r6/MIPS64r6 and uses the GPR-based equivalents instead. Renamed expandPseudoDiv to insertDivByZeroTrap to better describe the behaviour of the function. MipsDelaySlotFiller now invalidates the liveness information when moving instructions to the delay slot. Without this, divrem.ll will abort since %GP ends up used before it is defined. Reviewers: vmedic, zoran.jovanovic, jkolek Reviewed By: jkolek Differential Revision: http://reviews.llvm.org/D3896 llvm-svn: 210760
2014-06-12 18:44:10 +08:00
II_DMULTU>, ISA_MIPS3_NOT_32R6_64R6;
[mips] Split IIIdiv int II_DIV, II_DIVU, II_DDIV, and II_DDIVU No functional change since the InstrItinData's were duplicated llvm-svn: 199497
2014-01-17 22:48:06 +08:00
def DSDIV : Div<"ddiv", II_DDIV, GPR64Opnd, [HI0_64, LO0_64]>,
[mips][mips64r6] Replace m[tf]hi, m[tf]lo, mult, multu, dmult, dmultu, div, ddiv, divu, ddivu for MIPS32r6/MIPS64. Summary: The accumulator-based (HI/LO) multiplies and divides from earlier ISA's have been removed and replaced with GPR-based equivalents. For example: div $1, $2 mflo $3 is now: div $3, $1, $2 This patch disables the accumulator-based multiplies and divides for MIPS32r6/MIPS64r6 and uses the GPR-based equivalents instead. Renamed expandPseudoDiv to insertDivByZeroTrap to better describe the behaviour of the function. MipsDelaySlotFiller now invalidates the liveness information when moving instructions to the delay slot. Without this, divrem.ll will abort since %GP ends up used before it is defined. Reviewers: vmedic, zoran.jovanovic, jkolek Reviewed By: jkolek Differential Revision: http://reviews.llvm.org/D3896 llvm-svn: 210760
2014-06-12 18:44:10 +08:00
MULT_FM<0, 0x1e>, ISA_MIPS3_NOT_32R6_64R6;
[mips] Split IIIdiv int II_DIV, II_DIVU, II_DDIV, and II_DDIVU No functional change since the InstrItinData's were duplicated llvm-svn: 199497
2014-01-17 22:48:06 +08:00
def DUDIV : Div<"ddivu", II_DDIVU, GPR64Opnd, [HI0_64, LO0_64]>,
[mips][mips64r6] Replace m[tf]hi, m[tf]lo, mult, multu, dmult, dmultu, div, ddiv, divu, ddivu for MIPS32r6/MIPS64. Summary: The accumulator-based (HI/LO) multiplies and divides from earlier ISA's have been removed and replaced with GPR-based equivalents. For example: div $1, $2 mflo $3 is now: div $3, $1, $2 This patch disables the accumulator-based multiplies and divides for MIPS32r6/MIPS64r6 and uses the GPR-based equivalents instead. Renamed expandPseudoDiv to insertDivByZeroTrap to better describe the behaviour of the function. MipsDelaySlotFiller now invalidates the liveness information when moving instructions to the delay slot. Without this, divrem.ll will abort since %GP ends up used before it is defined. Reviewers: vmedic, zoran.jovanovic, jkolek Reviewed By: jkolek Differential Revision: http://reviews.llvm.org/D3896 llvm-svn: 210760
2014-06-12 18:44:10 +08:00
MULT_FM<0, 0x1f>, ISA_MIPS3_NOT_32R6_64R6;
[mips] Rename accumulator register classes and FP register operands. llvm-svn: 188020
2013-08-09 05:54:26 +08:00
def PseudoDSDIV : MultDivPseudo<DSDIV, ACC128, GPR64Opnd, MipsDivRem,
[mips][mips64r6] Replace m[tf]hi, m[tf]lo, mult, multu, dmult, dmultu, div, ddiv, divu, ddivu for MIPS32r6/MIPS64. Summary: The accumulator-based (HI/LO) multiplies and divides from earlier ISA's have been removed and replaced with GPR-based equivalents. For example: div $1, $2 mflo $3 is now: div $3, $1, $2 This patch disables the accumulator-based multiplies and divides for MIPS32r6/MIPS64r6 and uses the GPR-based equivalents instead. Renamed expandPseudoDiv to insertDivByZeroTrap to better describe the behaviour of the function. MipsDelaySlotFiller now invalidates the liveness information when moving instructions to the delay slot. Without this, divrem.ll will abort since %GP ends up used before it is defined. Reviewers: vmedic, zoran.jovanovic, jkolek Reviewed By: jkolek Differential Revision: http://reviews.llvm.org/D3896 llvm-svn: 210760
2014-06-12 18:44:10 +08:00
II_DDIV, 0, 1, 1>, ISA_MIPS3_NOT_32R6_64R6;
[mips] Rename accumulator register classes and FP register operands. llvm-svn: 188020
2013-08-09 05:54:26 +08:00
def PseudoDUDIV : MultDivPseudo<DUDIV, ACC128, GPR64Opnd, MipsDivRemU,
[mips][mips64r6] Replace m[tf]hi, m[tf]lo, mult, multu, dmult, dmultu, div, ddiv, divu, ddivu for MIPS32r6/MIPS64. Summary: The accumulator-based (HI/LO) multiplies and divides from earlier ISA's have been removed and replaced with GPR-based equivalents. For example: div $1, $2 mflo $3 is now: div $3, $1, $2 This patch disables the accumulator-based multiplies and divides for MIPS32r6/MIPS64r6 and uses the GPR-based equivalents instead. Renamed expandPseudoDiv to insertDivByZeroTrap to better describe the behaviour of the function. MipsDelaySlotFiller now invalidates the liveness information when moving instructions to the delay slot. Without this, divrem.ll will abort since %GP ends up used before it is defined. Reviewers: vmedic, zoran.jovanovic, jkolek Reviewed By: jkolek Differential Revision: http://reviews.llvm.org/D3896 llvm-svn: 210760
2014-06-12 18:44:10 +08:00
II_DDIVU, 0, 1, 1>, ISA_MIPS3_NOT_32R6_64R6;
Add support for 64-bit integer multiply instructions. llvm-svn: 141017
2011-10-04 04:01:11 +08:00
[mips] Mark instructions defined in Mips64InstrInfo.td that are duplicates of instructions defined in MipsInstrInfo.td as codegen-only instructions. llvm-svn: 187828
2013-08-07 07:01:10 +08:00
let isCodeGenOnly = 1 in {
[mips][mips64r6] Replace m[tf]hi, m[tf]lo, mult, multu, dmult, dmultu, div, ddiv, divu, ddivu for MIPS32r6/MIPS64. Summary: The accumulator-based (HI/LO) multiplies and divides from earlier ISA's have been removed and replaced with GPR-based equivalents. For example: div $1, $2 mflo $3 is now: div $3, $1, $2 This patch disables the accumulator-based multiplies and divides for MIPS32r6/MIPS64r6 and uses the GPR-based equivalents instead. Renamed expandPseudoDiv to insertDivByZeroTrap to better describe the behaviour of the function. MipsDelaySlotFiller now invalidates the liveness information when moving instructions to the delay slot. Without this, divrem.ll will abort since %GP ends up used before it is defined. Reviewers: vmedic, zoran.jovanovic, jkolek Reviewed By: jkolek Differential Revision: http://reviews.llvm.org/D3896 llvm-svn: 210760
2014-06-12 18:44:10 +08:00
def MTHI64 : MoveToLOHI<"mthi", GPR64Opnd, [HI0_64]>, MTLO_FM<0x11>,
ISA_MIPS3_NOT_32R6_64R6;
def MTLO64 : MoveToLOHI<"mtlo", GPR64Opnd, [LO0_64]>, MTLO_FM<0x13>,
ISA_MIPS3_NOT_32R6_64R6;
def MFHI64 : MoveFromLOHI<"mfhi", GPR64Opnd, AC0_64>, MFLO_FM<0x10>,
ISA_MIPS3_NOT_32R6_64R6;
def MFLO64 : MoveFromLOHI<"mflo", GPR64Opnd, AC0_64>, MFLO_FM<0x12>,
ISA_MIPS3_NOT_32R6_64R6;
def PseudoMFHI64 : PseudoMFLOHI<GPR64, ACC128, MipsMFHI>,
ISA_MIPS3_NOT_32R6_64R6;
def PseudoMFLO64 : PseudoMFLOHI<GPR64, ACC128, MipsMFLO>,
ISA_MIPS3_NOT_32R6_64R6;
def PseudoMTLOHI64 : PseudoMTLOHI<ACC128, GPR64>, ISA_MIPS3_NOT_32R6_64R6;
Add definitions of instructions which move values between 64-bit integer registers and 64-bit HI and LO registers. Fix encoding of the 32-bit versions of the instructions. llvm-svn: 141015
2011-10-04 03:28:44 +08:00
64-bit sign extension in register instructions. llvm-svn: 148862
2012-01-25 05:41:09 +08:00
/// Sign Ext In Register Instructions.
[mips] Fold FeatureSEInReg into FeatureMips32r2 Summary: No functional change Reviewers: vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3693 llvm-svn: 208543
2014-05-12 20:28:15 +08:00
def SEB64 : SignExtInReg<"seb", i8, GPR64Opnd, II_SEB>, SEB_FM<0x10, 0x20>,
ISA_MIPS32R2;
def SEH64 : SignExtInReg<"seh", i16, GPR64Opnd, II_SEH>, SEB_FM<0x18, 0x20>,
ISA_MIPS32R2;
[mips] Mark instructions defined in Mips64InstrInfo.td that are duplicates of instructions defined in MipsInstrInfo.td as codegen-only instructions. llvm-svn: 187828
2013-08-07 07:01:10 +08:00
}
64-bit sign extension in register instructions. llvm-svn: 148862
2012-01-25 05:41:09 +08:00
Add support for 64-bit count leading ones and zeros instructions. llvm-svn: 141028
2011-10-04 05:16:50 +08:00
/// Count Leading
[mips] Fold FeatureBitCount into FeatureMips32 and FeatureMips64 Summary: DCL[ZO] are now correctly marked as being MIPS64 instructions. This has no effect on the CodeGen tests since expansion of i64 prevented their use anyway. The check for MIPS16 to prevent the use of CLZ no longer prevents DCLZ as well. This is not a functional change since DCLZ is still prohibited by being a MIPS64 instruction (MIPS16 is only compatible with MIPS32). No functional change Reviewers: vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3694 llvm-svn: 208544
2014-05-12 20:41:59 +08:00
def DCLZ : CountLeading0<"dclz", GPR64Opnd>, CLO_FM<0x24>, ISA_MIPS64;
def DCLO : CountLeading1<"dclo", GPR64Opnd>, CLO_FM<0x25>, ISA_MIPS64;
Add support for 64-bit count leading ones and zeros instructions. llvm-svn: 141028
2011-10-04 05:16:50 +08:00
Add definition of DSBH (Double Swap Bytes within Halfwords) and DSHD (Double Swap Halfwords within Doublewords). Add a pattern which replaces 64-bit bswap with a DSBH and DSHD pair. llvm-svn: 147017
2011-12-21 07:56:43 +08:00
/// Double Word Swap Bytes/HalfWords
[mips] Fold FeatureSwap into FeatureMips32r2 and FeatureMips64r2 Summary: dsbh and dshd are not available on Mips32r2. No codegen test changes required since expansion of i64 prevented the use of these instructions anyway. Depends on D3690 Reviewers: vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3692 llvm-svn: 208542
2014-05-12 20:15:41 +08:00
def DSBH : SubwordSwap<"dsbh", GPR64Opnd>, SEB_FM<2, 0x24>, ISA_MIPS64R2;
def DSHD : SubwordSwap<"dshd", GPR64Opnd>, SEB_FM<5, 0x24>, ISA_MIPS64R2;
[mips] Refactor subword-swap, EXT/INS, load-effective-address and read-hardware instructions. llvm-svn: 170956
2012-12-22 07:21:32 +08:00
[mips] Resolve register classes dynamically using ptr_rc to reduce the number of load/store instructions defined. Previously, we were defining load/store instructions for each pointer size (32 and 64-bit), but now we need just one definition. llvm-svn: 188830
2013-08-21 05:08:22 +08:00
def LEA_ADDiu64 : EffectiveAddress<"daddiu", GPR64Opnd>, LW_FM<0x19>;
Add definition of DSBH (Double Swap Bytes within Halfwords) and DSHD (Double Swap Halfwords within Doublewords). Add a pattern which replaces 64-bit bswap with a DSBH and DSHD pair. llvm-svn: 147017
2011-12-21 07:56:43 +08:00
[mips] Mark instructions defined in Mips64InstrInfo.td that are duplicates of instructions defined in MipsInstrInfo.td as codegen-only instructions. llvm-svn: 187828
2013-08-07 07:01:10 +08:00
let isCodeGenOnly = 1 in
[mips] Delete register class HWRegs64. No functionality change. llvm-svn: 188016
2013-08-09 05:37:32 +08:00
def RDHWR64 : ReadHardware<GPR64Opnd, HWRegsOpnd>, RDHWR_FM;
Modify class ReadHardware and add definition of 64-bit version of instruction RDHWR. llvm-svn: 146101
2011-12-08 07:31:26 +08:00
[mips] Use uimm5 and uimm6 instead of shamt and imm, if the immediate has to fit into a 5-bit or 6-bit field. llvm-svn: 190226
2013-09-07 08:02:02 +08:00
def DEXT : ExtBase<"dext", GPR64Opnd, uimm6, MipsExt>, EXT_FM<3>;
def DEXTU : ExtBase<"dextu", GPR64Opnd, uimm6>, EXT_FM<2>;
def DEXTM : ExtBase<"dextm", GPR64Opnd, uimm5>, EXT_FM<1>;
def DINS : InsBase<"dins", GPR64Opnd, uimm6, MipsIns>, EXT_FM<7>;
def DINSU : InsBase<"dinsu", GPR64Opnd, uimm6>, EXT_FM<6>;
def DINSM : InsBase<"dinsm", GPR64Opnd, uimm5>, EXT_FM<5>;
Add definitions of 64-bit extract and insert instrucions and make PerformANDCombine and PerformOrCombine aware of them. Test cases are included too. llvm-svn: 145853
2011-12-06 05:26:34 +08:00
The define for 64 bit sign extension neglected to initialize fields of the class that it used. The result was nonsense code. Before: 0000000000000000 <foo>: 0: 00441100 0x441100 4: 03e00008 jr ra 8: 00000000 nop After: 0000000000000000 <foo>: 0: 00041000 sll v0,a0,0x0 4: 03e00008 jr ra 8: 00000000 nop llvm-svn: 161377
2012-08-07 08:35:22 +08:00
let isCodeGenOnly = 1, rs = 0, shamt = 0 in {
[mips] Rename register classes CPURegs and CPU64Regs. llvm-svn: 187832
2013-08-07 07:08:38 +08:00
def DSLL64_32 : FR<0x00, 0x3c, (outs GPR64:$rd), (ins GPR32:$rt),
[mips][sched] Split IIArith in preparation for the first scheduler targeting a specific MIPS CPU. IIArith -> II_ADD, II_ADDU, II_AND, II_CL[ZO], II_DADDIU, II_DADDU, II_DROTR, II_DROTR32, II_DROTRV, II_DSLL, II_DSLL32, II_DSLLV, II_DSR[AL], II_DSR[AL]32, II_DSR[AL]V, II_DSUBU, II_LUI, II_MOV[ZFNT], II_NOR, II_OR, II_RDHWR, II_ROTR, II_ROTRV, II_SLL, II_SLLV, II_SR[AL], II_SR[AL]V, II_SUBU, II_XOR No functional change since the InstrItinData's have been duplicated. This is necessary because the classes are shared between all schedulers. Once this patch series is committed there will be an InstrItinClass for each mnemonic with minimal grouping. This does increase the size of the itinerary tables for each MIPS scheduler but we have a few options for dealing with that later. These options include reducing the number of classes once we see the best way to simplify them, or by extending tablegen to be able to compress the table by eliminating duplicates entries, etc. llvm-svn: 199391
2014-01-16 22:27:20 +08:00
"dsll\t$rd, $rt, 32", [], II_DSLL>;
[mips] Rename register classes CPURegs and CPU64Regs. llvm-svn: 187832
2013-08-07 07:08:38 +08:00
def SLL64_32 : FR<0x0, 0x00, (outs GPR64:$rd), (ins GPR32:$rt),
[mips][sched] Split IIArith in preparation for the first scheduler targeting a specific MIPS CPU. IIArith -> II_ADD, II_ADDU, II_AND, II_CL[ZO], II_DADDIU, II_DADDU, II_DROTR, II_DROTR32, II_DROTRV, II_DSLL, II_DSLL32, II_DSLLV, II_DSR[AL], II_DSR[AL]32, II_DSR[AL]V, II_DSUBU, II_LUI, II_MOV[ZFNT], II_NOR, II_OR, II_RDHWR, II_ROTR, II_ROTRV, II_SLL, II_SLLV, II_SR[AL], II_SR[AL]V, II_SUBU, II_XOR No functional change since the InstrItinData's have been duplicated. This is necessary because the classes are shared between all schedulers. Once this patch series is committed there will be an InstrItinClass for each mnemonic with minimal grouping. This does increase the size of the itinerary tables for each MIPS scheduler but we have a few options for dealing with that later. These options include reducing the number of classes once we see the best way to simplify them, or by extending tablegen to be able to compress the table by eliminating duplicates entries, etc. llvm-svn: 199391
2014-01-16 22:27:20 +08:00
"sll\t$rd, $rt, 0", [], II_SLL>;
[mips] Rename register classes CPURegs and CPU64Regs. llvm-svn: 187832
2013-08-07 07:08:38 +08:00
def SLL64_64 : FR<0x0, 0x00, (outs GPR64:$rd), (ins GPR64:$rt),
[mips][sched] Split IIArith in preparation for the first scheduler targeting a specific MIPS CPU. IIArith -> II_ADD, II_ADDU, II_AND, II_CL[ZO], II_DADDIU, II_DADDU, II_DROTR, II_DROTR32, II_DROTRV, II_DSLL, II_DSLL32, II_DSLLV, II_DSR[AL], II_DSR[AL]32, II_DSR[AL]V, II_DSUBU, II_LUI, II_MOV[ZFNT], II_NOR, II_OR, II_RDHWR, II_ROTR, II_ROTRV, II_SLL, II_SLLV, II_SR[AL], II_SR[AL]V, II_SUBU, II_XOR No functional change since the InstrItinData's have been duplicated. This is necessary because the classes are shared between all schedulers. Once this patch series is committed there will be an InstrItinClass for each mnemonic with minimal grouping. This does increase the size of the itinerary tables for each MIPS scheduler but we have a few options for dealing with that later. These options include reducing the number of classes once we see the best way to simplify them, or by extending tablegen to be able to compress the table by eliminating duplicates entries, etc. llvm-svn: 199391
2014-01-16 22:27:20 +08:00
"sll\t$rd, $rt, 0", [], II_SLL>;
The define for 64 bit sign extension neglected to initialize fields of the class that it used. The result was nonsense code. Before: 0000000000000000 <foo>: 0: 00441100 0x441100 4: 03e00008 jr ra 8: 00000000 nop After: 0000000000000000 <foo>: 0: 00041000 sll v0,a0,0x0 4: 03e00008 jr ra 8: 00000000 nop llvm-svn: 161377
2012-08-07 08:35:22 +08:00
}
[MIPS] Add cpu octeon and some instructions The Octeon cpu from Cavium Networks is mips64r2 based and has an extended instruction set. In order to utilize this with LLVM, a new cpu feature "octeon" and a subtarget feature "cnmips" is added. A small set of new instructions (baddu, dmul, pop, dpop, seq, sne) is also added. LLVM generates dmul, pop and dpop instructions with option -mcpu=octeon or -mattr=+cnmips. llvm-svn: 204337
2014-03-20 19:51:58 +08:00
[mips] Optimize long branch for MIPS64 by removing %higher and %highest. %higher and %highest can have non-zero values only for offsets greater than 2GB, which is highly unlikely, if not impossible when compiling a single function. This makes long branch for MIPS64 3 instructions smaller. Differential Revision: http://llvm-reviews.chandlerc.com/D3281.diff llvm-svn: 209678
2014-05-28 02:53:06 +08:00
// We need the following pseudo instruction to avoid offset calculation for
[mips] Fix MipsLongBranch pass to work when the offset from the branch to the target cannot be determined accurately. This is the case for NaCl where the sandboxing instructions are added in MC layer, after the MipsLongBranch pass. It is also the case when the code has inline assembly. Instead of calculating offset in the MipsLongBranch pass, use %hi(sym1 - sym2) and %lo(sym1 - sym2) expressions that are resolved during the fixup. This patch also deletes microMIPS test file test/CodeGen/Mips/micromips-long-branch.ll and implements microMIPS CHECKs in a much simpler way in a file test/CodeGen/Mips/longbranch.ll, together with MIPS32 and MIPS64. llvm-svn: 207656
2014-04-30 23:06:25 +08:00
// long branches. See the comment in file MipsLongBranch.cpp for detailed
// explanation.
// Expands to: daddiu $dst, $src, %PART($tgt - $baltgt)
[mips] Optimize long branch for MIPS64 by removing %higher and %highest. %higher and %highest can have non-zero values only for offsets greater than 2GB, which is highly unlikely, if not impossible when compiling a single function. This makes long branch for MIPS64 3 instructions smaller. Differential Revision: http://llvm-reviews.chandlerc.com/D3281.diff llvm-svn: 209678
2014-05-28 02:53:06 +08:00
// where %PART may be %hi or %lo, depending on the relocation kind
[mips] Fix MipsLongBranch pass to work when the offset from the branch to the target cannot be determined accurately. This is the case for NaCl where the sandboxing instructions are added in MC layer, after the MipsLongBranch pass. It is also the case when the code has inline assembly. Instead of calculating offset in the MipsLongBranch pass, use %hi(sym1 - sym2) and %lo(sym1 - sym2) expressions that are resolved during the fixup. This patch also deletes microMIPS test file test/CodeGen/Mips/micromips-long-branch.ll and implements microMIPS CHECKs in a much simpler way in a file test/CodeGen/Mips/longbranch.ll, together with MIPS32 and MIPS64. llvm-svn: 207656
2014-04-30 23:06:25 +08:00
// that $tgt is annotated with.
def LONG_BRANCH_DADDiu : PseudoSE<(outs GPR64Opnd:$dst),
(ins GPR64Opnd:$src, brtarget:$tgt, brtarget:$baltgt), []>;
[MIPS] Add cpu octeon and some instructions The Octeon cpu from Cavium Networks is mips64r2 based and has an extended instruction set. In order to utilize this with LLVM, a new cpu feature "octeon" and a subtarget feature "cnmips" is added. A small set of new instructions (baddu, dmul, pop, dpop, seq, sne) is also added. LLVM generates dmul, pop and dpop instructions with option -mcpu=octeon or -mattr=+cnmips. llvm-svn: 204337
2014-03-20 19:51:58 +08:00
// Cavium Octeon cmMIPS instructions
[mips] Split Instruction.Predicates into smaller lists and re-join them with !listconcat Summary: The overall idea is to chop the Predicates list into subsets that are usually overridden independently. This allows subclasses to partially override the predicates of their superclasses without having to re-add all the existing predicates. This patch starts the process by moving HasStdEnc into a new EncodingPredicates list and almost everything else into AdditionalPredicates. It has revealed a couple likely bugs where 'let Predicates' has removed the HasStdEnc predicate. No functional change (confirmed by diffing tablegen-erated files). Depends on D3549, D3506 Reviewers: vmedic Differential Revision: http://reviews.llvm.org/D3550 llvm-svn: 208184
2014-05-07 18:27:09 +08:00
let EncodingPredicates = []<Predicate>, // FIXME: The lack of HasStdEnc is probably a bug
AdditionalPredicates = [HasCnMips] in {
[MIPS] Add cpu octeon and some instructions The Octeon cpu from Cavium Networks is mips64r2 based and has an extended instruction set. In order to utilize this with LLVM, a new cpu feature "octeon" and a subtarget feature "cnmips" is added. A small set of new instructions (baddu, dmul, pop, dpop, seq, sne) is also added. LLVM generates dmul, pop and dpop instructions with option -mcpu=octeon or -mattr=+cnmips. llvm-svn: 204337
2014-03-20 19:51:58 +08:00
class Count1s<string opstr, RegisterOperand RO>:
InstSE<(outs RO:$rd), (ins RO:$rs), !strconcat(opstr, "\t$rd, $rs"),
[mips] Add more Octeon cnMips instructions Adds the instructions ext/ext32/cins/cins32. It also changes pop/dpop to accept the two operand version and adds a simple pattern to generate baddu. Tests for the two operand versions (including baddu/dmul/dpop/pop) and the code generation pattern for baddu are included. Reviewed by: Daniel.Sanders@imgtec.com llvm-svn: 205449
2014-04-03 02:40:43 +08:00
[(set RO:$rd, (ctpop RO:$rs))], II_POP, FrmR, opstr> {
let TwoOperandAliasConstraint = "$rd = $rs";
}
class ExtsCins<string opstr, SDPatternOperator Op = null_frag>:
InstSE<(outs GPR64Opnd:$rt), (ins GPR64Opnd:$rs, uimm5:$pos, uimm5:$lenm1),
!strconcat(opstr, " $rt, $rs, $pos, $lenm1"),
[(set GPR64Opnd:$rt, (Op GPR64Opnd:$rs, imm:$pos, imm:$lenm1))],
NoItinerary, FrmR, opstr> {
let TwoOperandAliasConstraint = "$rt = $rs";
}
[MIPS] Add cpu octeon and some instructions The Octeon cpu from Cavium Networks is mips64r2 based and has an extended instruction set. In order to utilize this with LLVM, a new cpu feature "octeon" and a subtarget feature "cnmips" is added. A small set of new instructions (baddu, dmul, pop, dpop, seq, sne) is also added. LLVM generates dmul, pop and dpop instructions with option -mcpu=octeon or -mattr=+cnmips. llvm-svn: 204337
2014-03-20 19:51:58 +08:00
class SetCC64_R<string opstr, PatFrag cond_op> :
InstSE<(outs GPR64Opnd:$rd), (ins GPR64Opnd:$rs, GPR64Opnd:$rt),
!strconcat(opstr, "\t$rd, $rs, $rt"),
[(set GPR64Opnd:$rd, (cond_op GPR64Opnd:$rs, GPR64Opnd:$rt))],
[mips] Add more Octeon cnMips instructions Adds the instructions ext/ext32/cins/cins32. It also changes pop/dpop to accept the two operand version and adds a simple pattern to generate baddu. Tests for the two operand versions (including baddu/dmul/dpop/pop) and the code generation pattern for baddu are included. Reviewed by: Daniel.Sanders@imgtec.com llvm-svn: 205449
2014-04-03 02:40:43 +08:00
II_SEQ_SNE, FrmR, opstr> {
let TwoOperandAliasConstraint = "$rd = $rs";
}
[MIPS] Add cpu octeon and some instructions The Octeon cpu from Cavium Networks is mips64r2 based and has an extended instruction set. In order to utilize this with LLVM, a new cpu feature "octeon" and a subtarget feature "cnmips" is added. A small set of new instructions (baddu, dmul, pop, dpop, seq, sne) is also added. LLVM generates dmul, pop and dpop instructions with option -mcpu=octeon or -mattr=+cnmips. llvm-svn: 204337
2014-03-20 19:51:58 +08:00
[mips] Add Octeon cnMips instructions seqi/snei and v3mulu/vmm0/vmulu. This patch adds the Octeon cnMips instructions seqi/snei and v3mulu/vmm0/vmulu. It is only for the assembler. Test case is included. Reviewed by: Daniel.Sanders@imgtec.com llvm-svn: 205631
2014-04-05 00:21:59 +08:00
class SetCC64_I<string opstr, PatFrag cond_op>:
InstSE<(outs GPR64Opnd:$rt), (ins GPR64Opnd:$rs, simm10_64:$imm10),
!strconcat(opstr, "\t$rt, $rs, $imm10"),
[(set GPR64Opnd:$rt, (cond_op GPR64Opnd:$rs, immSExt10_64:$imm10))],
II_SEQI_SNEI, FrmI, opstr> {
let TwoOperandAliasConstraint = "$rt = $rs";
}
[MIPS] Add cpu octeon and some instructions The Octeon cpu from Cavium Networks is mips64r2 based and has an extended instruction set. In order to utilize this with LLVM, a new cpu feature "octeon" and a subtarget feature "cnmips" is added. A small set of new instructions (baddu, dmul, pop, dpop, seq, sne) is also added. LLVM generates dmul, pop and dpop instructions with option -mcpu=octeon or -mattr=+cnmips. llvm-svn: 204337
2014-03-20 19:51:58 +08:00
// Unsigned Byte Add
[mips] Add more Octeon cnMips instructions Adds the instructions ext/ext32/cins/cins32. It also changes pop/dpop to accept the two operand version and adds a simple pattern to generate baddu. Tests for the two operand versions (including baddu/dmul/dpop/pop) and the code generation pattern for baddu are included. Reviewed by: Daniel.Sanders@imgtec.com llvm-svn: 205449
2014-04-03 02:40:43 +08:00
let Pattern = [(set GPR64Opnd:$rd,
(and (add GPR64Opnd:$rs, GPR64Opnd:$rt), 255))] in
def BADDu : ArithLogicR<"baddu", GPR64Opnd, 1, II_BADDU>,
ADD_FM<0x1c, 0x28>;
[MIPS] Add cpu octeon and some instructions The Octeon cpu from Cavium Networks is mips64r2 based and has an extended instruction set. In order to utilize this with LLVM, a new cpu feature "octeon" and a subtarget feature "cnmips" is added. A small set of new instructions (baddu, dmul, pop, dpop, seq, sne) is also added. LLVM generates dmul, pop and dpop instructions with option -mcpu=octeon or -mattr=+cnmips. llvm-svn: 204337
2014-03-20 19:51:58 +08:00
// Multiply Doubleword to GPR
let Defs = [HI0, LO0, P0, P1, P2] in
def DMUL : ArithLogicR<"dmul", GPR64Opnd, 1, II_DMUL, mul>,
ADD_FM<0x1c, 0x03>;
[mips] Add more Octeon cnMips instructions Adds the instructions ext/ext32/cins/cins32. It also changes pop/dpop to accept the two operand version and adds a simple pattern to generate baddu. Tests for the two operand versions (including baddu/dmul/dpop/pop) and the code generation pattern for baddu are included. Reviewed by: Daniel.Sanders@imgtec.com llvm-svn: 205449
2014-04-03 02:40:43 +08:00
// Extract a signed bit field /+32
def EXTS : ExtsCins<"exts">, EXTS_FM<0x3a>;
def EXTS32: ExtsCins<"exts32">, EXTS_FM<0x3b>;
// Clear and insert a bit field /+32
def CINS : ExtsCins<"cins">, EXTS_FM<0x32>;
def CINS32: ExtsCins<"cins32">, EXTS_FM<0x33>;
[mips] Add Octeon cnMips instructions mtmX and mtpX Adds the Octeon cnMips instructions "load multiplier register MPLx" and "load product register Px". Includes tests. Reviews by: Daniel.Sanders@imgtec.com llvm-svn: 205343
2014-04-02 02:35:26 +08:00
// Move to multiplier/product register
def MTM0 : MoveToLOHI<"mtm0", GPR64Opnd, [MPL0, P0, P1, P2]>, MTMR_FM<0x08>;
def MTM1 : MoveToLOHI<"mtm1", GPR64Opnd, [MPL1, P0, P1, P2]>, MTMR_FM<0x0c>;
def MTM2 : MoveToLOHI<"mtm2", GPR64Opnd, [MPL2, P0, P1, P2]>, MTMR_FM<0x0d>;
def MTP0 : MoveToLOHI<"mtp0", GPR64Opnd, [P0]>, MTMR_FM<0x09>;
def MTP1 : MoveToLOHI<"mtp1", GPR64Opnd, [P1]>, MTMR_FM<0x0a>;
def MTP2 : MoveToLOHI<"mtp2", GPR64Opnd, [P2]>, MTMR_FM<0x0b>;
[MIPS] Add cpu octeon and some instructions The Octeon cpu from Cavium Networks is mips64r2 based and has an extended instruction set. In order to utilize this with LLVM, a new cpu feature "octeon" and a subtarget feature "cnmips" is added. A small set of new instructions (baddu, dmul, pop, dpop, seq, sne) is also added. LLVM generates dmul, pop and dpop instructions with option -mcpu=octeon or -mattr=+cnmips. llvm-svn: 204337
2014-03-20 19:51:58 +08:00
// Count Ones in a Word/Doubleword
def POP : Count1s<"pop", GPR32Opnd>, POP_FM<0x2c>;
def DPOP : Count1s<"dpop", GPR64Opnd>, POP_FM<0x2d>;
// Set on equal/not equal
def SEQ : SetCC64_R<"seq", seteq>, SEQ_FM<0x2a>;
[mips] Add Octeon cnMips instructions seqi/snei and v3mulu/vmm0/vmulu. This patch adds the Octeon cnMips instructions seqi/snei and v3mulu/vmm0/vmulu. It is only for the assembler. Test case is included. Reviewed by: Daniel.Sanders@imgtec.com llvm-svn: 205631
2014-04-05 00:21:59 +08:00
def SEQi : SetCC64_I<"seqi", seteq>, SEQI_FM<0x2e>;
[MIPS] Add cpu octeon and some instructions The Octeon cpu from Cavium Networks is mips64r2 based and has an extended instruction set. In order to utilize this with LLVM, a new cpu feature "octeon" and a subtarget feature "cnmips" is added. A small set of new instructions (baddu, dmul, pop, dpop, seq, sne) is also added. LLVM generates dmul, pop and dpop instructions with option -mcpu=octeon or -mattr=+cnmips. llvm-svn: 204337
2014-03-20 19:51:58 +08:00
def SNE : SetCC64_R<"sne", setne>, SEQ_FM<0x2b>;
[mips] Add Octeon cnMips instructions seqi/snei and v3mulu/vmm0/vmulu. This patch adds the Octeon cnMips instructions seqi/snei and v3mulu/vmm0/vmulu. It is only for the assembler. Test case is included. Reviewed by: Daniel.Sanders@imgtec.com llvm-svn: 205631
2014-04-05 00:21:59 +08:00
def SNEi : SetCC64_I<"snei", setne>, SEQI_FM<0x2f>;
[mips] Remove non-ascii character. llvm-svn: 207123
2014-04-25 00:31:10 +08:00
// 192-bit x 64-bit Unsigned Multiply and Add
[mips] Add Octeon cnMips instructions seqi/snei and v3mulu/vmm0/vmulu. This patch adds the Octeon cnMips instructions seqi/snei and v3mulu/vmm0/vmulu. It is only for the assembler. Test case is included. Reviewed by: Daniel.Sanders@imgtec.com llvm-svn: 205631
2014-04-05 00:21:59 +08:00
let Defs = [P0, P1, P2] in
def V3MULU: ArithLogicR<"v3mulu", GPR64Opnd, 0, II_DMUL>,
ADD_FM<0x1c, 0x11>;
// 64-bit Unsigned Multiply and Add Move
let Defs = [MPL0, P0, P1, P2] in
def VMM0 : ArithLogicR<"vmm0", GPR64Opnd, 0, II_DMUL>,
ADD_FM<0x1c, 0x10>;
// 64-bit Unsigned Multiply and Add
let Defs = [MPL1, MPL2, P0, P1, P2] in
def VMULU : ArithLogicR<"vmulu", GPR64Opnd, 0, II_DMUL>,
ADD_FM<0x1c, 0x0f>;
[MIPS] Add cpu octeon and some instructions The Octeon cpu from Cavium Networks is mips64r2 based and has an extended instruction set. In order to utilize this with LLVM, a new cpu feature "octeon" and a subtarget feature "cnmips" is added. A small set of new instructions (baddu, dmul, pop, dpop, seq, sne) is also added. LLVM generates dmul, pop and dpop instructions with option -mcpu=octeon or -mattr=+cnmips. llvm-svn: 204337
2014-03-20 19:51:58 +08:00
}
Add disassembler to MIPS. Patch by Vladimir Medic. llvm-svn: 154935
2012-04-18 02:03:21 +08:00
}
[mips] Add more Octeon cnMips instructions Adds the instructions ext/ext32/cins/cins32. It also changes pop/dpop to accept the two operand version and adds a simple pattern to generate baddu. Tests for the two operand versions (including baddu/dmul/dpop/pop) and the code generation pattern for baddu are included. Reviewed by: Daniel.Sanders@imgtec.com llvm-svn: 205449
2014-04-03 02:40:43 +08:00
Add definitions of Mips64 rotate instructions. llvm-svn: 140870
2011-10-01 02:51:46 +08:00
//===----------------------------------------------------------------------===//
// Arbitrary patterns that map to one or more instructions
//===----------------------------------------------------------------------===//
32-to-64-bit extended load. llvm-svn: 144554
2011-11-15 03:06:14 +08:00
// extended loads
[mips] Remove redundant 'let Predicates = [HasStdEnc]' statements Summary: The MipsPat class already initializes Predicates to [HasStdEnc]. No functional change (confirmed by diffing tablegen-erated files before and after) Differential Revision: http://reviews.llvm.org/D3546 llvm-svn: 207548
2014-04-30 00:24:10 +08:00
def : MipsPat<(i64 (extloadi1 addr:$src)), (LB64 addr:$src)>;
def : MipsPat<(i64 (extloadi8 addr:$src)), (LB64 addr:$src)>;
def : MipsPat<(i64 (extloadi16 addr:$src)), (LH64 addr:$src)>;
def : MipsPat<(i64 (extloadi32 addr:$src)), (LW64 addr:$src)>;
Modify lowering of GlobalAddress so that correct code is emitted when target is Mips64. llvm-svn: 141618
2011-10-11 08:55:05 +08:00
// hi/lo relocs
1. introduce MipsPat in place of Pat in order to exclude those from being used by Mips16 or Micro Mips 2. clean up a few lines too long encountered Patch by Reed Kotler. llvm-svn: 158470
2012-06-15 05:03:23 +08:00
def : MipsPat<(MipsHi tglobaladdr:$in), (LUi64 tglobaladdr:$in)>;
def : MipsPat<(MipsHi tblockaddress:$in), (LUi64 tblockaddress:$in)>;
def : MipsPat<(MipsHi tjumptable:$in), (LUi64 tjumptable:$in)>;
def : MipsPat<(MipsHi tconstpool:$in), (LUi64 tconstpool:$in)>;
def : MipsPat<(MipsHi tglobaltlsaddr:$in), (LUi64 tglobaltlsaddr:$in)>;
[mips] Generate big GOT code. llvm-svn: 168460
2012-11-22 04:40:38 +08:00
def : MipsPat<(MipsHi texternalsym:$in), (LUi64 texternalsym:$in)>;
1. introduce MipsPat in place of Pat in order to exclude those from being used by Mips16 or Micro Mips 2. clean up a few lines too long encountered Patch by Reed Kotler. llvm-svn: 158470
2012-06-15 05:03:23 +08:00
def : MipsPat<(MipsLo tglobaladdr:$in), (DADDiu ZERO_64, tglobaladdr:$in)>;
def : MipsPat<(MipsLo tblockaddress:$in), (DADDiu ZERO_64, tblockaddress:$in)>;
def : MipsPat<(MipsLo tjumptable:$in), (DADDiu ZERO_64, tjumptable:$in)>;
def : MipsPat<(MipsLo tconstpool:$in), (DADDiu ZERO_64, tconstpool:$in)>;
def : MipsPat<(MipsLo tglobaltlsaddr:$in),
(DADDiu ZERO_64, tglobaltlsaddr:$in)>;
[mips] Generate big GOT code. llvm-svn: 168460
2012-11-22 04:40:38 +08:00
def : MipsPat<(MipsLo texternalsym:$in), (DADDiu ZERO_64, texternalsym:$in)>;
1. introduce MipsPat in place of Pat in order to exclude those from being used by Mips16 or Micro Mips 2. clean up a few lines too long encountered Patch by Reed Kotler. llvm-svn: 158470
2012-06-15 05:03:23 +08:00
[mips] Rename register classes CPURegs and CPU64Regs. llvm-svn: 187832
2013-08-07 07:08:38 +08:00
def : MipsPat<(add GPR64:$hi, (MipsLo tglobaladdr:$lo)),
(DADDiu GPR64:$hi, tglobaladdr:$lo)>;
def : MipsPat<(add GPR64:$hi, (MipsLo tblockaddress:$lo)),
(DADDiu GPR64:$hi, tblockaddress:$lo)>;
def : MipsPat<(add GPR64:$hi, (MipsLo tjumptable:$lo)),
(DADDiu GPR64:$hi, tjumptable:$lo)>;
def : MipsPat<(add GPR64:$hi, (MipsLo tconstpool:$lo)),
(DADDiu GPR64:$hi, tconstpool:$lo)>;
def : MipsPat<(add GPR64:$hi, (MipsLo tglobaltlsaddr:$lo)),
(DADDiu GPR64:$hi, tglobaltlsaddr:$lo)>;
def : WrapperPat<tglobaladdr, DADDiu, GPR64>;
def : WrapperPat<tconstpool, DADDiu, GPR64>;
def : WrapperPat<texternalsym, DADDiu, GPR64>;
def : WrapperPat<tblockaddress, DADDiu, GPR64>;
def : WrapperPat<tjumptable, DADDiu, GPR64>;
def : WrapperPat<tglobaltlsaddr, DADDiu, GPR64>;
defm : BrcondPats<GPR64, BEQ64, BNE64, SLT64, SLTu64, SLTi64, SLTiu64,
Add patterns for conditional branches with 64-bit register operands. llvm-svn: 141696
2011-10-12 03:09:09 +08:00
ZERO_64>;
[mips] Add instruction selection patterns for blez and bgez. llvm-svn: 182396
2013-05-22 01:13:47 +08:00
def : MipsPat<(brcond (i32 (setlt i64:$lhs, 1)), bb:$dst),
(BLEZ64 i64:$lhs, bb:$dst)>;
def : MipsPat<(brcond (i32 (setgt i64:$lhs, -1)), bb:$dst),
(BGEZ64 i64:$lhs, bb:$dst)>;
Add support for 64-bit set-on-less-than instructions. llvm-svn: 141695
2011-10-12 02:53:46 +08:00
// setcc patterns
[mips] Rename register classes CPURegs and CPU64Regs. llvm-svn: 187832
2013-08-07 07:08:38 +08:00
defm : SeteqPats<GPR64, SLTiu64, XOR64, SLTu64, ZERO_64>;
defm : SetlePats<GPR64, SLT64, SLTu64>;
defm : SetgtPats<GPR64, SLT64, SLTu64>;
defm : SetgePats<GPR64, SLT64, SLTu64>;
defm : SetgeImmPats<GPR64, SLTi64, SLTiu64>;
Add 64-bit to 32-bit trunc pattern. llvm-svn: 143988
2011-11-08 02:57:41 +08:00
// truncate
[mips] Rename register classes CPURegs and CPU64Regs. llvm-svn: 187832
2013-08-07 07:08:38 +08:00
def : MipsPat<(i32 (trunc GPR64:$src)),
[mips] Split Instruction.Predicates into smaller lists and re-join them with !listconcat Summary: The overall idea is to chop the Predicates list into subsets that are usually overridden independently. This allows subclasses to partially override the predicates of their superclasses without having to re-add all the existing predicates. This patch starts the process by moving HasStdEnc into a new EncodingPredicates list and almost everything else into AdditionalPredicates. It has revealed a couple likely bugs where 'let Predicates' has removed the HasStdEnc predicate. No functional change (confirmed by diffing tablegen-erated files). Depends on D3549, D3506 Reviewers: vmedic Differential Revision: http://reviews.llvm.org/D3550 llvm-svn: 208184
2014-05-07 18:27:09 +08:00
(SLL (EXTRACT_SUBREG GPR64:$src, sub_32), 0)>;
remove blanks, and some code format llvm-svn: 151625
2012-02-28 15:46:26 +08:00
32 to 64-bit zext pattern. llvm-svn: 146096
2011-12-08 07:14:41 +08:00
// 32-to-64-bit extension
[mips] Rename register classes CPURegs and CPU64Regs. llvm-svn: 187832
2013-08-07 07:08:38 +08:00
def : MipsPat<(i64 (anyext GPR32:$src)), (SLL64_32 GPR32:$src)>;
def : MipsPat<(i64 (zext GPR32:$src)), (DSRL (DSLL64_32 GPR32:$src), 32)>;
def : MipsPat<(i64 (sext GPR32:$src)), (SLL64_32 GPR32:$src)>;
32-to-64-bit sign extension pattern. llvm-svn: 146995
2011-12-21 06:06:20 +08:00
32-to-64-bit sext_inreg pattern. llvm-svn: 147004
2011-12-21 06:40:40 +08:00
// Sign extend in register
[mips] Rename register classes CPURegs and CPU64Regs. llvm-svn: 187832
2013-08-07 07:08:38 +08:00
def : MipsPat<(i64 (sext_inreg GPR64:$src, i32)),
(SLL64_64 GPR64:$src)>;
32-to-64-bit sext_inreg pattern. llvm-svn: 147004
2011-12-21 06:40:40 +08:00
1. introduce MipsPat in place of Pat in order to exclude those from being used by Mips16 or Micro Mips 2. clean up a few lines too long encountered Patch by Reed Kotler. llvm-svn: 158470
2012-06-15 05:03:23 +08:00
// bswap MipsPattern
[mips] Rename register classes CPURegs and CPU64Regs. llvm-svn: 187832
2013-08-07 07:08:38 +08:00
def : MipsPat<(bswap GPR64:$rt), (DSHD (DSBH GPR64:$rt))>;
Improvements to MIPS64 assembler: - Teach it about dadd[i] instructions and move pseudo-instruction - Make it parse the register names correctly (for N32 / N64) llvm-svn: 165506
2012-10-10 00:27:43 +08:00
//===----------------------------------------------------------------------===//
// Instruction aliases
//===----------------------------------------------------------------------===//
[mips] Add PredicateControl to InstAlias's Summary: No functional change Depends on D3649 Reviewers: vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3672 llvm-svn: 208334
2014-05-09 00:12:31 +08:00
def : MipsInstAlias<"move $dst, $src",
(DADDu GPR64Opnd:$dst, GPR64Opnd:$src, ZERO_64), 1>,
[mips] Free up two values in SubtargetFeatureFlag by folding the redundant IsGP32/IsGP64 into IsGP32bit/IsGP64bit Summary: We are currently very close to the 32-bit limit of the current assembler implementation. This is because there is no way to represent an instruction that is available in, for example, Mips3 or Mips32. We have to define a feature bit that represents this. This patch cleans up a pair of redundant feature bits and slightly postpones the point we will reach the limit. Reviewers: zoran.jovanovic, jkolek, vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3703 llvm-svn: 208685
2014-05-13 19:17:46 +08:00
GPR_64;
[mips] Add PredicateControl to InstAlias's Summary: No functional change Depends on D3649 Reviewers: vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3672 llvm-svn: 208334
2014-05-09 00:12:31 +08:00
def : MipsInstAlias<"daddu $rs, $rt, $imm",
(DADDiu GPR64Opnd:$rs, GPR64Opnd:$rt, simm16_64:$imm),
0>;
def : MipsInstAlias<"dadd $rs, $rt, $imm",
(DADDi GPR64Opnd:$rs, GPR64Opnd:$rt, simm16_64:$imm),
0>;
def : MipsInstAlias<"daddu $rs, $imm",
(DADDiu GPR64Opnd:$rs, GPR64Opnd:$rs, simm16_64:$imm),
0>;
def : MipsInstAlias<"dadd $rs, $imm",
(DADDi GPR64Opnd:$rs, GPR64Opnd:$rs, simm16_64:$imm),
0>;
def : MipsInstAlias<"add $rs, $imm",
(ADDi GPR32Opnd:$rs, GPR32Opnd:$rs, simm16:$imm),
0>;
def : MipsInstAlias<"addu $rs, $imm",
(ADDiu GPR32Opnd:$rs, GPR32Opnd:$rs, simm16:$imm),
0>;
def : MipsInstAlias<"dsll $rd, $rt, $rs",
[mips] Marked up instructions added in MIPS-III and tested that IAS for -mcpu=mips[12] does not accept them Summary: This required a new instruction group representing the 32-bit subset of MIPS-III that was available in MIPS32 A small number of instructions are correctly rejected but with the wrong error message. These have been placed in a separate test for now. There's some obvious InstAlias's that ought to be marked MIPS-III but arent. This is because they are not currently tested. I intend to catch these with a final pass through the tablegen records to find tablegen records without ISA annotations. Depends on D3674 Reviewers: vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3675 llvm-svn: 208408
2014-05-09 21:02:27 +08:00
(DSLLV GPR64Opnd:$rd, GPR64Opnd:$rt, GPR32Opnd:$rs), 0>,
ISA_MIPS3;
[mips] Add PredicateControl to InstAlias's Summary: No functional change Depends on D3649 Reviewers: vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3672 llvm-svn: 208334
2014-05-09 00:12:31 +08:00
def : MipsInstAlias<"dsubu $rt, $rs, $imm",
(DADDiu GPR64Opnd:$rt, GPR64Opnd:$rs,
InvertedImOperand64:$imm), 0>;
def : MipsInstAlias<"dsub $rs, $imm",
(DADDi GPR64Opnd:$rs, GPR64Opnd:$rs,
InvertedImOperand64:$imm),
0>;
def : MipsInstAlias<"dsubu $rs, $imm",
(DADDiu GPR64Opnd:$rs, GPR64Opnd:$rs,
InvertedImOperand64:$imm),
0>;
[mips] Added missing dsra -> dsrav and sra -> srav aliases. Summary: dsll, dsrl, sll, and srl already exist. Reviewers: vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3673 llvm-svn: 208397
2014-05-09 17:24:49 +08:00
def : MipsInstAlias<"dsra $rd, $rt, $rs",
[mips] Marked up instructions added in MIPS-III and tested that IAS for -mcpu=mips[12] does not accept them Summary: This required a new instruction group representing the 32-bit subset of MIPS-III that was available in MIPS32 A small number of instructions are correctly rejected but with the wrong error message. These have been placed in a separate test for now. There's some obvious InstAlias's that ought to be marked MIPS-III but arent. This is because they are not currently tested. I intend to catch these with a final pass through the tablegen records to find tablegen records without ISA annotations. Depends on D3674 Reviewers: vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3675 llvm-svn: 208408
2014-05-09 21:02:27 +08:00
(DSRAV GPR64Opnd:$rd, GPR64Opnd:$rt, GPR32Opnd:$rs), 0>,
ISA_MIPS3;
[mips] Add PredicateControl to InstAlias's Summary: No functional change Depends on D3649 Reviewers: vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3672 llvm-svn: 208334
2014-05-09 00:12:31 +08:00
def : MipsInstAlias<"dsrl $rd, $rt, $rs",
[mips] Marked up instructions added in MIPS-III and tested that IAS for -mcpu=mips[12] does not accept them Summary: This required a new instruction group representing the 32-bit subset of MIPS-III that was available in MIPS32 A small number of instructions are correctly rejected but with the wrong error message. These have been placed in a separate test for now. There's some obvious InstAlias's that ought to be marked MIPS-III but arent. This is because they are not currently tested. I intend to catch these with a final pass through the tablegen records to find tablegen records without ISA annotations. Depends on D3674 Reviewers: vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3675 llvm-svn: 208408
2014-05-09 21:02:27 +08:00
(DSRLV GPR64Opnd:$rd, GPR64Opnd:$rt, GPR32Opnd:$rs), 0>,
ISA_MIPS3;
This is a resubmittal. For some reason it broke the bots yesterday but I cannot reproduce the problem and have scrubed my sources and even tested with llvm-lit -v --vg. Removal of redundant code and formatting fixes. Contributers: Jack Carter/Vladimir Medic llvm-svn: 172842
2013-01-19 04:15:06 +08:00
Mips assembler: Add branch macro definitions This patch adds bnez and beqz instructions which represent alias definitions for bne and beq instructions as follows: bnez $rs,$imm => bne $rs,$zero,$imm beqz $rs,$imm => beq $rs,$zero,$imm The corresponding test cases are added. Patch by Vladimir Medic llvm-svn: 182040
2013-05-17 03:40:19 +08:00
/// Move between CPU and coprocessor registers
[mips] Clean up definitions of move word from/to coprocessor instructions. No functionality change. llvm-svn: 189431
2013-08-28 08:42:50 +08:00
let DecoderNamespace = "Mips64", Predicates = [HasMips64] in {
def DMFC0 : MFC3OP<"dmfc0", GPR64Opnd>, MFC3OP_FM<0x10, 1>;
[mips] Marked up instructions added in MIPS-III and tested that IAS for -mcpu=mips[12] does not accept them Summary: This required a new instruction group representing the 32-bit subset of MIPS-III that was available in MIPS32 A small number of instructions are correctly rejected but with the wrong error message. These have been placed in a separate test for now. There's some obvious InstAlias's that ought to be marked MIPS-III but arent. This is because they are not currently tested. I intend to catch these with a final pass through the tablegen records to find tablegen records without ISA annotations. Depends on D3674 Reviewers: vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3675 llvm-svn: 208408
2014-05-09 21:02:27 +08:00
def DMTC0 : MFC3OP<"dmtc0", GPR64Opnd>, MFC3OP_FM<0x10, 5>, ISA_MIPS3;
def DMFC2 : MFC3OP<"dmfc2", GPR64Opnd>, MFC3OP_FM<0x12, 1>, ISA_MIPS3;
def DMTC2 : MFC3OP<"dmtc2", GPR64Opnd>, MFC3OP_FM<0x12, 5>, ISA_MIPS3;
Expose move to/from coprocessor instructions in MIPS64 mode. Note: [D]M{T,F}CP2 is just a recommended encoding. Vendors often provide a custom CP2 that interprets instructions differently and may wish to add their own instructions that use this opcode. We should ensure that this is easy to do. I will probably add a 'has custom CP{0-3}' subtarget flag to make this easy: We want to avoid the GCC situation where every MIPS vendor makes a custom fork that breaks every other MIPS CPU and so can't be merged upstream. llvm-svn: 165711
2012-10-11 18:21:34 +08:00
}
This is a resubmittal. For some reason it broke the bots yesterday but I cannot reproduce the problem and have scrubed my sources and even tested with llvm-lit -v --vg. Removal of redundant code and formatting fixes. Contributers: Jack Carter/Vladimir Medic llvm-svn: 172842
2013-01-19 04:15:06 +08:00
Expose move to/from coprocessor instructions in MIPS64 mode. Note: [D]M{T,F}CP2 is just a recommended encoding. Vendors often provide a custom CP2 that interprets instructions differently and may wish to add their own instructions that use this opcode. We should ensure that this is easy to do. I will probably add a 'has custom CP{0-3}' subtarget flag to make this easy: We want to avoid the GCC situation where every MIPS vendor makes a custom fork that breaks every other MIPS CPU and so can't be merged upstream. llvm-svn: 165711
2012-10-11 18:21:34 +08:00
// Two operand (implicit 0 selector) versions:
[mips] Add PredicateControl to InstAlias's Summary: No functional change Depends on D3649 Reviewers: vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3672 llvm-svn: 208334
2014-05-09 00:12:31 +08:00
def : MipsInstAlias<"dmfc0 $rt, $rd", (DMFC0 GPR64Opnd:$rt, GPR64Opnd:$rd, 0), 0>;
def : MipsInstAlias<"dmtc0 $rt, $rd", (DMTC0 GPR64Opnd:$rt, GPR64Opnd:$rd, 0), 0>;
def : MipsInstAlias<"dmfc2 $rt, $rd", (DMFC2 GPR64Opnd:$rt, GPR64Opnd:$rd, 0), 0>;
def : MipsInstAlias<"dmtc2 $rt, $rd", (DMTC2 GPR64Opnd:$rt, GPR64Opnd:$rd, 0), 0>;
Expose move to/from coprocessor instructions in MIPS64 mode. Note: [D]M{T,F}CP2 is just a recommended encoding. Vendors often provide a custom CP2 that interprets instructions differently and may wish to add their own instructions that use this opcode. We should ensure that this is easy to do. I will probably add a 'has custom CP{0-3}' subtarget flag to make this easy: We want to avoid the GCC situation where every MIPS vendor makes a custom fork that breaks every other MIPS CPU and so can't be merged upstream. llvm-svn: 165711
2012-10-11 18:21:34 +08:00