maxjhandsome
/
llvm-project
forked from OSchip/llvm-project
1
0
Fork 0
Code Issues Pull Requests Packages Releases Wiki Activity
llvm-project/llvm/test/MC/Disassembler/ARM/d16.txt

24 lines
726 B
Plaintext
Raw Normal View History

Fix bashism in tests added by r221341 llvm-svn: 221342
2014-11-05 20:40:21 +08:00
# RUN: llvm-mc < %s -triple thumbv7-unknown-unknown -disassemble -mattr=+vfp4,-d16 2>&1 | FileCheck %s --check-prefix=D32
# RUN: llvm-mc < %s -triple thumbv7-unknown-unknown -disassemble -mattr=+vfp4,-d16 2>&1 | FileCheck %s --check-prefix=D32
[ARM] Honor FeatureD16 in the assembler and disassembler Some ARM FPUs only have 16 double-precision registers, rather than the normal 32. LLVM represents this with the D16 target feature. This is currently used by CodeGen to avoid using high registers when they are not available, but the assembler and disassembler do not. I fix this in the assmebler and disassembler rather than the InstrInfo.td files, as the latter would require a large number of changes everywhere one of the floating-point instructions is referenced in the backend. This solution is similar to the one used for co-processor numbers and MSR masks. llvm-svn: 221341
2014-11-05 20:06:39 +08:00
# D32: vadd.f64 d1, d2, d16
# D16: warning: invalid instruction encoding
[0x32,0xee,0x20,0x1b]
# D32: vadd.f64 d1, d17, d6
# D16: warning: invalid instruction encoding
[0x31,0xee,0x86,0x1b]
# D32: vadd.f64 d19, d7, d6
# D16: warning: invalid instruction encoding
[0x77,0xee,0x06,0x3b]
# D32: vcvt.f64.f32 d22, s4
# D16: warning: invalid instruction encoding
[0xf7,0xee,0xc2,0x6a]
# D32: vcvt.f32.f64 s26, d30
# D16: warning: invalid instruction encoding
[0xb7,0xee,0xee,0xdb]