forked from OSchip/llvm-project
60 lines
1.7 KiB
C++
60 lines
1.7 KiB
C++
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//===- HexagonSubtarget.cpp - Hexagon Subtarget Information ---------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file implements the Hexagon specific subclass of TargetSubtarget.
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//
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//===----------------------------------------------------------------------===//
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#include "HexagonSubtarget.h"
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#include "Hexagon.h"
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#include "llvm/Support/CommandLine.h"
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#include "llvm/Support/ErrorHandling.h"
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using namespace llvm;
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#define GET_SUBTARGETINFO_CTOR
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#define GET_SUBTARGETINFO_TARGET_DESC
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#include "HexagonGenSubtargetInfo.inc"
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static cl::opt<bool>
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EnableV3("enable-hexagon-v3", cl::Hidden,
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cl::desc("Enable Hexagon V3 instructions."));
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static cl::opt<bool>
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EnableMemOps(
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"enable-hexagon-memops",
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cl::Hidden, cl::ZeroOrMore, cl::ValueDisallowed,
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cl::desc("Generate V4 MEMOP in code generation for Hexagon target"));
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HexagonSubtarget::HexagonSubtarget(StringRef TT, StringRef CPU, StringRef FS):
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HexagonGenSubtargetInfo(TT, CPU, FS),
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HexagonArchVersion(V1),
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CPUString(CPU.str()) {
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ParseSubtargetFeatures(CPU, FS);
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switch(HexagonArchVersion) {
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case HexagonSubtarget::V2:
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break;
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case HexagonSubtarget::V3:
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EnableV3 = true;
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break;
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case HexagonSubtarget::V4:
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break;
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default:
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llvm_unreachable("Unknown Architecture Version.");
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}
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// Initialize scheduling itinerary for the specified CPU.
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InstrItins = getInstrItineraryForCPU(CPUString);
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if (EnableMemOps)
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UseMemOps = true;
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else
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UseMemOps = false;
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}
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