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[Tests] Autogen a test in advance of updates llvm-svn: 360091
2019-05-07 06:12:07 +08:00
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
Introduce element-wise atomic memcpy intrinsic This change adds a new intrinsic which is intended to provide memcpy functionality with additional atomicity guarantees. Please refer to the review thread or language reference for further details. Differential Revision: https://reviews.llvm.org/D27133 llvm-svn: 290708
2016-12-29 22:31:07 +08:00
; RUN: llc < %s -mtriple=x86_64-unknown-linux-gnu | FileCheck %s
[Tests] Rename tests before adding new ones llvm-svn: 360092
2019-05-07 06:16:55 +08:00
define i8* @test_memcpy1_generic(i8* %P, i8* %Q) {
; CHECK-LABEL: test_memcpy1_generic:
[Tests] Autogen a test in advance of updates llvm-svn: 360091
2019-05-07 06:12:07 +08:00
; CHECK: # %bb.0:
; CHECK-NEXT: pushq %rbx
; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: .cfi_offset %rbx, -16
; CHECK-NEXT: movq %rdi, %rbx
; CHECK-NEXT: movl $1024, %edx # imm = 0x400
; CHECK-NEXT: callq __llvm_memcpy_element_unordered_atomic_1
; CHECK-NEXT: movq %rbx, %rax
; CHECK-NEXT: popq %rbx
; CHECK-NEXT: .cfi_def_cfa_offset 8
; CHECK-NEXT: retq
Changing constants in a test (NFC) Summary: Changing the lengths of the atomic memory intrinsics in a test to make sure that they don't get lowered into loads/stores if/when expansion of these occurs in selectiondag. llvm-svn: 331800
2018-05-09 03:08:12 +08:00
call void @llvm.memcpy.element.unordered.atomic.p0i8.p0i8.i32(i8* align 4 %P, i8* align 4 %Q, i32 1024, i32 1)
Introduce element-wise atomic memcpy intrinsic This change adds a new intrinsic which is intended to provide memcpy functionality with additional atomicity guarantees. Please refer to the review thread or language reference for further details. Differential Revision: https://reviews.llvm.org/D27133 llvm-svn: 290708
2016-12-29 22:31:07 +08:00
ret i8* %P
[Atomics] Rename and change prototype for atomic memcpy intrinsic Summary: Background: http://lists.llvm.org/pipermail/llvm-dev/2017-May/112779.html This change is to alter the prototype for the atomic memcpy intrinsic. The prototype itself is being changed to more closely resemble the semantics and parameters of the llvm.memcpy intrinsic -- to ease later combination of the llvm.memcpy and atomic memcpy intrinsics. Furthermore, the name of the atomic memcpy intrinsic is being changed to make it clear that it is not a generic atomic memcpy, but specifically a memcpy is unordered atomic. Reviewers: reames, sanjoy, efriedma Reviewed By: reames Subscribers: mzolotukhin, anna, llvm-commits, skatkov Differential Revision: https://reviews.llvm.org/D33240 llvm-svn: 305558
2017-06-16 22:43:59 +08:00
; 3rd arg (%edx) -- length
Introduce element-wise atomic memcpy intrinsic This change adds a new intrinsic which is intended to provide memcpy functionality with additional atomicity guarantees. Please refer to the review thread or language reference for further details. Differential Revision: https://reviews.llvm.org/D27133 llvm-svn: 290708
2016-12-29 22:31:07 +08:00
}
[Tests] Rename tests before adding new ones llvm-svn: 360092
2019-05-07 06:16:55 +08:00
define i8* @test_memcpy2_generic(i8* %P, i8* %Q) {
; CHECK-LABEL: test_memcpy2_generic:
[Tests] Autogen a test in advance of updates llvm-svn: 360091
2019-05-07 06:12:07 +08:00
; CHECK: # %bb.0:
; CHECK-NEXT: pushq %rbx
; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: .cfi_offset %rbx, -16
; CHECK-NEXT: movq %rdi, %rbx
; CHECK-NEXT: movl $1024, %edx # imm = 0x400
; CHECK-NEXT: callq __llvm_memcpy_element_unordered_atomic_2
; CHECK-NEXT: movq %rbx, %rax
; CHECK-NEXT: popq %rbx
; CHECK-NEXT: .cfi_def_cfa_offset 8
; CHECK-NEXT: retq
Changing constants in a test (NFC) Summary: Changing the lengths of the atomic memory intrinsics in a test to make sure that they don't get lowered into loads/stores if/when expansion of these occurs in selectiondag. llvm-svn: 331800
2018-05-09 03:08:12 +08:00
call void @llvm.memcpy.element.unordered.atomic.p0i8.p0i8.i32(i8* align 4 %P, i8* align 4 %Q, i32 1024, i32 2)
Introduce element-wise atomic memcpy intrinsic This change adds a new intrinsic which is intended to provide memcpy functionality with additional atomicity guarantees. Please refer to the review thread or language reference for further details. Differential Revision: https://reviews.llvm.org/D27133 llvm-svn: 290708
2016-12-29 22:31:07 +08:00
ret i8* %P
[Atomics] Rename and change prototype for atomic memcpy intrinsic Summary: Background: http://lists.llvm.org/pipermail/llvm-dev/2017-May/112779.html This change is to alter the prototype for the atomic memcpy intrinsic. The prototype itself is being changed to more closely resemble the semantics and parameters of the llvm.memcpy intrinsic -- to ease later combination of the llvm.memcpy and atomic memcpy intrinsics. Furthermore, the name of the atomic memcpy intrinsic is being changed to make it clear that it is not a generic atomic memcpy, but specifically a memcpy is unordered atomic. Reviewers: reames, sanjoy, efriedma Reviewed By: reames Subscribers: mzolotukhin, anna, llvm-commits, skatkov Differential Revision: https://reviews.llvm.org/D33240 llvm-svn: 305558
2017-06-16 22:43:59 +08:00
; 3rd arg (%edx) -- length
Introduce element-wise atomic memcpy intrinsic This change adds a new intrinsic which is intended to provide memcpy functionality with additional atomicity guarantees. Please refer to the review thread or language reference for further details. Differential Revision: https://reviews.llvm.org/D27133 llvm-svn: 290708
2016-12-29 22:31:07 +08:00
}
[Tests] Rename tests before adding new ones llvm-svn: 360092
2019-05-07 06:16:55 +08:00
define i8* @test_memcpy4_generic(i8* %P, i8* %Q) {
; CHECK-LABEL: test_memcpy4_generic:
[Tests] Autogen a test in advance of updates llvm-svn: 360091
2019-05-07 06:12:07 +08:00
; CHECK: # %bb.0:
; CHECK-NEXT: pushq %rbx
; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: .cfi_offset %rbx, -16
; CHECK-NEXT: movq %rdi, %rbx
; CHECK-NEXT: movl $1024, %edx # imm = 0x400
; CHECK-NEXT: callq __llvm_memcpy_element_unordered_atomic_4
; CHECK-NEXT: movq %rbx, %rax
; CHECK-NEXT: popq %rbx
; CHECK-NEXT: .cfi_def_cfa_offset 8
; CHECK-NEXT: retq
Changing constants in a test (NFC) Summary: Changing the lengths of the atomic memory intrinsics in a test to make sure that they don't get lowered into loads/stores if/when expansion of these occurs in selectiondag. llvm-svn: 331800
2018-05-09 03:08:12 +08:00
call void @llvm.memcpy.element.unordered.atomic.p0i8.p0i8.i32(i8* align 4 %P, i8* align 4 %Q, i32 1024, i32 4)
Introduce element-wise atomic memcpy intrinsic This change adds a new intrinsic which is intended to provide memcpy functionality with additional atomicity guarantees. Please refer to the review thread or language reference for further details. Differential Revision: https://reviews.llvm.org/D27133 llvm-svn: 290708
2016-12-29 22:31:07 +08:00
ret i8* %P
[Atomics] Rename and change prototype for atomic memcpy intrinsic Summary: Background: http://lists.llvm.org/pipermail/llvm-dev/2017-May/112779.html This change is to alter the prototype for the atomic memcpy intrinsic. The prototype itself is being changed to more closely resemble the semantics and parameters of the llvm.memcpy intrinsic -- to ease later combination of the llvm.memcpy and atomic memcpy intrinsics. Furthermore, the name of the atomic memcpy intrinsic is being changed to make it clear that it is not a generic atomic memcpy, but specifically a memcpy is unordered atomic. Reviewers: reames, sanjoy, efriedma Reviewed By: reames Subscribers: mzolotukhin, anna, llvm-commits, skatkov Differential Revision: https://reviews.llvm.org/D33240 llvm-svn: 305558
2017-06-16 22:43:59 +08:00
; 3rd arg (%edx) -- length
Introduce element-wise atomic memcpy intrinsic This change adds a new intrinsic which is intended to provide memcpy functionality with additional atomicity guarantees. Please refer to the review thread or language reference for further details. Differential Revision: https://reviews.llvm.org/D27133 llvm-svn: 290708
2016-12-29 22:31:07 +08:00
}
define i8* @test_memcpy8(i8* %P, i8* %Q) {
[Tests] Autogen a test in advance of updates llvm-svn: 360091
2019-05-07 06:12:07 +08:00
; CHECK-LABEL: test_memcpy8:
; CHECK: # %bb.0:
; CHECK-NEXT: pushq %rbx
; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: .cfi_offset %rbx, -16
; CHECK-NEXT: movq %rdi, %rbx
; CHECK-NEXT: movl $1024, %edx # imm = 0x400
; CHECK-NEXT: callq __llvm_memcpy_element_unordered_atomic_8
; CHECK-NEXT: movq %rbx, %rax
; CHECK-NEXT: popq %rbx
; CHECK-NEXT: .cfi_def_cfa_offset 8
; CHECK-NEXT: retq
Changing constants in a test (NFC) Summary: Changing the lengths of the atomic memory intrinsics in a test to make sure that they don't get lowered into loads/stores if/when expansion of these occurs in selectiondag. llvm-svn: 331800
2018-05-09 03:08:12 +08:00
call void @llvm.memcpy.element.unordered.atomic.p0i8.p0i8.i32(i8* align 8 %P, i8* align 8 %Q, i32 1024, i32 8)
Introduce element-wise atomic memcpy intrinsic This change adds a new intrinsic which is intended to provide memcpy functionality with additional atomicity guarantees. Please refer to the review thread or language reference for further details. Differential Revision: https://reviews.llvm.org/D27133 llvm-svn: 290708
2016-12-29 22:31:07 +08:00
ret i8* %P
[Atomics] Rename and change prototype for atomic memcpy intrinsic Summary: Background: http://lists.llvm.org/pipermail/llvm-dev/2017-May/112779.html This change is to alter the prototype for the atomic memcpy intrinsic. The prototype itself is being changed to more closely resemble the semantics and parameters of the llvm.memcpy intrinsic -- to ease later combination of the llvm.memcpy and atomic memcpy intrinsics. Furthermore, the name of the atomic memcpy intrinsic is being changed to make it clear that it is not a generic atomic memcpy, but specifically a memcpy is unordered atomic. Reviewers: reames, sanjoy, efriedma Reviewed By: reames Subscribers: mzolotukhin, anna, llvm-commits, skatkov Differential Revision: https://reviews.llvm.org/D33240 llvm-svn: 305558
2017-06-16 22:43:59 +08:00
; 3rd arg (%edx) -- length
Introduce element-wise atomic memcpy intrinsic This change adds a new intrinsic which is intended to provide memcpy functionality with additional atomicity guarantees. Please refer to the review thread or language reference for further details. Differential Revision: https://reviews.llvm.org/D27133 llvm-svn: 290708
2016-12-29 22:31:07 +08:00
}
[Tests] Rename tests before adding new ones llvm-svn: 360092
2019-05-07 06:16:55 +08:00
define i8* @test_memcpy16_generic(i8* %P, i8* %Q) {
; CHECK-LABEL: test_memcpy16_generic:
[Tests] Autogen a test in advance of updates llvm-svn: 360091
2019-05-07 06:12:07 +08:00
; CHECK: # %bb.0:
; CHECK-NEXT: pushq %rbx
; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: .cfi_offset %rbx, -16
; CHECK-NEXT: movq %rdi, %rbx
; CHECK-NEXT: movl $1024, %edx # imm = 0x400
; CHECK-NEXT: callq __llvm_memcpy_element_unordered_atomic_16
; CHECK-NEXT: movq %rbx, %rax
; CHECK-NEXT: popq %rbx
; CHECK-NEXT: .cfi_def_cfa_offset 8
; CHECK-NEXT: retq
Changing constants in a test (NFC) Summary: Changing the lengths of the atomic memory intrinsics in a test to make sure that they don't get lowered into loads/stores if/when expansion of these occurs in selectiondag. llvm-svn: 331800
2018-05-09 03:08:12 +08:00
call void @llvm.memcpy.element.unordered.atomic.p0i8.p0i8.i32(i8* align 16 %P, i8* align 16 %Q, i32 1024, i32 16)
Introduce element-wise atomic memcpy intrinsic This change adds a new intrinsic which is intended to provide memcpy functionality with additional atomicity guarantees. Please refer to the review thread or language reference for further details. Differential Revision: https://reviews.llvm.org/D27133 llvm-svn: 290708
2016-12-29 22:31:07 +08:00
ret i8* %P
[Atomics] Rename and change prototype for atomic memcpy intrinsic Summary: Background: http://lists.llvm.org/pipermail/llvm-dev/2017-May/112779.html This change is to alter the prototype for the atomic memcpy intrinsic. The prototype itself is being changed to more closely resemble the semantics and parameters of the llvm.memcpy intrinsic -- to ease later combination of the llvm.memcpy and atomic memcpy intrinsics. Furthermore, the name of the atomic memcpy intrinsic is being changed to make it clear that it is not a generic atomic memcpy, but specifically a memcpy is unordered atomic. Reviewers: reames, sanjoy, efriedma Reviewed By: reames Subscribers: mzolotukhin, anna, llvm-commits, skatkov Differential Revision: https://reviews.llvm.org/D33240 llvm-svn: 305558
2017-06-16 22:43:59 +08:00
; 3rd arg (%edx) -- length
Introduce element-wise atomic memcpy intrinsic This change adds a new intrinsic which is intended to provide memcpy functionality with additional atomicity guarantees. Please refer to the review thread or language reference for further details. Differential Revision: https://reviews.llvm.org/D27133 llvm-svn: 290708
2016-12-29 22:31:07 +08:00
}
define void @test_memcpy_args(i8** %Storage) {
[Tests] Autogen a test in advance of updates llvm-svn: 360091
2019-05-07 06:12:07 +08:00
; CHECK-LABEL: test_memcpy_args:
; CHECK: # %bb.0:
; CHECK-NEXT: pushq %rax
; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: movq (%rdi), %rax
; CHECK-NEXT: movq 8(%rdi), %rsi
; CHECK-NEXT: movq %rax, %rdi
; CHECK-NEXT: movl $1024, %edx # imm = 0x400
; CHECK-NEXT: callq __llvm_memcpy_element_unordered_atomic_4
; CHECK-NEXT: popq %rax
; CHECK-NEXT: .cfi_def_cfa_offset 8
; CHECK-NEXT: retq
Introduce element-wise atomic memcpy intrinsic This change adds a new intrinsic which is intended to provide memcpy functionality with additional atomicity guarantees. Please refer to the review thread or language reference for further details. Differential Revision: https://reviews.llvm.org/D27133 llvm-svn: 290708
2016-12-29 22:31:07 +08:00
%Dst = load i8*, i8** %Storage
%Src.addr = getelementptr i8*, i8** %Storage, i64 1
%Src = load i8*, i8** %Src.addr
[Atomics] Rename and change prototype for atomic memcpy intrinsic Summary: Background: http://lists.llvm.org/pipermail/llvm-dev/2017-May/112779.html This change is to alter the prototype for the atomic memcpy intrinsic. The prototype itself is being changed to more closely resemble the semantics and parameters of the llvm.memcpy intrinsic -- to ease later combination of the llvm.memcpy and atomic memcpy intrinsics. Furthermore, the name of the atomic memcpy intrinsic is being changed to make it clear that it is not a generic atomic memcpy, but specifically a memcpy is unordered atomic. Reviewers: reames, sanjoy, efriedma Reviewed By: reames Subscribers: mzolotukhin, anna, llvm-commits, skatkov Differential Revision: https://reviews.llvm.org/D33240 llvm-svn: 305558
2017-06-16 22:43:59 +08:00
; 1st arg (%rdi)
; 2nd arg (%rsi)
; 3rd arg (%edx) -- length
Changing constants in a test (NFC) Summary: Changing the lengths of the atomic memory intrinsics in a test to make sure that they don't get lowered into loads/stores if/when expansion of these occurs in selectiondag. llvm-svn: 331800
2018-05-09 03:08:12 +08:00
call void @llvm.memcpy.element.unordered.atomic.p0i8.p0i8.i32(i8* align 4 %Dst, i8* align 4 %Src, i32 1024, i32 4)
ret void
Introduce element-wise atomic memcpy intrinsic This change adds a new intrinsic which is intended to provide memcpy functionality with additional atomicity guarantees. Please refer to the review thread or language reference for further details. Differential Revision: https://reviews.llvm.org/D27133 llvm-svn: 290708
2016-12-29 22:31:07 +08:00
}
[Tests] Rename tests before adding new ones llvm-svn: 360092
2019-05-07 06:16:55 +08:00
define i8* @test_memmove1_generic(i8* %P, i8* %Q) {
; CHECK-LABEL: test_memmove1_generic:
[Tests] Autogen a test in advance of updates llvm-svn: 360091
2019-05-07 06:12:07 +08:00
; CHECK: # %bb.0:
; CHECK-NEXT: pushq %rbx
; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: .cfi_offset %rbx, -16
; CHECK-NEXT: movq %rdi, %rbx
; CHECK-NEXT: movl $1024, %edx # imm = 0x400
; CHECK-NEXT: callq __llvm_memmove_element_unordered_atomic_1
; CHECK-NEXT: movq %rbx, %rax
; CHECK-NEXT: popq %rbx
; CHECK-NEXT: .cfi_def_cfa_offset 8
; CHECK-NEXT: retq
Changing constants in a test (NFC) Summary: Changing the lengths of the atomic memory intrinsics in a test to make sure that they don't get lowered into loads/stores if/when expansion of these occurs in selectiondag. llvm-svn: 331800
2018-05-09 03:08:12 +08:00
call void @llvm.memmove.element.unordered.atomic.p0i8.p0i8.i32(i8* align 4 %P, i8* align 4 %Q, i32 1024, i32 1)
Add element atomic memmove intrinsic Summary: Continuing the work from https://reviews.llvm.org/D33240, this change introduces an element unordered-atomic memmove intrinsic. This intrinsic is essentially memmove with the implementation requirement that all loads/stores used for the copy are done with unordered-atomic loads/stores of a given element size. Reviewers: eli.friedman, reames, mkazantsev, skatkov Reviewed By: reames Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D34884 llvm-svn: 307796
2017-07-12 23:25:26 +08:00
ret i8* %P
; 3rd arg (%edx) -- length
}
[Tests] Rename tests before adding new ones llvm-svn: 360092
2019-05-07 06:16:55 +08:00
define i8* @test_memmove2_generic(i8* %P, i8* %Q) {
; CHECK-LABEL: test_memmove2_generic:
[Tests] Autogen a test in advance of updates llvm-svn: 360091
2019-05-07 06:12:07 +08:00
; CHECK: # %bb.0:
; CHECK-NEXT: pushq %rbx
; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: .cfi_offset %rbx, -16
; CHECK-NEXT: movq %rdi, %rbx
; CHECK-NEXT: movl $1024, %edx # imm = 0x400
; CHECK-NEXT: callq __llvm_memmove_element_unordered_atomic_2
; CHECK-NEXT: movq %rbx, %rax
; CHECK-NEXT: popq %rbx
; CHECK-NEXT: .cfi_def_cfa_offset 8
; CHECK-NEXT: retq
Changing constants in a test (NFC) Summary: Changing the lengths of the atomic memory intrinsics in a test to make sure that they don't get lowered into loads/stores if/when expansion of these occurs in selectiondag. llvm-svn: 331800
2018-05-09 03:08:12 +08:00
call void @llvm.memmove.element.unordered.atomic.p0i8.p0i8.i32(i8* align 4 %P, i8* align 4 %Q, i32 1024, i32 2)
Add element atomic memmove intrinsic Summary: Continuing the work from https://reviews.llvm.org/D33240, this change introduces an element unordered-atomic memmove intrinsic. This intrinsic is essentially memmove with the implementation requirement that all loads/stores used for the copy are done with unordered-atomic loads/stores of a given element size. Reviewers: eli.friedman, reames, mkazantsev, skatkov Reviewed By: reames Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D34884 llvm-svn: 307796
2017-07-12 23:25:26 +08:00
ret i8* %P
; 3rd arg (%edx) -- length
}
[Tests] Rename tests before adding new ones llvm-svn: 360092
2019-05-07 06:16:55 +08:00
define i8* @test_memmove4_generic(i8* %P, i8* %Q) {
; CHECK-LABEL: test_memmove4_generic:
[Tests] Autogen a test in advance of updates llvm-svn: 360091
2019-05-07 06:12:07 +08:00
; CHECK: # %bb.0:
; CHECK-NEXT: pushq %rbx
; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: .cfi_offset %rbx, -16
; CHECK-NEXT: movq %rdi, %rbx
; CHECK-NEXT: movl $1024, %edx # imm = 0x400
; CHECK-NEXT: callq __llvm_memmove_element_unordered_atomic_4
; CHECK-NEXT: movq %rbx, %rax
; CHECK-NEXT: popq %rbx
; CHECK-NEXT: .cfi_def_cfa_offset 8
; CHECK-NEXT: retq
Changing constants in a test (NFC) Summary: Changing the lengths of the atomic memory intrinsics in a test to make sure that they don't get lowered into loads/stores if/when expansion of these occurs in selectiondag. llvm-svn: 331800
2018-05-09 03:08:12 +08:00
call void @llvm.memmove.element.unordered.atomic.p0i8.p0i8.i32(i8* align 4 %P, i8* align 4 %Q, i32 1024, i32 4)
Add element atomic memmove intrinsic Summary: Continuing the work from https://reviews.llvm.org/D33240, this change introduces an element unordered-atomic memmove intrinsic. This intrinsic is essentially memmove with the implementation requirement that all loads/stores used for the copy are done with unordered-atomic loads/stores of a given element size. Reviewers: eli.friedman, reames, mkazantsev, skatkov Reviewed By: reames Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D34884 llvm-svn: 307796
2017-07-12 23:25:26 +08:00
ret i8* %P
; 3rd arg (%edx) -- length
}
[Tests] Rename tests before adding new ones llvm-svn: 360092
2019-05-07 06:16:55 +08:00
define i8* @test_memmove8_generic(i8* %P, i8* %Q) {
; CHECK-LABEL: test_memmove8_generic:
[Tests] Autogen a test in advance of updates llvm-svn: 360091
2019-05-07 06:12:07 +08:00
; CHECK: # %bb.0:
; CHECK-NEXT: pushq %rbx
; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: .cfi_offset %rbx, -16
; CHECK-NEXT: movq %rdi, %rbx
; CHECK-NEXT: movl $1024, %edx # imm = 0x400
; CHECK-NEXT: callq __llvm_memmove_element_unordered_atomic_8
; CHECK-NEXT: movq %rbx, %rax
; CHECK-NEXT: popq %rbx
; CHECK-NEXT: .cfi_def_cfa_offset 8
; CHECK-NEXT: retq
Changing constants in a test (NFC) Summary: Changing the lengths of the atomic memory intrinsics in a test to make sure that they don't get lowered into loads/stores if/when expansion of these occurs in selectiondag. llvm-svn: 331800
2018-05-09 03:08:12 +08:00
call void @llvm.memmove.element.unordered.atomic.p0i8.p0i8.i32(i8* align 8 %P, i8* align 8 %Q, i32 1024, i32 8)
Add element atomic memmove intrinsic Summary: Continuing the work from https://reviews.llvm.org/D33240, this change introduces an element unordered-atomic memmove intrinsic. This intrinsic is essentially memmove with the implementation requirement that all loads/stores used for the copy are done with unordered-atomic loads/stores of a given element size. Reviewers: eli.friedman, reames, mkazantsev, skatkov Reviewed By: reames Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D34884 llvm-svn: 307796
2017-07-12 23:25:26 +08:00
ret i8* %P
; 3rd arg (%edx) -- length
}
[Tests] Rename tests before adding new ones llvm-svn: 360092
2019-05-07 06:16:55 +08:00
define i8* @test_memmove16_generic(i8* %P, i8* %Q) {
; CHECK-LABEL: test_memmove16_generic:
[Tests] Autogen a test in advance of updates llvm-svn: 360091
2019-05-07 06:12:07 +08:00
; CHECK: # %bb.0:
; CHECK-NEXT: pushq %rbx
; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: .cfi_offset %rbx, -16
; CHECK-NEXT: movq %rdi, %rbx
; CHECK-NEXT: movl $1024, %edx # imm = 0x400
; CHECK-NEXT: callq __llvm_memmove_element_unordered_atomic_16
; CHECK-NEXT: movq %rbx, %rax
; CHECK-NEXT: popq %rbx
; CHECK-NEXT: .cfi_def_cfa_offset 8
; CHECK-NEXT: retq
Changing constants in a test (NFC) Summary: Changing the lengths of the atomic memory intrinsics in a test to make sure that they don't get lowered into loads/stores if/when expansion of these occurs in selectiondag. llvm-svn: 331800
2018-05-09 03:08:12 +08:00
call void @llvm.memmove.element.unordered.atomic.p0i8.p0i8.i32(i8* align 16 %P, i8* align 16 %Q, i32 1024, i32 16)
Add element atomic memmove intrinsic Summary: Continuing the work from https://reviews.llvm.org/D33240, this change introduces an element unordered-atomic memmove intrinsic. This intrinsic is essentially memmove with the implementation requirement that all loads/stores used for the copy are done with unordered-atomic loads/stores of a given element size. Reviewers: eli.friedman, reames, mkazantsev, skatkov Reviewed By: reames Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D34884 llvm-svn: 307796
2017-07-12 23:25:26 +08:00
ret i8* %P
; 3rd arg (%edx) -- length
}
define void @test_memmove_args(i8** %Storage) {
[Tests] Autogen a test in advance of updates llvm-svn: 360091
2019-05-07 06:12:07 +08:00
; CHECK-LABEL: test_memmove_args:
; CHECK: # %bb.0:
; CHECK-NEXT: pushq %rax
; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: movq (%rdi), %rax
; CHECK-NEXT: movq 8(%rdi), %rsi
; CHECK-NEXT: movq %rax, %rdi
; CHECK-NEXT: movl $1024, %edx # imm = 0x400
; CHECK-NEXT: callq __llvm_memmove_element_unordered_atomic_4
; CHECK-NEXT: popq %rax
; CHECK-NEXT: .cfi_def_cfa_offset 8
; CHECK-NEXT: retq
Add element atomic memmove intrinsic Summary: Continuing the work from https://reviews.llvm.org/D33240, this change introduces an element unordered-atomic memmove intrinsic. This intrinsic is essentially memmove with the implementation requirement that all loads/stores used for the copy are done with unordered-atomic loads/stores of a given element size. Reviewers: eli.friedman, reames, mkazantsev, skatkov Reviewed By: reames Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D34884 llvm-svn: 307796
2017-07-12 23:25:26 +08:00
%Dst = load i8*, i8** %Storage
%Src.addr = getelementptr i8*, i8** %Storage, i64 1
%Src = load i8*, i8** %Src.addr
; 1st arg (%rdi)
; 2nd arg (%rsi)
; 3rd arg (%edx) -- length
Changing constants in a test (NFC) Summary: Changing the lengths of the atomic memory intrinsics in a test to make sure that they don't get lowered into loads/stores if/when expansion of these occurs in selectiondag. llvm-svn: 331800
2018-05-09 03:08:12 +08:00
call void @llvm.memmove.element.unordered.atomic.p0i8.p0i8.i32(i8* align 4 %Dst, i8* align 4 %Src, i32 1024, i32 4)
ret void
Add element atomic memmove intrinsic Summary: Continuing the work from https://reviews.llvm.org/D33240, this change introduces an element unordered-atomic memmove intrinsic. This intrinsic is essentially memmove with the implementation requirement that all loads/stores used for the copy are done with unordered-atomic loads/stores of a given element size. Reviewers: eli.friedman, reames, mkazantsev, skatkov Reviewed By: reames Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D34884 llvm-svn: 307796
2017-07-12 23:25:26 +08:00
}
[Tests] Rename tests before adding new ones llvm-svn: 360092
2019-05-07 06:16:55 +08:00
define i8* @test_memset1_generic(i8* %P, i8 %V) {
; CHECK-LABEL: test_memset1_generic:
[Tests] Autogen a test in advance of updates llvm-svn: 360091
2019-05-07 06:12:07 +08:00
; CHECK: # %bb.0:
; CHECK-NEXT: pushq %rbx
; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: .cfi_offset %rbx, -16
; CHECK-NEXT: movq %rdi, %rbx
; CHECK-NEXT: movl $1024, %edx # imm = 0x400
; CHECK-NEXT: callq __llvm_memset_element_unordered_atomic_1
; CHECK-NEXT: movq %rbx, %rax
; CHECK-NEXT: popq %rbx
; CHECK-NEXT: .cfi_def_cfa_offset 8
; CHECK-NEXT: retq
Changing constants in a test (NFC) Summary: Changing the lengths of the atomic memory intrinsics in a test to make sure that they don't get lowered into loads/stores if/when expansion of these occurs in selectiondag. llvm-svn: 331800
2018-05-09 03:08:12 +08:00
call void @llvm.memset.element.unordered.atomic.p0i8.i32(i8* align 1 %P, i8 %V, i32 1024, i32 1)
Add element atomic memset intrinsic Summary: Continuing the work from https://reviews.llvm.org/D33240, this change introduces an element unordered-atomic memset intrinsic. This intrinsic is essentially memset with the implementation requirement that all stores used for the assignment are done with unordered-atomic stores of a given element size. Reviewers: eli.friedman, reames, mkazantsev, skatkov Reviewed By: reames Subscribers: jfb, dschuff, sbc100, jgravelle-google, aheejin, efriedma, llvm-commits Differential Revision: https://reviews.llvm.org/D34885 llvm-svn: 307854
2017-07-13 05:57:23 +08:00
ret i8* %P
; 3rd arg (%edx) -- length
}
[Tests] Rename tests before adding new ones llvm-svn: 360092
2019-05-07 06:16:55 +08:00
define i8* @test_memset2_generic(i8* %P, i8 %V) {
; CHECK-LABEL: test_memset2_generic:
[Tests] Autogen a test in advance of updates llvm-svn: 360091
2019-05-07 06:12:07 +08:00
; CHECK: # %bb.0:
; CHECK-NEXT: pushq %rbx
; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: .cfi_offset %rbx, -16
; CHECK-NEXT: movq %rdi, %rbx
; CHECK-NEXT: movl $1024, %edx # imm = 0x400
; CHECK-NEXT: callq __llvm_memset_element_unordered_atomic_2
; CHECK-NEXT: movq %rbx, %rax
; CHECK-NEXT: popq %rbx
; CHECK-NEXT: .cfi_def_cfa_offset 8
; CHECK-NEXT: retq
Changing constants in a test (NFC) Summary: Changing the lengths of the atomic memory intrinsics in a test to make sure that they don't get lowered into loads/stores if/when expansion of these occurs in selectiondag. llvm-svn: 331800
2018-05-09 03:08:12 +08:00
call void @llvm.memset.element.unordered.atomic.p0i8.i32(i8* align 2 %P, i8 %V, i32 1024, i32 2)
Add element atomic memset intrinsic Summary: Continuing the work from https://reviews.llvm.org/D33240, this change introduces an element unordered-atomic memset intrinsic. This intrinsic is essentially memset with the implementation requirement that all stores used for the assignment are done with unordered-atomic stores of a given element size. Reviewers: eli.friedman, reames, mkazantsev, skatkov Reviewed By: reames Subscribers: jfb, dschuff, sbc100, jgravelle-google, aheejin, efriedma, llvm-commits Differential Revision: https://reviews.llvm.org/D34885 llvm-svn: 307854
2017-07-13 05:57:23 +08:00
ret i8* %P
; 3rd arg (%edx) -- length
}
[Tests] Rename tests before adding new ones llvm-svn: 360092
2019-05-07 06:16:55 +08:00
define i8* @test_memset4_generic(i8* %P, i8 %V) {
; CHECK-LABEL: test_memset4_generic:
[Tests] Autogen a test in advance of updates llvm-svn: 360091
2019-05-07 06:12:07 +08:00
; CHECK: # %bb.0:
; CHECK-NEXT: pushq %rbx
; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: .cfi_offset %rbx, -16
; CHECK-NEXT: movq %rdi, %rbx
; CHECK-NEXT: movl $1024, %edx # imm = 0x400
; CHECK-NEXT: callq __llvm_memset_element_unordered_atomic_4
; CHECK-NEXT: movq %rbx, %rax
; CHECK-NEXT: popq %rbx
; CHECK-NEXT: .cfi_def_cfa_offset 8
; CHECK-NEXT: retq
Changing constants in a test (NFC) Summary: Changing the lengths of the atomic memory intrinsics in a test to make sure that they don't get lowered into loads/stores if/when expansion of these occurs in selectiondag. llvm-svn: 331800
2018-05-09 03:08:12 +08:00
call void @llvm.memset.element.unordered.atomic.p0i8.i32(i8* align 4 %P, i8 %V, i32 1024, i32 4)
Add element atomic memset intrinsic Summary: Continuing the work from https://reviews.llvm.org/D33240, this change introduces an element unordered-atomic memset intrinsic. This intrinsic is essentially memset with the implementation requirement that all stores used for the assignment are done with unordered-atomic stores of a given element size. Reviewers: eli.friedman, reames, mkazantsev, skatkov Reviewed By: reames Subscribers: jfb, dschuff, sbc100, jgravelle-google, aheejin, efriedma, llvm-commits Differential Revision: https://reviews.llvm.org/D34885 llvm-svn: 307854
2017-07-13 05:57:23 +08:00
ret i8* %P
; 3rd arg (%edx) -- length
}
[Tests] Rename tests before adding new ones llvm-svn: 360092
2019-05-07 06:16:55 +08:00
define i8* @test_memset8_generic(i8* %P, i8 %V) {
; CHECK-LABEL: test_memset8_generic:
[Tests] Autogen a test in advance of updates llvm-svn: 360091
2019-05-07 06:12:07 +08:00
; CHECK: # %bb.0:
; CHECK-NEXT: pushq %rbx
; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: .cfi_offset %rbx, -16
; CHECK-NEXT: movq %rdi, %rbx
; CHECK-NEXT: movl $1024, %edx # imm = 0x400
; CHECK-NEXT: callq __llvm_memset_element_unordered_atomic_8
; CHECK-NEXT: movq %rbx, %rax
; CHECK-NEXT: popq %rbx
; CHECK-NEXT: .cfi_def_cfa_offset 8
; CHECK-NEXT: retq
Changing constants in a test (NFC) Summary: Changing the lengths of the atomic memory intrinsics in a test to make sure that they don't get lowered into loads/stores if/when expansion of these occurs in selectiondag. llvm-svn: 331800
2018-05-09 03:08:12 +08:00
call void @llvm.memset.element.unordered.atomic.p0i8.i32(i8* align 8 %P, i8 %V, i32 1024, i32 8)
Add element atomic memset intrinsic Summary: Continuing the work from https://reviews.llvm.org/D33240, this change introduces an element unordered-atomic memset intrinsic. This intrinsic is essentially memset with the implementation requirement that all stores used for the assignment are done with unordered-atomic stores of a given element size. Reviewers: eli.friedman, reames, mkazantsev, skatkov Reviewed By: reames Subscribers: jfb, dschuff, sbc100, jgravelle-google, aheejin, efriedma, llvm-commits Differential Revision: https://reviews.llvm.org/D34885 llvm-svn: 307854
2017-07-13 05:57:23 +08:00
ret i8* %P
; 3rd arg (%edx) -- length
}
[Tests] Rename tests before adding new ones llvm-svn: 360092
2019-05-07 06:16:55 +08:00
define i8* @test_memset16_generic(i8* %P, i8 %V) {
; CHECK-LABEL: test_memset16_generic:
[Tests] Autogen a test in advance of updates llvm-svn: 360091
2019-05-07 06:12:07 +08:00
; CHECK: # %bb.0:
; CHECK-NEXT: pushq %rbx
; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: .cfi_offset %rbx, -16
; CHECK-NEXT: movq %rdi, %rbx
; CHECK-NEXT: movl $1024, %edx # imm = 0x400
; CHECK-NEXT: callq __llvm_memset_element_unordered_atomic_16
; CHECK-NEXT: movq %rbx, %rax
; CHECK-NEXT: popq %rbx
; CHECK-NEXT: .cfi_def_cfa_offset 8
; CHECK-NEXT: retq
Changing constants in a test (NFC) Summary: Changing the lengths of the atomic memory intrinsics in a test to make sure that they don't get lowered into loads/stores if/when expansion of these occurs in selectiondag. llvm-svn: 331800
2018-05-09 03:08:12 +08:00
call void @llvm.memset.element.unordered.atomic.p0i8.i32(i8* align 16 %P, i8 %V, i32 1024, i32 16)
Add element atomic memset intrinsic Summary: Continuing the work from https://reviews.llvm.org/D33240, this change introduces an element unordered-atomic memset intrinsic. This intrinsic is essentially memset with the implementation requirement that all stores used for the assignment are done with unordered-atomic stores of a given element size. Reviewers: eli.friedman, reames, mkazantsev, skatkov Reviewed By: reames Subscribers: jfb, dschuff, sbc100, jgravelle-google, aheejin, efriedma, llvm-commits Differential Revision: https://reviews.llvm.org/D34885 llvm-svn: 307854
2017-07-13 05:57:23 +08:00
ret i8* %P
; 3rd arg (%edx) -- length
}
define void @test_memset_args(i8** %Storage, i8* %V) {
[Tests] Autogen a test in advance of updates llvm-svn: 360091
2019-05-07 06:12:07 +08:00
; CHECK-LABEL: test_memset_args:
; CHECK: # %bb.0:
; CHECK-NEXT: pushq %rax
; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: movq (%rdi), %rdi
; CHECK-NEXT: movzbl (%rsi), %esi
; CHECK-NEXT: movl $1024, %edx # imm = 0x400
; CHECK-NEXT: callq __llvm_memset_element_unordered_atomic_4
; CHECK-NEXT: popq %rax
; CHECK-NEXT: .cfi_def_cfa_offset 8
; CHECK-NEXT: retq
Add element atomic memset intrinsic Summary: Continuing the work from https://reviews.llvm.org/D33240, this change introduces an element unordered-atomic memset intrinsic. This intrinsic is essentially memset with the implementation requirement that all stores used for the assignment are done with unordered-atomic stores of a given element size. Reviewers: eli.friedman, reames, mkazantsev, skatkov Reviewed By: reames Subscribers: jfb, dschuff, sbc100, jgravelle-google, aheejin, efriedma, llvm-commits Differential Revision: https://reviews.llvm.org/D34885 llvm-svn: 307854
2017-07-13 05:57:23 +08:00
%Dst = load i8*, i8** %Storage
%Val = load i8, i8* %V
; 1st arg (%rdi)
; 2nd arg (%rsi)
; 3rd arg (%edx) -- length
Changing constants in a test (NFC) Summary: Changing the lengths of the atomic memory intrinsics in a test to make sure that they don't get lowered into loads/stores if/when expansion of these occurs in selectiondag. llvm-svn: 331800
2018-05-09 03:08:12 +08:00
call void @llvm.memset.element.unordered.atomic.p0i8.i32(i8* align 4 %Dst, i8 %Val, i32 1024, i32 4)
ret void
Add element atomic memset intrinsic Summary: Continuing the work from https://reviews.llvm.org/D33240, this change introduces an element unordered-atomic memset intrinsic. This intrinsic is essentially memset with the implementation requirement that all stores used for the assignment are done with unordered-atomic stores of a given element size. Reviewers: eli.friedman, reames, mkazantsev, skatkov Reviewed By: reames Subscribers: jfb, dschuff, sbc100, jgravelle-google, aheejin, efriedma, llvm-commits Differential Revision: https://reviews.llvm.org/D34885 llvm-svn: 307854
2017-07-13 05:57:23 +08:00
}
[Tests] Add tests for optimized lowerings of element.unordered.atomic memset/memcmove/memcopy llvm-svn: 360093
2019-05-07 06:25:59 +08:00
;; Next batch of tests are cases where we could profitably lower to
;; atomic loads and stores directly, just as we do for non-atomic ones for
;; non element.unorderered.atomic variants.
define i8* @test_memcpy1_64(i8* %P, i8* %Q) {
; CHECK-LABEL: test_memcpy1_64:
; CHECK: # %bb.0:
; CHECK-NEXT: pushq %rbx
; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: .cfi_offset %rbx, -16
; CHECK-NEXT: movq %rdi, %rbx
; CHECK-NEXT: movl $64, %edx
; CHECK-NEXT: callq __llvm_memcpy_element_unordered_atomic_1
; CHECK-NEXT: movq %rbx, %rax
; CHECK-NEXT: popq %rbx
; CHECK-NEXT: .cfi_def_cfa_offset 8
; CHECK-NEXT: retq
call void @llvm.memcpy.element.unordered.atomic.p0i8.p0i8.i32(i8* align 1 %P, i8* align 1 %Q, i32 64, i32 1)
ret i8* %P
}
; Ensure align 16 generates vector load/stores even with small element size
define i8* @test_memcpy1_64_align4(i8* %P, i8* %Q) {
; CHECK-LABEL: test_memcpy1_64_align4:
; CHECK: # %bb.0:
; CHECK-NEXT: pushq %rbx
; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: .cfi_offset %rbx, -16
; CHECK-NEXT: movq %rdi, %rbx
; CHECK-NEXT: movl $64, %edx
; CHECK-NEXT: callq __llvm_memcpy_element_unordered_atomic_1
; CHECK-NEXT: movq %rbx, %rax
; CHECK-NEXT: popq %rbx
; CHECK-NEXT: .cfi_def_cfa_offset 8
; CHECK-NEXT: retq
call void @llvm.memcpy.element.unordered.atomic.p0i8.p0i8.i32(i8* align 4 %P, i8* align 4 %Q, i32 64, i32 1)
ret i8* %P
}
define i8* @test_memcpy1_64_align8(i8* %P, i8* %Q) {
; CHECK-LABEL: test_memcpy1_64_align8:
; CHECK: # %bb.0:
; CHECK-NEXT: pushq %rbx
; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: .cfi_offset %rbx, -16
; CHECK-NEXT: movq %rdi, %rbx
; CHECK-NEXT: movl $64, %edx
; CHECK-NEXT: callq __llvm_memcpy_element_unordered_atomic_1
; CHECK-NEXT: movq %rbx, %rax
; CHECK-NEXT: popq %rbx
; CHECK-NEXT: .cfi_def_cfa_offset 8
; CHECK-NEXT: retq
call void @llvm.memcpy.element.unordered.atomic.p0i8.p0i8.i32(i8* align 8 %P, i8* align 8 %Q, i32 64, i32 1)
ret i8* %P
}
define i8* @test_memcpy1_64_align16(i8* %P, i8* %Q) {
; CHECK-LABEL: test_memcpy1_64_align16:
; CHECK: # %bb.0:
; CHECK-NEXT: pushq %rbx
; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: .cfi_offset %rbx, -16
; CHECK-NEXT: movq %rdi, %rbx
; CHECK-NEXT: movl $64, %edx
; CHECK-NEXT: callq __llvm_memcpy_element_unordered_atomic_1
; CHECK-NEXT: movq %rbx, %rax
; CHECK-NEXT: popq %rbx
; CHECK-NEXT: .cfi_def_cfa_offset 8
; CHECK-NEXT: retq
call void @llvm.memcpy.element.unordered.atomic.p0i8.p0i8.i32(i8* align 16 %P, i8* align 16 %Q, i32 64, i32 1)
ret i8* %P
}
; Make sure that different source & dest alignments are handled correctly.
define i8* @test_memcpy1_64_diff_aligns(i8* %P, i8* %Q) {
; CHECK-LABEL: test_memcpy1_64_diff_aligns:
; CHECK: # %bb.0:
; CHECK-NEXT: pushq %rbx
; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: .cfi_offset %rbx, -16
; CHECK-NEXT: movq %rdi, %rbx
; CHECK-NEXT: movl $64, %edx
; CHECK-NEXT: callq __llvm_memcpy_element_unordered_atomic_1
; CHECK-NEXT: movq %rbx, %rax
; CHECK-NEXT: popq %rbx
; CHECK-NEXT: .cfi_def_cfa_offset 8
; CHECK-NEXT: retq
call void @llvm.memcpy.element.unordered.atomic.p0i8.p0i8.i32(i8* align 1 %P, i8* align 16 %Q, i32 64, i32 1)
ret i8* %P
}
define i8* @test_memcpy2_64(i8* %P, i8* %Q) {
; CHECK-LABEL: test_memcpy2_64:
; CHECK: # %bb.0:
; CHECK-NEXT: pushq %rbx
; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: .cfi_offset %rbx, -16
; CHECK-NEXT: movq %rdi, %rbx
; CHECK-NEXT: movl $64, %edx
; CHECK-NEXT: callq __llvm_memcpy_element_unordered_atomic_2
; CHECK-NEXT: movq %rbx, %rax
; CHECK-NEXT: popq %rbx
; CHECK-NEXT: .cfi_def_cfa_offset 8
; CHECK-NEXT: retq
call void @llvm.memcpy.element.unordered.atomic.p0i8.p0i8.i32(i8* align 2 %P, i8* align 2 %Q, i32 64, i32 2)
ret i8* %P
}
define i8* @test_memcpy4_64(i8* %P, i8* %Q) {
; CHECK-LABEL: test_memcpy4_64:
; CHECK: # %bb.0:
; CHECK-NEXT: pushq %rbx
; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: .cfi_offset %rbx, -16
; CHECK-NEXT: movq %rdi, %rbx
; CHECK-NEXT: movl $64, %edx
; CHECK-NEXT: callq __llvm_memcpy_element_unordered_atomic_4
; CHECK-NEXT: movq %rbx, %rax
; CHECK-NEXT: popq %rbx
; CHECK-NEXT: .cfi_def_cfa_offset 8
; CHECK-NEXT: retq
call void @llvm.memcpy.element.unordered.atomic.p0i8.p0i8.i32(i8* align 4 %P, i8* align 4 %Q, i32 64, i32 4)
ret i8* %P
}
define i8* @test_memcpy8_64(i8* %P, i8* %Q) {
; CHECK-LABEL: test_memcpy8_64:
; CHECK: # %bb.0:
; CHECK-NEXT: pushq %rbx
; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: .cfi_offset %rbx, -16
; CHECK-NEXT: movq %rdi, %rbx
; CHECK-NEXT: movl $64, %edx
; CHECK-NEXT: callq __llvm_memcpy_element_unordered_atomic_8
; CHECK-NEXT: movq %rbx, %rax
; CHECK-NEXT: popq %rbx
; CHECK-NEXT: .cfi_def_cfa_offset 8
; CHECK-NEXT: retq
call void @llvm.memcpy.element.unordered.atomic.p0i8.p0i8.i32(i8* align 8 %P, i8* align 8 %Q, i32 64, i32 8)
ret i8* %P
}
define i8* @test_memcpy16_64(i8* %P, i8* %Q) {
; CHECK-LABEL: test_memcpy16_64:
; CHECK: # %bb.0:
; CHECK-NEXT: pushq %rbx
; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: .cfi_offset %rbx, -16
; CHECK-NEXT: movq %rdi, %rbx
; CHECK-NEXT: movl $64, %edx
; CHECK-NEXT: callq __llvm_memcpy_element_unordered_atomic_16
; CHECK-NEXT: movq %rbx, %rax
; CHECK-NEXT: popq %rbx
; CHECK-NEXT: .cfi_def_cfa_offset 8
; CHECK-NEXT: retq
call void @llvm.memcpy.element.unordered.atomic.p0i8.p0i8.i32(i8* align 16 %P, i8* align 16 %Q, i32 64, i32 16)
ret i8* %P
}
; ==================================
define i8* @test_memmove1_64(i8* %P, i8* %Q) {
; CHECK-LABEL: test_memmove1_64:
; CHECK: # %bb.0:
; CHECK-NEXT: pushq %rbx
; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: .cfi_offset %rbx, -16
; CHECK-NEXT: movq %rdi, %rbx
; CHECK-NEXT: movl $64, %edx
; CHECK-NEXT: callq __llvm_memmove_element_unordered_atomic_1
; CHECK-NEXT: movq %rbx, %rax
; CHECK-NEXT: popq %rbx
; CHECK-NEXT: .cfi_def_cfa_offset 8
; CHECK-NEXT: retq
call void @llvm.memmove.element.unordered.atomic.p0i8.p0i8.i32(i8* align 1 %P, i8* align 1 %Q, i32 64, i32 1)
ret i8* %P
}
; Ensure align 16 generates vector load/stores even with small element size
define i8* @test_memmove1_64_align16(i8* %P, i8* %Q) {
; CHECK-LABEL: test_memmove1_64_align16:
; CHECK: # %bb.0:
; CHECK-NEXT: pushq %rbx
; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: .cfi_offset %rbx, -16
; CHECK-NEXT: movq %rdi, %rbx
; CHECK-NEXT: movl $64, %edx
; CHECK-NEXT: callq __llvm_memmove_element_unordered_atomic_1
; CHECK-NEXT: movq %rbx, %rax
; CHECK-NEXT: popq %rbx
; CHECK-NEXT: .cfi_def_cfa_offset 8
; CHECK-NEXT: retq
call void @llvm.memmove.element.unordered.atomic.p0i8.p0i8.i32(i8* align 16 %P, i8* align 16 %Q, i32 64, i32 1)
ret i8* %P
}
; Make sure that different source & dest alignments are handled correctly.
define i8* @test_memmove1_64_diff_aligns(i8* %P, i8* %Q) {
; CHECK-LABEL: test_memmove1_64_diff_aligns:
; CHECK: # %bb.0:
; CHECK-NEXT: pushq %rbx
; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: .cfi_offset %rbx, -16
; CHECK-NEXT: movq %rdi, %rbx
; CHECK-NEXT: movl $64, %edx
; CHECK-NEXT: callq __llvm_memmove_element_unordered_atomic_1
; CHECK-NEXT: movq %rbx, %rax
; CHECK-NEXT: popq %rbx
; CHECK-NEXT: .cfi_def_cfa_offset 8
; CHECK-NEXT: retq
call void @llvm.memmove.element.unordered.atomic.p0i8.p0i8.i32(i8* align 1 %P, i8* align 16 %Q, i32 64, i32 1)
ret i8* %P
}
define i8* @test_memmove2_64(i8* %P, i8* %Q) {
; CHECK-LABEL: test_memmove2_64:
; CHECK: # %bb.0:
; CHECK-NEXT: pushq %rbx
; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: .cfi_offset %rbx, -16
; CHECK-NEXT: movq %rdi, %rbx
; CHECK-NEXT: movl $64, %edx
; CHECK-NEXT: callq __llvm_memmove_element_unordered_atomic_2
; CHECK-NEXT: movq %rbx, %rax
; CHECK-NEXT: popq %rbx
; CHECK-NEXT: .cfi_def_cfa_offset 8
; CHECK-NEXT: retq
call void @llvm.memmove.element.unordered.atomic.p0i8.p0i8.i32(i8* align 2 %P, i8* align 2 %Q, i32 64, i32 2)
ret i8* %P
}
define i8* @test_memmove4_64(i8* %P, i8* %Q) {
; CHECK-LABEL: test_memmove4_64:
; CHECK: # %bb.0:
; CHECK-NEXT: pushq %rbx
; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: .cfi_offset %rbx, -16
; CHECK-NEXT: movq %rdi, %rbx
; CHECK-NEXT: movl $64, %edx
; CHECK-NEXT: callq __llvm_memmove_element_unordered_atomic_4
; CHECK-NEXT: movq %rbx, %rax
; CHECK-NEXT: popq %rbx
; CHECK-NEXT: .cfi_def_cfa_offset 8
; CHECK-NEXT: retq
call void @llvm.memmove.element.unordered.atomic.p0i8.p0i8.i32(i8* align 4 %P, i8* align 4 %Q, i32 64, i32 4)
ret i8* %P
}
define i8* @test_memmove8_64(i8* %P, i8* %Q) {
; CHECK-LABEL: test_memmove8_64:
; CHECK: # %bb.0:
; CHECK-NEXT: pushq %rbx
; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: .cfi_offset %rbx, -16
; CHECK-NEXT: movq %rdi, %rbx
; CHECK-NEXT: movl $64, %edx
; CHECK-NEXT: callq __llvm_memmove_element_unordered_atomic_8
; CHECK-NEXT: movq %rbx, %rax
; CHECK-NEXT: popq %rbx
; CHECK-NEXT: .cfi_def_cfa_offset 8
; CHECK-NEXT: retq
call void @llvm.memmove.element.unordered.atomic.p0i8.p0i8.i32(i8* align 8 %P, i8* align 8 %Q, i32 64, i32 8)
ret i8* %P
}
define i8* @test_memmove16_64(i8* %P, i8* %Q) {
; CHECK-LABEL: test_memmove16_64:
; CHECK: # %bb.0:
; CHECK-NEXT: pushq %rbx
; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: .cfi_offset %rbx, -16
; CHECK-NEXT: movq %rdi, %rbx
; CHECK-NEXT: movl $64, %edx
; CHECK-NEXT: callq __llvm_memmove_element_unordered_atomic_16
; CHECK-NEXT: movq %rbx, %rax
; CHECK-NEXT: popq %rbx
; CHECK-NEXT: .cfi_def_cfa_offset 8
; CHECK-NEXT: retq
call void @llvm.memmove.element.unordered.atomic.p0i8.p0i8.i32(i8* align 16 %P, i8* align 16 %Q, i32 64, i32 16)
ret i8* %P
}
; ==============================
define i8* @test_memset1_64(i8* %P, i8 %V) {
; CHECK-LABEL: test_memset1_64:
; CHECK: # %bb.0:
; CHECK-NEXT: pushq %rbx
; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: .cfi_offset %rbx, -16
; CHECK-NEXT: movq %rdi, %rbx
; CHECK-NEXT: movl $64, %edx
; CHECK-NEXT: callq __llvm_memset_element_unordered_atomic_1
; CHECK-NEXT: movq %rbx, %rax
; CHECK-NEXT: popq %rbx
; CHECK-NEXT: .cfi_def_cfa_offset 8
; CHECK-NEXT: retq
call void @llvm.memset.element.unordered.atomic.p0i8.i32(i8* align 1 %P, i8 %V, i32 64, i32 1)
ret i8* %P
}
define i8* @test_memset1_64_align16(i8* %P, i8 %V) {
; CHECK-LABEL: test_memset1_64_align16:
; CHECK: # %bb.0:
; CHECK-NEXT: pushq %rbx
; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: .cfi_offset %rbx, -16
; CHECK-NEXT: movq %rdi, %rbx
; CHECK-NEXT: movl $64, %edx
; CHECK-NEXT: callq __llvm_memset_element_unordered_atomic_1
; CHECK-NEXT: movq %rbx, %rax
; CHECK-NEXT: popq %rbx
; CHECK-NEXT: .cfi_def_cfa_offset 8
; CHECK-NEXT: retq
call void @llvm.memset.element.unordered.atomic.p0i8.i32(i8* align 16 %P, i8 %V, i32 64, i32 1)
ret i8* %P
}
define i8* @test_memset2_64(i8* %P, i8 %V) {
; CHECK-LABEL: test_memset2_64:
; CHECK: # %bb.0:
; CHECK-NEXT: pushq %rbx
; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: .cfi_offset %rbx, -16
; CHECK-NEXT: movq %rdi, %rbx
; CHECK-NEXT: movl $64, %edx
; CHECK-NEXT: callq __llvm_memset_element_unordered_atomic_2
; CHECK-NEXT: movq %rbx, %rax
; CHECK-NEXT: popq %rbx
; CHECK-NEXT: .cfi_def_cfa_offset 8
; CHECK-NEXT: retq
call void @llvm.memset.element.unordered.atomic.p0i8.i32(i8* align 2 %P, i8 %V, i32 64, i32 2)
ret i8* %P
}
[Tests] Yet more combination of tests for unordered.atomic memset llvm-svn: 360177
2019-05-08 01:45:52 +08:00
;; Use the memset4 case to explore alignment and sizing requirements in the
;; lowering
[Tests] Add tests for optimized lowerings of element.unordered.atomic memset/memcmove/memcopy llvm-svn: 360093
2019-05-07 06:25:59 +08:00
define i8* @test_memset4_64(i8* %P, i8 %V) {
; CHECK-LABEL: test_memset4_64:
; CHECK: # %bb.0:
; CHECK-NEXT: pushq %rbx
; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: .cfi_offset %rbx, -16
; CHECK-NEXT: movq %rdi, %rbx
; CHECK-NEXT: movl $64, %edx
; CHECK-NEXT: callq __llvm_memset_element_unordered_atomic_4
; CHECK-NEXT: movq %rbx, %rax
; CHECK-NEXT: popq %rbx
; CHECK-NEXT: .cfi_def_cfa_offset 8
; CHECK-NEXT: retq
call void @llvm.memset.element.unordered.atomic.p0i8.i32(i8* align 4 %P, i8 %V, i32 64, i32 4)
ret i8* %P
}
[Tests] Yet more combination of tests for unordered.atomic memset llvm-svn: 360177
2019-05-08 01:45:52 +08:00
define i8* @test_memset4_64_align8(i8* %P, i8 %V) {
; CHECK-LABEL: test_memset4_64_align8:
; CHECK: # %bb.0:
; CHECK-NEXT: pushq %rbx
; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: .cfi_offset %rbx, -16
; CHECK-NEXT: movq %rdi, %rbx
; CHECK-NEXT: movl $64, %edx
; CHECK-NEXT: callq __llvm_memset_element_unordered_atomic_4
; CHECK-NEXT: movq %rbx, %rax
; CHECK-NEXT: popq %rbx
; CHECK-NEXT: .cfi_def_cfa_offset 8
; CHECK-NEXT: retq
call void @llvm.memset.element.unordered.atomic.p0i8.i32(i8* align 8 %P, i8 %V, i32 64, i32 4)
ret i8* %P
}
define i8* @test_memset4_64_align16(i8* %P, i8 %V) {
; CHECK-LABEL: test_memset4_64_align16:
; CHECK: # %bb.0:
; CHECK-NEXT: pushq %rbx
; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: .cfi_offset %rbx, -16
; CHECK-NEXT: movq %rdi, %rbx
; CHECK-NEXT: movl $64, %edx
; CHECK-NEXT: callq __llvm_memset_element_unordered_atomic_4
; CHECK-NEXT: movq %rbx, %rax
; CHECK-NEXT: popq %rbx
; CHECK-NEXT: .cfi_def_cfa_offset 8
; CHECK-NEXT: retq
call void @llvm.memset.element.unordered.atomic.p0i8.i32(i8* align 16 %P, i8 %V, i32 64, i32 4)
ret i8* %P
}
define i8* @test_memset4_64_align64(i8* %P, i8 %V) {
; CHECK-LABEL: test_memset4_64_align64:
; CHECK: # %bb.0:
; CHECK-NEXT: pushq %rbx
; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: .cfi_offset %rbx, -16
; CHECK-NEXT: movq %rdi, %rbx
; CHECK-NEXT: movl $64, %edx
; CHECK-NEXT: callq __llvm_memset_element_unordered_atomic_4
; CHECK-NEXT: movq %rbx, %rax
; CHECK-NEXT: popq %rbx
; CHECK-NEXT: .cfi_def_cfa_offset 8
; CHECK-NEXT: retq
call void @llvm.memset.element.unordered.atomic.p0i8.i32(i8* align 64 %P, i8 %V, i32 64, i32 4)
ret i8* %P
}
define i8* @test_memset4_4(i8* %P, i8 %V) {
; CHECK-LABEL: test_memset4_4:
; CHECK: # %bb.0:
; CHECK-NEXT: pushq %rbx
; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: .cfi_offset %rbx, -16
; CHECK-NEXT: movq %rdi, %rbx
; CHECK-NEXT: movl $4, %edx
; CHECK-NEXT: callq __llvm_memset_element_unordered_atomic_4
; CHECK-NEXT: movq %rbx, %rax
; CHECK-NEXT: popq %rbx
; CHECK-NEXT: .cfi_def_cfa_offset 8
; CHECK-NEXT: retq
call void @llvm.memset.element.unordered.atomic.p0i8.i32(i8* align 4 %P, i8 %V, i32 4, i32 4)
ret i8* %P
}
define i8* @test_memset4_8(i8* %P, i8 %V) {
; CHECK-LABEL: test_memset4_8:
; CHECK: # %bb.0:
; CHECK-NEXT: pushq %rbx
; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: .cfi_offset %rbx, -16
; CHECK-NEXT: movq %rdi, %rbx
; CHECK-NEXT: movl $8, %edx
; CHECK-NEXT: callq __llvm_memset_element_unordered_atomic_4
; CHECK-NEXT: movq %rbx, %rax
; CHECK-NEXT: popq %rbx
; CHECK-NEXT: .cfi_def_cfa_offset 8
; CHECK-NEXT: retq
call void @llvm.memset.element.unordered.atomic.p0i8.i32(i8* align 4 %P, i8 %V, i32 8, i32 4)
ret i8* %P
}
define i8* @test_memset4_8_align8(i8* %P, i8 %V) {
; CHECK-LABEL: test_memset4_8_align8:
; CHECK: # %bb.0:
; CHECK-NEXT: pushq %rbx
; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: .cfi_offset %rbx, -16
; CHECK-NEXT: movq %rdi, %rbx
; CHECK-NEXT: movl $8, %edx
; CHECK-NEXT: callq __llvm_memset_element_unordered_atomic_4
; CHECK-NEXT: movq %rbx, %rax
; CHECK-NEXT: popq %rbx
; CHECK-NEXT: .cfi_def_cfa_offset 8
; CHECK-NEXT: retq
call void @llvm.memset.element.unordered.atomic.p0i8.i32(i8* align 8 %P, i8 %V, i32 8, i32 4)
ret i8* %P
}
[Tests] Add tests for optimized lowerings of element.unordered.atomic memset/memcmove/memcopy llvm-svn: 360093
2019-05-07 06:25:59 +08:00
define i8* @test_memset4_12(i8* %P, i8 %V) {
; CHECK-LABEL: test_memset4_12:
; CHECK: # %bb.0:
; CHECK-NEXT: pushq %rbx
; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: .cfi_offset %rbx, -16
; CHECK-NEXT: movq %rdi, %rbx
; CHECK-NEXT: movl $12, %edx
; CHECK-NEXT: callq __llvm_memset_element_unordered_atomic_4
; CHECK-NEXT: movq %rbx, %rax
; CHECK-NEXT: popq %rbx
; CHECK-NEXT: .cfi_def_cfa_offset 8
; CHECK-NEXT: retq
call void @llvm.memset.element.unordered.atomic.p0i8.i32(i8* align 4 %P, i8 %V, i32 12, i32 4)
ret i8* %P
}
define i8* @test_memset4_16(i8* %P, i8 %V) {
; CHECK-LABEL: test_memset4_16:
; CHECK: # %bb.0:
; CHECK-NEXT: pushq %rbx
; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: .cfi_offset %rbx, -16
; CHECK-NEXT: movq %rdi, %rbx
; CHECK-NEXT: movl $16, %edx
; CHECK-NEXT: callq __llvm_memset_element_unordered_atomic_4
; CHECK-NEXT: movq %rbx, %rax
; CHECK-NEXT: popq %rbx
; CHECK-NEXT: .cfi_def_cfa_offset 8
; CHECK-NEXT: retq
call void @llvm.memset.element.unordered.atomic.p0i8.i32(i8* align 4 %P, i8 %V, i32 16, i32 4)
ret i8* %P
}
[Tests] Yet more combination of tests for unordered.atomic memset llvm-svn: 360177
2019-05-08 01:45:52 +08:00
define i8* @test_memset4_16_align16(i8* %P, i8 %V) {
; CHECK-LABEL: test_memset4_16_align16:
; CHECK: # %bb.0:
; CHECK-NEXT: pushq %rbx
; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: .cfi_offset %rbx, -16
; CHECK-NEXT: movq %rdi, %rbx
; CHECK-NEXT: movl $16, %edx
; CHECK-NEXT: callq __llvm_memset_element_unordered_atomic_4
; CHECK-NEXT: movq %rbx, %rax
; CHECK-NEXT: popq %rbx
; CHECK-NEXT: .cfi_def_cfa_offset 8
; CHECK-NEXT: retq
call void @llvm.memset.element.unordered.atomic.p0i8.i32(i8* align 16 %P, i8 %V, i32 16, i32 4)
ret i8* %P
}
[Tests] Add tests for optimized lowerings of element.unordered.atomic memset/memcmove/memcopy llvm-svn: 360093
2019-05-07 06:25:59 +08:00
define i8* @test_memset4_60(i8* %P, i8 %V) {
; CHECK-LABEL: test_memset4_60:
; CHECK: # %bb.0:
; CHECK-NEXT: pushq %rbx
; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: .cfi_offset %rbx, -16
; CHECK-NEXT: movq %rdi, %rbx
; CHECK-NEXT: movl $60, %edx
; CHECK-NEXT: callq __llvm_memset_element_unordered_atomic_4
; CHECK-NEXT: movq %rbx, %rax
; CHECK-NEXT: popq %rbx
; CHECK-NEXT: .cfi_def_cfa_offset 8
; CHECK-NEXT: retq
call void @llvm.memset.element.unordered.atomic.p0i8.i32(i8* align 4 %P, i8 %V, i32 60, i32 4)
ret i8* %P
}
define i8* @test_memset8_64(i8* %P, i8 %V) {
; CHECK-LABEL: test_memset8_64:
; CHECK: # %bb.0:
; CHECK-NEXT: pushq %rbx
; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: .cfi_offset %rbx, -16
; CHECK-NEXT: movq %rdi, %rbx
; CHECK-NEXT: movl $64, %edx
; CHECK-NEXT: callq __llvm_memset_element_unordered_atomic_8
; CHECK-NEXT: movq %rbx, %rax
; CHECK-NEXT: popq %rbx
; CHECK-NEXT: .cfi_def_cfa_offset 8
; CHECK-NEXT: retq
call void @llvm.memset.element.unordered.atomic.p0i8.i32(i8* align 8 %P, i8 %V, i32 64, i32 8)
ret i8* %P
}
define i8* @test_memset16_64(i8* %P, i8 %V) {
; CHECK-LABEL: test_memset16_64:
; CHECK: # %bb.0:
; CHECK-NEXT: pushq %rbx
; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: .cfi_offset %rbx, -16
; CHECK-NEXT: movq %rdi, %rbx
; CHECK-NEXT: movl $64, %edx
; CHECK-NEXT: callq __llvm_memset_element_unordered_atomic_16
; CHECK-NEXT: movq %rbx, %rax
; CHECK-NEXT: popq %rbx
; CHECK-NEXT: .cfi_def_cfa_offset 8
; CHECK-NEXT: retq
call void @llvm.memset.element.unordered.atomic.p0i8.i32(i8* align 16 %P, i8 %V, i32 64, i32 16)
ret i8* %P
}
define i8* @test_memset16_64_zero(i8* %P) {
; CHECK-LABEL: test_memset16_64_zero:
; CHECK: # %bb.0:
; CHECK-NEXT: pushq %rbx
; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: .cfi_offset %rbx, -16
; CHECK-NEXT: movq %rdi, %rbx
; CHECK-NEXT: xorl %esi, %esi
; CHECK-NEXT: movl $64, %edx
; CHECK-NEXT: callq __llvm_memset_element_unordered_atomic_16
; CHECK-NEXT: movq %rbx, %rax
; CHECK-NEXT: popq %rbx
; CHECK-NEXT: .cfi_def_cfa_offset 8
; CHECK-NEXT: retq
call void @llvm.memset.element.unordered.atomic.p0i8.i32(i8* align 16 %P, i8 0, i32 64, i32 16)
ret i8* %P
}
[Atomics] Rename and change prototype for atomic memcpy intrinsic Summary: Background: http://lists.llvm.org/pipermail/llvm-dev/2017-May/112779.html This change is to alter the prototype for the atomic memcpy intrinsic. The prototype itself is being changed to more closely resemble the semantics and parameters of the llvm.memcpy intrinsic -- to ease later combination of the llvm.memcpy and atomic memcpy intrinsics. Furthermore, the name of the atomic memcpy intrinsic is being changed to make it clear that it is not a generic atomic memcpy, but specifically a memcpy is unordered atomic. Reviewers: reames, sanjoy, efriedma Reviewed By: reames Subscribers: mzolotukhin, anna, llvm-commits, skatkov Differential Revision: https://reviews.llvm.org/D33240 llvm-svn: 305558
2017-06-16 22:43:59 +08:00
declare void @llvm.memcpy.element.unordered.atomic.p0i8.p0i8.i32(i8* nocapture, i8* nocapture, i32, i32) nounwind
Add element atomic memmove intrinsic Summary: Continuing the work from https://reviews.llvm.org/D33240, this change introduces an element unordered-atomic memmove intrinsic. This intrinsic is essentially memmove with the implementation requirement that all loads/stores used for the copy are done with unordered-atomic loads/stores of a given element size. Reviewers: eli.friedman, reames, mkazantsev, skatkov Reviewed By: reames Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D34884 llvm-svn: 307796
2017-07-12 23:25:26 +08:00
declare void @llvm.memmove.element.unordered.atomic.p0i8.p0i8.i32(i8* nocapture, i8* nocapture, i32, i32) nounwind
Add element atomic memset intrinsic Summary: Continuing the work from https://reviews.llvm.org/D33240, this change introduces an element unordered-atomic memset intrinsic. This intrinsic is essentially memset with the implementation requirement that all stores used for the assignment are done with unordered-atomic stores of a given element size. Reviewers: eli.friedman, reames, mkazantsev, skatkov Reviewed By: reames Subscribers: jfb, dschuff, sbc100, jgravelle-google, aheejin, efriedma, llvm-commits Differential Revision: https://reviews.llvm.org/D34885 llvm-svn: 307854
2017-07-13 05:57:23 +08:00
declare void @llvm.memset.element.unordered.atomic.p0i8.i32(i8* nocapture, i8, i32, i32) nounwind