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llvm-project/llvm/test/CodeGen/X86/vec_ss_load_fold.ll

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[X86][SSE] Regenerate scalar math load folding tests for 32 and 64 bit targets llvm-svn: 279630
2016-08-24 23:07:11 +08:00
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
[X86][SSE] Add MINSD/MAXSD/MINSS/MAXSS intrinsic scalar load folding support These are no different in load behaviour to the existing ADD/SUB/MUL/DIV scalar ops but were missing from isNonFoldablePartialRegisterLoad llvm-svn: 279652
2016-08-25 02:40:53 +08:00
; RUN: llc < %s -mtriple=i686-apple-darwin9 -mattr=+sse,+sse2,+sse4.1 | FileCheck %s --check-prefix=X32
; RUN: llc < %s -mtriple=x86_64-apple-darwin9 -mattr=+sse,+sse2,+sse4.1 | FileCheck %s --check-prefix=X64
[X86] Add AVX and AVX512 command lines to the vec_ss_load_fold test. llvm-svn: 280645
2016-09-05 10:20:53 +08:00
; RUN: llc < %s -mtriple=i686-apple-darwin9 -mattr=+avx | FileCheck %s --check-prefix=X32_AVX
; RUN: llc < %s -mtriple=x86_64-apple-darwin9 -mattr=+avx | FileCheck %s --check-prefix=X64_AVX
; RUN: llc < %s -mtriple=i686-apple-darwin9 -mattr=+avx512f | FileCheck %s --check-prefix=X32_AVX
; RUN: llc < %s -mtriple=x86_64-apple-darwin9 -mattr=+avx512f | FileCheck %s --check-prefix=X64_AVX
new testcase llvm-svn: 30893
2006-10-12 06:07:38 +08:00
Add nounwind. llvm-svn: 50837
2008-05-08 06:59:08 +08:00
define i16 @test1(float %f) nounwind {
[X86][SSE] Regenerate scalar math load folding tests for 32 and 64 bit targets llvm-svn: 279630
2016-08-24 23:07:11 +08:00
; X32-LABEL: test1:
; X32: ## BB#0:
; X32-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
; X32-NEXT: xorps %xmm1, %xmm1
; X32-NEXT: subss LCPI0_0, %xmm0
; X32-NEXT: mulss LCPI0_1, %xmm0
[X86][SSE] Add MINSD/MAXSD/MINSS/MAXSS intrinsic scalar load folding support These are no different in load behaviour to the existing ADD/SUB/MUL/DIV scalar ops but were missing from isNonFoldablePartialRegisterLoad llvm-svn: 279652
2016-08-25 02:40:53 +08:00
; X32-NEXT: minss LCPI0_2, %xmm0
[X86][SSE] Regenerate scalar math load folding tests for 32 and 64 bit targets llvm-svn: 279630
2016-08-24 23:07:11 +08:00
; X32-NEXT: maxss %xmm1, %xmm0
; X32-NEXT: cvttss2si %xmm0, %eax
; X32-NEXT: ## kill: %AX<def> %AX<kill> %EAX<kill>
; X32-NEXT: retl
VirtRegMap: Replace some identity copies with KILL instructions. An identity COPY like this: %AL = COPY %AL, %EAX<imp-def> has no semantic effect, but encodes liveness information: Further users of %EAX only depend on this instruction even though it does not define the full register. Replace the COPY with a KILL instruction in those cases to maintain this liveness information. (This reverts a small part of r238588 but this time adds a comment explaining why a KILL instruction is useful). llvm-svn: 274952
2016-07-09 08:19:07 +08:00
;
[X86][SSE] Regenerate scalar math load folding tests for 32 and 64 bit targets llvm-svn: 279630
2016-08-24 23:07:11 +08:00
; X64-LABEL: test1:
; X64: ## BB#0:
; X64-NEXT: xorps %xmm1, %xmm1
; X64-NEXT: blendps {{.*#+}} xmm0 = xmm0[0],xmm1[1,2,3]
; X64-NEXT: subss {{.*}}(%rip), %xmm0
; X64-NEXT: mulss {{.*}}(%rip), %xmm0
[X86][SSE] Add MINSD/MAXSD/MINSS/MAXSS intrinsic scalar load folding support These are no different in load behaviour to the existing ADD/SUB/MUL/DIV scalar ops but were missing from isNonFoldablePartialRegisterLoad llvm-svn: 279652
2016-08-25 02:40:53 +08:00
; X64-NEXT: minss {{.*}}(%rip), %xmm0
[X86][SSE] Regenerate scalar math load folding tests for 32 and 64 bit targets llvm-svn: 279630
2016-08-24 23:07:11 +08:00
; X64-NEXT: maxss %xmm1, %xmm0
; X64-NEXT: cvttss2si %xmm0, %eax
; X64-NEXT: ## kill: %AX<def> %AX<kill> %EAX<kill>
; X64-NEXT: retq
[X86] Add AVX and AVX512 command lines to the vec_ss_load_fold test. llvm-svn: 280645
2016-09-05 10:20:53 +08:00
;
; X32_AVX-LABEL: test1:
; X32_AVX: ## BB#0:
; X32_AVX-NEXT: vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero
; X32_AVX-NEXT: vxorps %xmm1, %xmm1, %xmm1
; X32_AVX-NEXT: vsubss LCPI0_0, %xmm0, %xmm0
; X32_AVX-NEXT: vmulss LCPI0_1, %xmm0, %xmm0
; X32_AVX-NEXT: vminss LCPI0_2, %xmm0, %xmm0
; X32_AVX-NEXT: vmaxss %xmm1, %xmm0, %xmm0
; X32_AVX-NEXT: vcvttss2si %xmm0, %eax
; X32_AVX-NEXT: ## kill: %AX<def> %AX<kill> %EAX<kill>
; X32_AVX-NEXT: retl
;
; X64_AVX-LABEL: test1:
; X64_AVX: ## BB#0:
; X64_AVX-NEXT: vxorps %xmm1, %xmm1, %xmm1
; X64_AVX-NEXT: vmovss {{.*#+}} xmm0 = xmm0[0],xmm1[1,2,3]
; X64_AVX-NEXT: vsubss {{.*}}(%rip), %xmm0, %xmm0
; X64_AVX-NEXT: vmulss {{.*}}(%rip), %xmm0, %xmm0
; X64_AVX-NEXT: vminss {{.*}}(%rip), %xmm0, %xmm0
; X64_AVX-NEXT: vmaxss %xmm1, %xmm0, %xmm0
; X64_AVX-NEXT: vcvttss2si %xmm0, %eax
; X64_AVX-NEXT: ## kill: %AX<def> %AX<kill> %EAX<kill>
; X64_AVX-NEXT: retq
VirtRegMap: Replace some identity copies with KILL instructions. An identity COPY like this: %AL = COPY %AL, %EAX<imp-def> has no semantic effect, but encodes liveness information: Further users of %EAX only depend on this instruction even though it does not define the full register. Replace the COPY with a KILL instruction in those cases to maintain this liveness information. (This reverts a small part of r238588 but this time adds a comment explaining why a KILL instruction is useful). llvm-svn: 274952
2016-07-09 08:19:07 +08:00
%tmp = insertelement <4 x float> undef, float %f, i32 0 ; <<4 x float>> [#uses=1]
%tmp10 = insertelement <4 x float> %tmp, float 0.000000e+00, i32 1 ; <<4 x float>> [#uses=1]
%tmp11 = insertelement <4 x float> %tmp10, float 0.000000e+00, i32 2 ; <<4 x float>> [#uses=1]
%tmp12 = insertelement <4 x float> %tmp11, float 0.000000e+00, i32 3 ; <<4 x float>> [#uses=1]
%tmp28 = tail call <4 x float> @llvm.x86.sse.sub.ss( <4 x float> %tmp12, <4 x float> < float 1.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00 > ) ; <<4 x float>> [#uses=1]
%tmp37 = tail call <4 x float> @llvm.x86.sse.mul.ss( <4 x float> %tmp28, <4 x float> < float 5.000000e-01, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00 > ) ; <<4 x float>> [#uses=1]
%tmp48 = tail call <4 x float> @llvm.x86.sse.min.ss( <4 x float> %tmp37, <4 x float> < float 6.553500e+04, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00 > ) ; <<4 x float>> [#uses=1]
%tmp59 = tail call <4 x float> @llvm.x86.sse.max.ss( <4 x float> %tmp48, <4 x float> zeroinitializer ) ; <<4 x float>> [#uses=1]
%tmp.upgrd.1 = tail call i32 @llvm.x86.sse.cvttss2si( <4 x float> %tmp59 ) ; <i32> [#uses=1]
%tmp69 = trunc i32 %tmp.upgrd.1 to i16 ; <i16> [#uses=1]
ret i16 %tmp69
new testcase llvm-svn: 30893
2006-10-12 06:07:38 +08:00
}
Add nounwind. llvm-svn: 50837
2008-05-08 06:59:08 +08:00
define i16 @test2(float %f) nounwind {
[X86][SSE] Regenerate scalar math load folding tests for 32 and 64 bit targets llvm-svn: 279630
2016-08-24 23:07:11 +08:00
; X32-LABEL: test2:
; X32: ## BB#0:
; X32-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
; X32-NEXT: addss LCPI1_0, %xmm0
; X32-NEXT: mulss LCPI1_1, %xmm0
; X32-NEXT: minss LCPI1_2, %xmm0
; X32-NEXT: xorps %xmm1, %xmm1
; X32-NEXT: maxss %xmm1, %xmm0
; X32-NEXT: cvttss2si %xmm0, %eax
; X32-NEXT: ## kill: %AX<def> %AX<kill> %EAX<kill>
; X32-NEXT: retl
VirtRegMap: Replace some identity copies with KILL instructions. An identity COPY like this: %AL = COPY %AL, %EAX<imp-def> has no semantic effect, but encodes liveness information: Further users of %EAX only depend on this instruction even though it does not define the full register. Replace the COPY with a KILL instruction in those cases to maintain this liveness information. (This reverts a small part of r238588 but this time adds a comment explaining why a KILL instruction is useful). llvm-svn: 274952
2016-07-09 08:19:07 +08:00
;
[X86][SSE] Regenerate scalar math load folding tests for 32 and 64 bit targets llvm-svn: 279630
2016-08-24 23:07:11 +08:00
; X64-LABEL: test2:
; X64: ## BB#0:
; X64-NEXT: addss {{.*}}(%rip), %xmm0
; X64-NEXT: mulss {{.*}}(%rip), %xmm0
; X64-NEXT: minss {{.*}}(%rip), %xmm0
; X64-NEXT: xorps %xmm1, %xmm1
; X64-NEXT: maxss %xmm1, %xmm0
; X64-NEXT: cvttss2si %xmm0, %eax
; X64-NEXT: ## kill: %AX<def> %AX<kill> %EAX<kill>
; X64-NEXT: retq
[X86] Add AVX and AVX512 command lines to the vec_ss_load_fold test. llvm-svn: 280645
2016-09-05 10:20:53 +08:00
;
; X32_AVX-LABEL: test2:
; X32_AVX: ## BB#0:
; X32_AVX-NEXT: vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero
; X32_AVX-NEXT: vaddss LCPI1_0, %xmm0, %xmm0
; X32_AVX-NEXT: vmulss LCPI1_1, %xmm0, %xmm0
; X32_AVX-NEXT: vminss LCPI1_2, %xmm0, %xmm0
; X32_AVX-NEXT: vxorps %xmm1, %xmm1, %xmm1
; X32_AVX-NEXT: vmaxss %xmm1, %xmm0, %xmm0
; X32_AVX-NEXT: vcvttss2si %xmm0, %eax
; X32_AVX-NEXT: ## kill: %AX<def> %AX<kill> %EAX<kill>
; X32_AVX-NEXT: retl
;
; X64_AVX-LABEL: test2:
; X64_AVX: ## BB#0:
; X64_AVX-NEXT: vaddss {{.*}}(%rip), %xmm0, %xmm0
; X64_AVX-NEXT: vmulss {{.*}}(%rip), %xmm0, %xmm0
; X64_AVX-NEXT: vminss {{.*}}(%rip), %xmm0, %xmm0
; X64_AVX-NEXT: vxorps %xmm1, %xmm1, %xmm1
; X64_AVX-NEXT: vmaxss %xmm1, %xmm0, %xmm0
; X64_AVX-NEXT: vcvttss2si %xmm0, %eax
; X64_AVX-NEXT: ## kill: %AX<def> %AX<kill> %EAX<kill>
; X64_AVX-NEXT: retq
VirtRegMap: Replace some identity copies with KILL instructions. An identity COPY like this: %AL = COPY %AL, %EAX<imp-def> has no semantic effect, but encodes liveness information: Further users of %EAX only depend on this instruction even though it does not define the full register. Replace the COPY with a KILL instruction in those cases to maintain this liveness information. (This reverts a small part of r238588 but this time adds a comment explaining why a KILL instruction is useful). llvm-svn: 274952
2016-07-09 08:19:07 +08:00
%tmp28 = fsub float %f, 1.000000e+00 ; <float> [#uses=1]
%tmp37 = fmul float %tmp28, 5.000000e-01 ; <float> [#uses=1]
%tmp375 = insertelement <4 x float> undef, float %tmp37, i32 0 ; <<4 x float>> [#uses=1]
%tmp48 = tail call <4 x float> @llvm.x86.sse.min.ss( <4 x float> %tmp375, <4 x float> < float 6.553500e+04, float undef, float undef, float undef > ) ; <<4 x float>> [#uses=1]
%tmp59 = tail call <4 x float> @llvm.x86.sse.max.ss( <4 x float> %tmp48, <4 x float> < float 0.000000e+00, float undef, float undef, float undef > ) ; <<4 x float>> [#uses=1]
%tmp = tail call i32 @llvm.x86.sse.cvttss2si( <4 x float> %tmp59 ) ; <i32> [#uses=1]
%tmp69 = trunc i32 %tmp to i16 ; <i16> [#uses=1]
ret i16 %tmp69
new testcase llvm-svn: 30893
2006-10-12 06:07:38 +08:00
}
Remove llvm-upgrade and update tests. llvm-svn: 47432
2008-02-21 15:42:26 +08:00
declare <4 x float> @llvm.x86.sse.sub.ss(<4 x float>, <4 x float>)
new testcase llvm-svn: 30893
2006-10-12 06:07:38 +08:00
Remove llvm-upgrade and update tests. llvm-svn: 47432
2008-02-21 15:42:26 +08:00
declare <4 x float> @llvm.x86.sse.mul.ss(<4 x float>, <4 x float>)
new testcase llvm-svn: 30893
2006-10-12 06:07:38 +08:00
Remove llvm-upgrade and update tests. llvm-svn: 47432
2008-02-21 15:42:26 +08:00
declare <4 x float> @llvm.x86.sse.min.ss(<4 x float>, <4 x float>)
new testcase llvm-svn: 30893
2006-10-12 06:07:38 +08:00
Remove llvm-upgrade and update tests. llvm-svn: 47432
2008-02-21 15:42:26 +08:00
declare <4 x float> @llvm.x86.sse.max.ss(<4 x float>, <4 x float>)
new testcase llvm-svn: 30893
2006-10-12 06:07:38 +08:00
Remove llvm-upgrade and update tests. llvm-svn: 47432
2008-02-21 15:42:26 +08:00
declare i32 @llvm.x86.sse.cvttss2si(<4 x float>)
fix rdar://7653908, a crash on a case where we would fold a load into a roundss intrinsic, producing a cyclic dag. The root cause of this is badness handling ComplexPattern nodes in the old dagisel that I noticed through inspection. Eliminate a copy of the of the code that handled ComplexPatterns by making EmitChildMatchCode call into EmitMatchCode. llvm-svn: 96408
2010-02-17 06:35:06 +08:00
declare <4 x float> @llvm.x86.sse41.round.ss(<4 x float>, <4 x float>, i32)
[X86][SSE] Regenerated scalar load folding tests llvm-svn: 270431
2016-05-23 20:53:09 +08:00
fix rdar://7653908, a crash on a case where we would fold a load into a roundss intrinsic, producing a cyclic dag. The root cause of this is badness handling ComplexPattern nodes in the old dagisel that I noticed through inspection. Eliminate a copy of the of the code that handled ComplexPatterns by making EmitChildMatchCode call into EmitMatchCode. llvm-svn: 96408
2010-02-17 06:35:06 +08:00
declare <4 x float> @f()
define <4 x float> @test3(<4 x float> %A, float *%b, i32 %C) nounwind {
[X86][SSE] Regenerate scalar math load folding tests for 32 and 64 bit targets llvm-svn: 279630
2016-08-24 23:07:11 +08:00
; X32-LABEL: test3:
; X32: ## BB#0:
; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
; X32-NEXT: roundss $4, (%eax), %xmm0
; X32-NEXT: retl
VirtRegMap: Replace some identity copies with KILL instructions. An identity COPY like this: %AL = COPY %AL, %EAX<imp-def> has no semantic effect, but encodes liveness information: Further users of %EAX only depend on this instruction even though it does not define the full register. Replace the COPY with a KILL instruction in those cases to maintain this liveness information. (This reverts a small part of r238588 but this time adds a comment explaining why a KILL instruction is useful). llvm-svn: 274952
2016-07-09 08:19:07 +08:00
;
[X86][SSE] Regenerate scalar math load folding tests for 32 and 64 bit targets llvm-svn: 279630
2016-08-24 23:07:11 +08:00
; X64-LABEL: test3:
; X64: ## BB#0:
; X64-NEXT: roundss $4, (%rdi), %xmm0
; X64-NEXT: retq
[X86] Add AVX and AVX512 command lines to the vec_ss_load_fold test. llvm-svn: 280645
2016-09-05 10:20:53 +08:00
;
; X32_AVX-LABEL: test3:
; X32_AVX: ## BB#0:
; X32_AVX-NEXT: movl {{[0-9]+}}(%esp), %eax
; X32_AVX-NEXT: vroundss $4, (%eax), %xmm0, %xmm0
; X32_AVX-NEXT: retl
;
; X64_AVX-LABEL: test3:
; X64_AVX: ## BB#0:
; X64_AVX-NEXT: vroundss $4, (%rdi), %xmm0, %xmm0
; X64_AVX-NEXT: retq
[opaque pointer type] Add textual IR support for explicit type parameter to load instruction Essentially the same as the GEP change in r230786. A similar migration script can be used to update test cases, though a few more test case improvements/changes were required this time around: (r229269-r229278) import fileinput import sys import re pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)") for line in sys.stdin: sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line)) Reviewers: rafael, dexonsmith, grosser Differential Revision: http://reviews.llvm.org/D7649 llvm-svn: 230794
2015-02-28 05:17:42 +08:00
%a = load float , float *%b
fix rdar://7653908, a crash on a case where we would fold a load into a roundss intrinsic, producing a cyclic dag. The root cause of this is badness handling ComplexPattern nodes in the old dagisel that I noticed through inspection. Eliminate a copy of the of the code that handled ComplexPatterns by making EmitChildMatchCode call into EmitMatchCode. llvm-svn: 96408
2010-02-17 06:35:06 +08:00
%B = insertelement <4 x float> undef, float %a, i32 0
%X = call <4 x float> @llvm.x86.sse41.round.ss(<4 x float> %A, <4 x float> %B, i32 4)
ret <4 x float> %X
}
define <4 x float> @test4(<4 x float> %A, float *%b, i32 %C) nounwind {
[X86][SSE] Regenerate scalar math load folding tests for 32 and 64 bit targets llvm-svn: 279630
2016-08-24 23:07:11 +08:00
; X32-LABEL: test4:
; X32: ## BB#0:
; X32-NEXT: subl $28, %esp
; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
; X32-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
; X32-NEXT: movaps %xmm0, (%esp) ## 16-byte Spill
; X32-NEXT: calll _f
; X32-NEXT: movaps (%esp), %xmm1 ## 16-byte Reload
; X32-NEXT: roundss $4, %xmm1, %xmm0
; X32-NEXT: addl $28, %esp
; X32-NEXT: retl
VirtRegMap: Replace some identity copies with KILL instructions. An identity COPY like this: %AL = COPY %AL, %EAX<imp-def> has no semantic effect, but encodes liveness information: Further users of %EAX only depend on this instruction even though it does not define the full register. Replace the COPY with a KILL instruction in those cases to maintain this liveness information. (This reverts a small part of r238588 but this time adds a comment explaining why a KILL instruction is useful). llvm-svn: 274952
2016-07-09 08:19:07 +08:00
;
[X86][SSE] Regenerate scalar math load folding tests for 32 and 64 bit targets llvm-svn: 279630
2016-08-24 23:07:11 +08:00
; X64-LABEL: test4:
; X64: ## BB#0:
; X64-NEXT: subq $24, %rsp
; X64-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
; X64-NEXT: movaps %xmm0, (%rsp) ## 16-byte Spill
; X64-NEXT: callq _f
; X64-NEXT: movaps (%rsp), %xmm1 ## 16-byte Reload
; X64-NEXT: roundss $4, %xmm1, %xmm0
; X64-NEXT: addq $24, %rsp
; X64-NEXT: retq
[X86] Add AVX and AVX512 command lines to the vec_ss_load_fold test. llvm-svn: 280645
2016-09-05 10:20:53 +08:00
;
; X32_AVX-LABEL: test4:
; X32_AVX: ## BB#0:
; X32_AVX-NEXT: subl $28, %esp
; X32_AVX-NEXT: movl {{[0-9]+}}(%esp), %eax
; X32_AVX-NEXT: vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero
; X32_AVX-NEXT: vmovaps %xmm0, (%esp) ## 16-byte Spill
; X32_AVX-NEXT: calll _f
; X32_AVX-NEXT: vroundss $4, (%esp), %xmm0, %xmm0 ## 16-byte Folded Reload
; X32_AVX-NEXT: addl $28, %esp
; X32_AVX-NEXT: retl
;
; X64_AVX-LABEL: test4:
; X64_AVX: ## BB#0:
; X64_AVX-NEXT: subq $24, %rsp
; X64_AVX-NEXT: vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero
; X64_AVX-NEXT: vmovaps %xmm0, (%rsp) ## 16-byte Spill
; X64_AVX-NEXT: callq _f
; X64_AVX-NEXT: vroundss $4, (%rsp), %xmm0, %xmm0 ## 16-byte Folded Reload
; X64_AVX-NEXT: addq $24, %rsp
; X64_AVX-NEXT: retq
[opaque pointer type] Add textual IR support for explicit type parameter to load instruction Essentially the same as the GEP change in r230786. A similar migration script can be used to update test cases, though a few more test case improvements/changes were required this time around: (r229269-r229278) import fileinput import sys import re pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)") for line in sys.stdin: sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line)) Reviewers: rafael, dexonsmith, grosser Differential Revision: http://reviews.llvm.org/D7649 llvm-svn: 230794
2015-02-28 05:17:42 +08:00
%a = load float , float *%b
fix rdar://7653908, a crash on a case where we would fold a load into a roundss intrinsic, producing a cyclic dag. The root cause of this is badness handling ComplexPattern nodes in the old dagisel that I noticed through inspection. Eliminate a copy of the of the code that handled ComplexPatterns by making EmitChildMatchCode call into EmitMatchCode. llvm-svn: 96408
2010-02-17 06:35:06 +08:00
%B = insertelement <4 x float> undef, float %a, i32 0
%q = call <4 x float> @f()
%X = call <4 x float> @llvm.x86.sse41.round.ss(<4 x float> %q, <4 x float> %B, i32 4)
ret <4 x float> %X
temporarily disable this. llvm-svn: 96717
2010-02-21 11:24:41 +08:00
}
X86: move Int_CVTSD2SSrr, Int_CVTSI2SSrr, Int_CVTSI2SDrr, Int_CVTSS2SDrr from OpTbl1 to OpTbl2 since they have 3 operands and the last operand can be changed to a memory operand. PR13576 llvm-svn: 161769
2012-08-14 02:29:41 +08:00
[X86][SSE] Regenerated scalar load folding tests llvm-svn: 270431
2016-05-23 20:53:09 +08:00
; PR13576
X86: move Int_CVTSD2SSrr, Int_CVTSI2SSrr, Int_CVTSI2SDrr, Int_CVTSS2SDrr from OpTbl1 to OpTbl2 since they have 3 operands and the last operand can be changed to a memory operand. PR13576 llvm-svn: 161769
2012-08-14 02:29:41 +08:00
define <2 x double> @test5() nounwind uwtable readnone noinline {
[X86][SSE] Regenerate scalar math load folding tests for 32 and 64 bit targets llvm-svn: 279630
2016-08-24 23:07:11 +08:00
; X32-LABEL: test5:
; X32: ## BB#0: ## %entry
; X32-NEXT: movaps {{.*#+}} xmm0 = [4.569870e+02,1.233210e+02]
; X32-NEXT: movl $128, %eax
; X32-NEXT: cvtsi2sdl %eax, %xmm0
; X32-NEXT: retl
VirtRegMap: Replace some identity copies with KILL instructions. An identity COPY like this: %AL = COPY %AL, %EAX<imp-def> has no semantic effect, but encodes liveness information: Further users of %EAX only depend on this instruction even though it does not define the full register. Replace the COPY with a KILL instruction in those cases to maintain this liveness information. (This reverts a small part of r238588 but this time adds a comment explaining why a KILL instruction is useful). llvm-svn: 274952
2016-07-09 08:19:07 +08:00
;
[X86][SSE] Regenerate scalar math load folding tests for 32 and 64 bit targets llvm-svn: 279630
2016-08-24 23:07:11 +08:00
; X64-LABEL: test5:
; X64: ## BB#0: ## %entry
; X64-NEXT: movaps {{.*#+}} xmm0 = [4.569870e+02,1.233210e+02]
; X64-NEXT: movl $128, %eax
; X64-NEXT: cvtsi2sdl %eax, %xmm0
; X64-NEXT: retq
[X86] Add AVX and AVX512 command lines to the vec_ss_load_fold test. llvm-svn: 280645
2016-09-05 10:20:53 +08:00
;
; X32_AVX-LABEL: test5:
; X32_AVX: ## BB#0: ## %entry
; X32_AVX-NEXT: vmovaps {{.*#+}} xmm0 = [4.569870e+02,1.233210e+02]
; X32_AVX-NEXT: movl $128, %eax
; X32_AVX-NEXT: vcvtsi2sdl %eax, %xmm0, %xmm0
; X32_AVX-NEXT: retl
;
; X64_AVX-LABEL: test5:
; X64_AVX: ## BB#0: ## %entry
; X64_AVX-NEXT: vmovaps {{.*#+}} xmm0 = [4.569870e+02,1.233210e+02]
; X64_AVX-NEXT: movl $128, %eax
; X64_AVX-NEXT: vcvtsi2sdl %eax, %xmm0, %xmm0
; X64_AVX-NEXT: retq
X86: move Int_CVTSD2SSrr, Int_CVTSI2SSrr, Int_CVTSI2SDrr, Int_CVTSS2SDrr from OpTbl1 to OpTbl2 since they have 3 operands and the last operand can be changed to a memory operand. PR13576 llvm-svn: 161769
2012-08-14 02:29:41 +08:00
entry:
[X86][SSE] Regenerate scalar math load folding tests for 32 and 64 bit targets llvm-svn: 279630
2016-08-24 23:07:11 +08:00
%0 = tail call <2 x double> @llvm.x86.sse2.cvtsi2sd(<2 x double> <double 4.569870e+02, double 1.233210e+02>, i32 128) nounwind readnone
X86: move Int_CVTSD2SSrr, Int_CVTSI2SSrr, Int_CVTSI2SDrr, Int_CVTSS2SDrr from OpTbl1 to OpTbl2 since they have 3 operands and the last operand can be changed to a memory operand. PR13576 llvm-svn: 161769
2012-08-14 02:29:41 +08:00
ret <2 x double> %0
}
declare <2 x double> @llvm.x86.sse2.cvtsi2sd(<2 x double>, i32) nounwind readnone
[X86][SSE] Add MINSD/MAXSD/MINSS/MAXSS intrinsic scalar load folding support These are no different in load behaviour to the existing ADD/SUB/MUL/DIV scalar ops but were missing from isNonFoldablePartialRegisterLoad llvm-svn: 279652
2016-08-25 02:40:53 +08:00
define <4 x float> @minss_fold(float* %x, <4 x float> %y) {
; X32-LABEL: minss_fold:
; X32: ## BB#0: ## %entry
; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
; X32-NEXT: minss (%eax), %xmm0
; X32-NEXT: retl
;
; X64-LABEL: minss_fold:
; X64: ## BB#0: ## %entry
; X64-NEXT: minss (%rdi), %xmm0
; X64-NEXT: retq
[X86] Add AVX and AVX512 command lines to the vec_ss_load_fold test. llvm-svn: 280645
2016-09-05 10:20:53 +08:00
;
; X32_AVX-LABEL: minss_fold:
; X32_AVX: ## BB#0: ## %entry
; X32_AVX-NEXT: movl {{[0-9]+}}(%esp), %eax
; X32_AVX-NEXT: vminss (%eax), %xmm0, %xmm0
; X32_AVX-NEXT: retl
;
; X64_AVX-LABEL: minss_fold:
; X64_AVX: ## BB#0: ## %entry
; X64_AVX-NEXT: vminss (%rdi), %xmm0, %xmm0
; X64_AVX-NEXT: retq
[X86][SSE] Add MINSD/MAXSD/MINSS/MAXSS intrinsic scalar load folding support These are no different in load behaviour to the existing ADD/SUB/MUL/DIV scalar ops but were missing from isNonFoldablePartialRegisterLoad llvm-svn: 279652
2016-08-25 02:40:53 +08:00
entry:
%0 = load float, float* %x, align 1
%vecinit.i = insertelement <4 x float> undef, float %0, i32 0
%vecinit2.i = insertelement <4 x float> %vecinit.i, float 0.000000e+00, i32 1
%vecinit3.i = insertelement <4 x float> %vecinit2.i, float 0.000000e+00, i32 2
%vecinit4.i = insertelement <4 x float> %vecinit3.i, float 0.000000e+00, i32 3
%1 = tail call <4 x float> @llvm.x86.sse.min.ss(<4 x float> %y, <4 x float> %vecinit4.i)
ret <4 x float> %1
}
define <4 x float> @maxss_fold(float* %x, <4 x float> %y) {
; X32-LABEL: maxss_fold:
; X32: ## BB#0: ## %entry
; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
; X32-NEXT: maxss (%eax), %xmm0
; X32-NEXT: retl
;
; X64-LABEL: maxss_fold:
; X64: ## BB#0: ## %entry
; X64-NEXT: maxss (%rdi), %xmm0
; X64-NEXT: retq
[X86] Add AVX and AVX512 command lines to the vec_ss_load_fold test. llvm-svn: 280645
2016-09-05 10:20:53 +08:00
;
; X32_AVX-LABEL: maxss_fold:
; X32_AVX: ## BB#0: ## %entry
; X32_AVX-NEXT: movl {{[0-9]+}}(%esp), %eax
; X32_AVX-NEXT: vmaxss (%eax), %xmm0, %xmm0
; X32_AVX-NEXT: retl
;
; X64_AVX-LABEL: maxss_fold:
; X64_AVX: ## BB#0: ## %entry
; X64_AVX-NEXT: vmaxss (%rdi), %xmm0, %xmm0
; X64_AVX-NEXT: retq
[X86][SSE] Add MINSD/MAXSD/MINSS/MAXSS intrinsic scalar load folding support These are no different in load behaviour to the existing ADD/SUB/MUL/DIV scalar ops but were missing from isNonFoldablePartialRegisterLoad llvm-svn: 279652
2016-08-25 02:40:53 +08:00
entry:
%0 = load float, float* %x, align 1
%vecinit.i = insertelement <4 x float> undef, float %0, i32 0
%vecinit2.i = insertelement <4 x float> %vecinit.i, float 0.000000e+00, i32 1
%vecinit3.i = insertelement <4 x float> %vecinit2.i, float 0.000000e+00, i32 2
%vecinit4.i = insertelement <4 x float> %vecinit3.i, float 0.000000e+00, i32 3
%1 = tail call <4 x float> @llvm.x86.sse.max.ss(<4 x float> %y, <4 x float> %vecinit4.i)
ret <4 x float> %1
}
[X86][SSE] Add CMPSS/CMPSD intrinsic scalar load folding support. llvm-svn: 279806
2016-08-26 15:08:00 +08:00
define <4 x float> @cmpss_fold(float* %x, <4 x float> %y) {
; X32-LABEL: cmpss_fold:
; X32: ## BB#0: ## %entry
; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
; X32-NEXT: cmpeqss (%eax), %xmm0
; X32-NEXT: retl
;
; X64-LABEL: cmpss_fold:
; X64: ## BB#0: ## %entry
; X64-NEXT: cmpeqss (%rdi), %xmm0
; X64-NEXT: retq
[X86] Add AVX and AVX512 command lines to the vec_ss_load_fold test. llvm-svn: 280645
2016-09-05 10:20:53 +08:00
;
; X32_AVX-LABEL: cmpss_fold:
; X32_AVX: ## BB#0: ## %entry
; X32_AVX-NEXT: movl {{[0-9]+}}(%esp), %eax
; X32_AVX-NEXT: vcmpeqss (%eax), %xmm0, %xmm0
; X32_AVX-NEXT: retl
;
; X64_AVX-LABEL: cmpss_fold:
; X64_AVX: ## BB#0: ## %entry
; X64_AVX-NEXT: vcmpeqss (%rdi), %xmm0, %xmm0
; X64_AVX-NEXT: retq
[X86][SSE] Add CMPSS/CMPSD intrinsic scalar load folding support. llvm-svn: 279806
2016-08-26 15:08:00 +08:00
entry:
%0 = load float, float* %x, align 1
%vecinit.i = insertelement <4 x float> undef, float %0, i32 0
%vecinit2.i = insertelement <4 x float> %vecinit.i, float 0.000000e+00, i32 1
%vecinit3.i = insertelement <4 x float> %vecinit2.i, float 0.000000e+00, i32 2
%vecinit4.i = insertelement <4 x float> %vecinit3.i, float 0.000000e+00, i32 3
%1 = tail call <4 x float> @llvm.x86.sse.cmp.ss(<4 x float> %y, <4 x float> %vecinit4.i, i8 0)
ret <4 x float> %1
}
declare <4 x float> @llvm.x86.sse.cmp.ss(<4 x float>, <4 x float>, i8) nounwind readnone