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llvm-project/llvm/test/CodeGen/X86/2011-10-21-widen-cmp.ll

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Make utils/update_llc_test_checks.py note that the assertions are autogenerated. Also update existing test cases which appear to be generated by it and weren't modified (other than addition of the header) by rerunning it. llvm-svn: 253917
2015-11-24 05:33:58 +08:00
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
[X86][SSE] Fixed arch/triple and regenerated results. Tidyup before diffs from new patch. llvm-svn: 253144
2015-11-15 04:42:01 +08:00
; RUN: llc < %s -mtriple=x86_64-unknown-linux-gnu -mcpu=corei7 | FileCheck %s
1. Fix the widening of SETCC in WidenVecOp_SETCC. Use the correct return CC type. 2. Fix a typo in CONCAT_VECTORS which exposed the bug in #1. llvm-svn: 142648
2011-10-21 19:42:07 +08:00
; Check that a <4 x float> compare is generated and that we are
; not stuck in an endless loop.
define void @cmp_2_floats() {
[X86][SSE] Fixed arch/triple and regenerated results. Tidyup before diffs from new patch. llvm-svn: 253144
2015-11-15 04:42:01 +08:00
; CHECK-LABEL: cmp_2_floats:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: cmpordps %xmm0, %xmm0
; CHECK-NEXT: pmovzxdq {{.*#+}} xmm0 = xmm0[0],zero,xmm0[1],zero
; CHECK-NEXT: psllq $32, %xmm0
[DAGCombine] Don't fold a trunc if it feeds an anyext Legalization tends to create anyext(trunc) patterns. This should always be combined - into either a single trunc, a single ext, or nothing if the types match exactly. But if we happen to combine the trunc first, we may pull the trunc away from the anyext or make it implicit (e.g. the truncate(extract) -> extract(bitcast) fold). To prevent this, we can avoid doing the fold, similarly to how we already handle fpround(fpextend). Differential Revision: https://reviews.llvm.org/D23893 llvm-svn: 280386
2016-09-02 01:59:24 +08:00
; CHECK-NEXT: pshufd {{.*#+}} xmm0 = xmm0[1,3,2,3]
[X86][SSE] Fixed arch/triple and regenerated results. Tidyup before diffs from new patch. llvm-svn: 253144
2015-11-15 04:42:01 +08:00
; CHECK-NEXT: pslld $31, %xmm0
; CHECK-NEXT: blendvps %xmm0, %xmm0
; CHECK-NEXT: movlps %xmm0, (%rax)
; CHECK-NEXT: retq
1. Fix the widening of SETCC in WidenVecOp_SETCC. Use the correct return CC type. 2. Fix a typo in CONCAT_VECTORS which exposed the bug in #1. llvm-svn: 142648
2011-10-21 19:42:07 +08:00
entry:
%0 = fcmp oeq <2 x float> undef, undef
%1 = select <2 x i1> %0, <2 x float> undef, <2 x float> undef
store <2 x float> %1, <2 x float>* undef
ret void
}
define void @cmp_2_doubles() {
[X86][SSE] Fixed arch/triple and regenerated results. Tidyup before diffs from new patch. llvm-svn: 253144
2015-11-15 04:42:01 +08:00
; CHECK-LABEL: cmp_2_doubles:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: cmpordpd %xmm0, %xmm0
; CHECK-NEXT: blendvpd %xmm0, %xmm0
; CHECK-NEXT: movapd %xmm0, (%rax)
; CHECK-NEXT: retq
1. Fix the widening of SETCC in WidenVecOp_SETCC. Use the correct return CC type. 2. Fix a typo in CONCAT_VECTORS which exposed the bug in #1. llvm-svn: 142648
2011-10-21 19:42:07 +08:00
entry:
%0 = fcmp oeq <2 x double> undef, undef
%1 = select <2 x i1> %0, <2 x double> undef, <2 x double> undef
store <2 x double> %1, <2 x double>* undef
ret void
}
Fix pr11193. SHL inserts zeros from the right, thus even when the original sign_extend_inreg value was of 1-bit, we need to sra. llvm-svn: 142724
2011-10-22 20:39:25 +08:00
[X86][SSE] Fixed arch/triple and regenerated results. Tidyup before diffs from new patch. llvm-svn: 253144
2015-11-15 04:42:01 +08:00
define void @mp_11193(<8 x float> * nocapture %aFOO, <8 x float>* nocapture %RET) nounwind {
; CHECK-LABEL: mp_11193:
; CHECK: # BB#0: # %allocas
[x86] avoid printing unnecessary sign bits of hex immediates in asm comments (PR20347) It would be better to check the valid/expected size of the immediate operand, but this is generally better than what we print right now. Differential Revision: http://reviews.llvm.org/D20385 llvm-svn: 271114
2016-05-28 22:58:37 +08:00
; CHECK-NEXT: movl $-1082130432, (%rsi) # imm = 0xBF800000
[X86][SSE] Fixed arch/triple and regenerated results. Tidyup before diffs from new patch. llvm-svn: 253144
2015-11-15 04:42:01 +08:00
; CHECK-NEXT: retq
Fix pr11193. SHL inserts zeros from the right, thus even when the original sign_extend_inreg value was of 1-bit, we need to sra. llvm-svn: 142724
2011-10-22 20:39:25 +08:00
allocas:
%bincmp = fcmp olt <8 x float> <float 1.000000e+00, float 1.000000e+00, float 1.000000e+00, float 1.000000e+00, float 9.000000e+00, float 1.000000e+00, float 9.000000e+00, float 1.000000e+00> , <float 3.000000e+00, float 3.000000e+00, float 3.000000e+00, float 3.000000e+00, float 3.000000e+00, float 3.000000e+00, float 3.000000e+00, float 3.000000e+00>
%t = extractelement <8 x i1> %bincmp, i32 0
%ft = sitofp i1 %t to float
%pp = bitcast <8 x float>* %RET to float*
store float %ft, float* %pp
ret void
}