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llvm-project/llvm/test/CodeGen/Thumb2/mve-gather-scatter-opt.ll

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[ARM][MVE] Masked gathers from base + vector of offsets Enables the masked gather pass to create a masked gather loading from a base and vector of offsets. This also enables v8i16 and v16i8 gather loads. Differential Revision: https://reviews.llvm.org/D72330
2020-01-14 17:48:02 +08:00
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
[ARM][MVE] Enable MVE gathers and scatters by default Enable MVE gather/scatters by default, which requires some minor adaptations in some tests. Differential revision: https://reviews.llvm.org/D86776
2020-08-28 23:27:23 +08:00
; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve.fp -enable-arm-maskedgatscat=false %s -o 2>/dev/null - | FileCheck --check-prefix NOGATSCAT %s
; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=-mve %s -o 2>/dev/null - | FileCheck --check-prefix NOMVE %s
[ARM][MVE] Enable masked gathers from vector of pointers Adds a pass to the ARM backend that takes a v4i32 gather and transforms it into a call to MVE's masked gather intrinsics. Differential Revision: https://reviews.llvm.org/D71743
2020-01-08 21:08:27 +08:00
[ARM][MVE] Enable masked scatter Extends the gather/scatter pass in MVEGatherScatterLowering.cpp to enable the transformation of masked scatters into calls to MVE's masked scatter intrinsic. Differential Revision: https://reviews.llvm.org/D72856
2020-01-21 17:44:31 +08:00
define arm_aapcs_vfpcc <4 x i32> @unscaled_i32_i32_gather(i8* %base, <4 x i32>* %offptr) {
; NOGATSCAT-LABEL: unscaled_i32_i32_gather:
[ARM][MVE] Enable masked gathers from vector of pointers Adds a pass to the ARM backend that takes a v4i32 gather and transforms it into a call to MVE's masked gather intrinsics. Differential Revision: https://reviews.llvm.org/D71743
2020-01-08 21:08:27 +08:00
; NOGATSCAT: @ %bb.0: @ %entry
[ARM][MVE] Masked gathers from base + vector of offsets Enables the masked gather pass to create a masked gather loading from a base and vector of offsets. This also enables v8i16 and v16i8 gather loads. Differential Revision: https://reviews.llvm.org/D72330
2020-01-14 17:48:02 +08:00
; NOGATSCAT-NEXT: vldrw.u32 q0, [r1]
; NOGATSCAT-NEXT: vadd.i32 q0, q0, r0
[ARM] Match dual lane vmovs from insert_vector_elt MVE has a dual lane vector move instruction, capable of moving two general purpose registers into lanes of a vector register. They look like one of: vmov q0[2], q0[0], r2, r0 vmov q0[3], q0[1], r3, r1 They only accept these lane indices though (and only insert into an i32), either moving lanes 1 and 3, or 0 and 2. This patch adds some tablegen patterns for them, selecting from vector inserts elements. Because the insert_elements are know to be canonicalized to ascending order there are several patterns that we need to select. These lane indices are: 3 2 1 0 -> vmovqrr 31; vmovqrr 20 3 2 1 -> vmovqrr 31; vmov 2 3 1 -> vmovqrr 31 2 1 0 -> vmovqrr 20; vmov 1 2 0 -> vmovqrr 20 With the top one being the most common. All other potential patterns of lane indices will be matched by a combination of these and the individual vmov pattern already present. This does mean that we are selecting several machine instructions at once due to the need to re-arrange the inserts, but in this case there is nothing else that will attempt to match an insert_vector_elt node. This is a recommit of 6cc3d80a84884a79967fffa4596c14001b8ba8a3 after fixing the backward instruction definitions.
2020-12-19 00:13:08 +08:00
; NOGATSCAT-NEXT: vmov r0, s2
; NOGATSCAT-NEXT: vmov r1, s0
Revert "[ARM] Match dual lane vmovs from insert_vector_elt" This one needed more testing.
2020-12-18 21:33:40 +08:00
; NOGATSCAT-NEXT: vmov r2, s3
[ARM] Match dual lane vmovs from insert_vector_elt MVE has a dual lane vector move instruction, capable of moving two general purpose registers into lanes of a vector register. They look like one of: vmov q0[2], q0[0], r2, r0 vmov q0[3], q0[1], r3, r1 They only accept these lane indices though (and only insert into an i32), either moving lanes 1 and 3, or 0 and 2. This patch adds some tablegen patterns for them, selecting from vector inserts elements. Because the insert_elements are know to be canonicalized to ascending order there are several patterns that we need to select. These lane indices are: 3 2 1 0 -> vmovqrr 31; vmovqrr 20 3 2 1 -> vmovqrr 31; vmov 2 3 1 -> vmovqrr 31 2 1 0 -> vmovqrr 20; vmov 1 2 0 -> vmovqrr 20 With the top one being the most common. All other potential patterns of lane indices will be matched by a combination of these and the individual vmov pattern already present. This does mean that we are selecting several machine instructions at once due to the need to re-arrange the inserts, but in this case there is nothing else that will attempt to match an insert_vector_elt node. This is a recommit of 6cc3d80a84884a79967fffa4596c14001b8ba8a3 after fixing the backward instruction definitions.
2020-12-19 00:13:08 +08:00
; NOGATSCAT-NEXT: vmov r3, s1
[ARM][MVE] Enable masked gathers from vector of pointers Adds a pass to the ARM backend that takes a v4i32 gather and transforms it into a call to MVE's masked gather intrinsics. Differential Revision: https://reviews.llvm.org/D71743
2020-01-08 21:08:27 +08:00
; NOGATSCAT-NEXT: ldr r0, [r0]
; NOGATSCAT-NEXT: ldr r1, [r1]
; NOGATSCAT-NEXT: ldr r2, [r2]
[ARM] Match dual lane vmovs from insert_vector_elt MVE has a dual lane vector move instruction, capable of moving two general purpose registers into lanes of a vector register. They look like one of: vmov q0[2], q0[0], r2, r0 vmov q0[3], q0[1], r3, r1 They only accept these lane indices though (and only insert into an i32), either moving lanes 1 and 3, or 0 and 2. This patch adds some tablegen patterns for them, selecting from vector inserts elements. Because the insert_elements are know to be canonicalized to ascending order there are several patterns that we need to select. These lane indices are: 3 2 1 0 -> vmovqrr 31; vmovqrr 20 3 2 1 -> vmovqrr 31; vmov 2 3 1 -> vmovqrr 31 2 1 0 -> vmovqrr 20; vmov 1 2 0 -> vmovqrr 20 With the top one being the most common. All other potential patterns of lane indices will be matched by a combination of these and the individual vmov pattern already present. This does mean that we are selecting several machine instructions at once due to the need to re-arrange the inserts, but in this case there is nothing else that will attempt to match an insert_vector_elt node. This is a recommit of 6cc3d80a84884a79967fffa4596c14001b8ba8a3 after fixing the backward instruction definitions.
2020-12-19 00:13:08 +08:00
; NOGATSCAT-NEXT: ldr r3, [r3]
; NOGATSCAT-NEXT: vmov q0[2], q0[0], r1, r0
; NOGATSCAT-NEXT: vmov q0[3], q0[1], r3, r2
[ARM][MVE] Enable masked gathers from vector of pointers Adds a pass to the ARM backend that takes a v4i32 gather and transforms it into a call to MVE's masked gather intrinsics. Differential Revision: https://reviews.llvm.org/D71743
2020-01-08 21:08:27 +08:00
; NOGATSCAT-NEXT: bx lr
[ARM][MVE] Masked gathers from base + vector of offsets Enables the masked gather pass to create a masked gather loading from a base and vector of offsets. This also enables v8i16 and v16i8 gather loads. Differential Revision: https://reviews.llvm.org/D72330
2020-01-14 17:48:02 +08:00
;
[ARM][MVE] Enable masked scatter Extends the gather/scatter pass in MVEGatherScatterLowering.cpp to enable the transformation of masked scatters into calls to MVE's masked scatter intrinsic. Differential Revision: https://reviews.llvm.org/D72856
2020-01-21 17:44:31 +08:00
; NOMVE-LABEL: unscaled_i32_i32_gather:
[ARM][MVE] Enable masked gathers from vector of pointers Adds a pass to the ARM backend that takes a v4i32 gather and transforms it into a call to MVE's masked gather intrinsics. Differential Revision: https://reviews.llvm.org/D71743
2020-01-08 21:08:27 +08:00
; NOMVE: @ %bb.0: @ %entry
[ARM][MVE] Masked gathers from base + vector of offsets Enables the masked gather pass to create a masked gather loading from a base and vector of offsets. This also enables v8i16 and v16i8 gather loads. Differential Revision: https://reviews.llvm.org/D72330
2020-01-14 17:48:02 +08:00
; NOMVE-NEXT: .save {r4, lr}
; NOMVE-NEXT: push {r4, lr}
; NOMVE-NEXT: ldm.w r1, {r2, r3, lr}
; NOMVE-NEXT: ldr r4, [r1, #12]
; NOMVE-NEXT: ldr.w r12, [r0, r2]
; NOMVE-NEXT: ldr r1, [r0, r3]
; NOMVE-NEXT: ldr.w r2, [r0, lr]
; NOMVE-NEXT: ldr r3, [r0, r4]
; NOMVE-NEXT: mov r0, r12
; NOMVE-NEXT: pop {r4, pc}
[ARM][MVE] Enable masked gathers from vector of pointers Adds a pass to the ARM backend that takes a v4i32 gather and transforms it into a call to MVE's masked gather intrinsics. Differential Revision: https://reviews.llvm.org/D71743
2020-01-08 21:08:27 +08:00
entry:
%offs = load <4 x i32>, <4 x i32>* %offptr, align 4
%byte_ptrs = getelementptr inbounds i8, i8* %base, <4 x i32> %offs
%ptrs = bitcast <4 x i8*> %byte_ptrs to <4 x i32*>
%gather = call <4 x i32> @llvm.masked.gather.v4i32.v4p0i32(<4 x i32*> %ptrs, i32 4, <4 x i1> <i1 true, i1 true, i1 true, i1 true>, <4 x i32> undef)
ret <4 x i32> %gather
}
declare <4 x i32> @llvm.masked.gather.v4i32.v4p0i32(<4 x i32*>, i32, <4 x i1>, <4 x i32>)
[ARM][MVE] Enable masked scatter Extends the gather/scatter pass in MVEGatherScatterLowering.cpp to enable the transformation of masked scatters into calls to MVE's masked scatter intrinsic. Differential Revision: https://reviews.llvm.org/D72856
2020-01-21 17:44:31 +08:00
define arm_aapcs_vfpcc void @unscaled_i32_i8_scatter(i8* %base, <4 x i8>* %offptr, <4 x i32> %input) {
; NOGATSCAT-LABEL: unscaled_i32_i8_scatter:
; NOGATSCAT: @ %bb.0: @ %entry
; NOGATSCAT-NEXT: vldrb.u32 q1, [r1]
; NOGATSCAT-NEXT: vmov r1, s0
; NOGATSCAT-NEXT: vadd.i32 q1, q1, r0
; NOGATSCAT-NEXT: vmov r0, s4
; NOGATSCAT-NEXT: str r1, [r0]
; NOGATSCAT-NEXT: vmov r0, s5
; NOGATSCAT-NEXT: vmov r1, s1
; NOGATSCAT-NEXT: str r1, [r0]
; NOGATSCAT-NEXT: vmov r0, s6
; NOGATSCAT-NEXT: vmov r1, s2
; NOGATSCAT-NEXT: str r1, [r0]
; NOGATSCAT-NEXT: vmov r0, s7
; NOGATSCAT-NEXT: vmov r1, s3
; NOGATSCAT-NEXT: str r1, [r0]
; NOGATSCAT-NEXT: bx lr
;
; NOMVE-LABEL: unscaled_i32_i8_scatter:
; NOMVE: @ %bb.0: @ %entry
; NOMVE-NEXT: .save {r4, lr}
; NOMVE-NEXT: push {r4, lr}
; NOMVE-NEXT: ldrb.w r12, [r1]
; NOMVE-NEXT: ldrb.w lr, [r1, #1]
; NOMVE-NEXT: ldrb r4, [r1, #2]
; NOMVE-NEXT: ldrb r1, [r1, #3]
; NOMVE-NEXT: str.w r2, [r0, r12]
; NOMVE-NEXT: ldr r2, [sp, #8]
; NOMVE-NEXT: str.w r3, [r0, lr]
; NOMVE-NEXT: str r2, [r0, r4]
; NOMVE-NEXT: ldr r2, [sp, #12]
; NOMVE-NEXT: str r2, [r0, r1]
; NOMVE-NEXT: pop {r4, pc}
entry:
%offs = load <4 x i8>, <4 x i8>* %offptr, align 1
%offs.zext = zext <4 x i8> %offs to <4 x i32>
%byte_ptrs = getelementptr inbounds i8, i8* %base, <4 x i32> %offs.zext
%ptrs = bitcast <4 x i8*> %byte_ptrs to <4 x i32*>
call void @llvm.masked.scatter.v4i32.v4p0i32(<4 x i32> %input, <4 x i32*> %ptrs, i32 4, <4 x i1> <i1 true, i1 true, i1 true, i1 true>)
ret void
}
declare void @llvm.masked.scatter.v4i32.v4p0i32(<4 x i32>, <4 x i32*>, i32, <4 x i1>)