forked from OSchip/llvm-project
22 lines
1.0 KiB
LLVM
22 lines
1.0 KiB
LLVM
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; RUN: llc -mtriple amdgcn-amdhsa -mcpu=fiji -amdgpu-scalarize-global-loads -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
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declare i32 @llvm.amdgcn.workitem.id.x()
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declare i32 @llvm.amdgcn.readfirstlane(i32)
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; GCN-LABEL: readfirstlane_uniform
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; GCN: s_load_dwordx2 s{{\[}}[[IN_ADDR:[0-9]+]]:1{{\]}}, s[4:5], 0x0
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; GCN: v_readfirstlane_b32 s[[SCALAR:[0-9]+]], v0
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; GCN: s_add_u32 s[[LOAD_ADDR:[0-9]+]], s[[IN_ADDR]], s[[SCALAR]]
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; GCN: s_load_dword s{{[0-9]+}}, s{{\[}}[[LOAD_ADDR]]
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define amdgpu_kernel void @readfirstlane_uniform(float addrspace(1)* noalias nocapture readonly, float addrspace(1)* noalias nocapture readonly) {
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%tid = tail call i32 @llvm.amdgcn.workitem.id.x()
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%scalar = tail call i32 @llvm.amdgcn.readfirstlane(i32 %tid)
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%idx = zext i32 %scalar to i64
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%gep0 = getelementptr inbounds float, float addrspace(1)* %0, i64 %idx
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%val = load float, float addrspace(1)* %gep0, align 4
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%gep1 = getelementptr inbounds float, float addrspace(1)* %1, i64 10
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store float %val, float addrspace(1)* %gep1, align 4
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ret void
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}
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