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llvm-project/llvm/test/MC/Mips/mips_directives.s

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This patch implements .set mips32r2 directive and sets appropriate feature bits. It also introduces helper functions that are used to set and clear feature bits as necessary. This directive is a counterpart of -mips32r2 command line options with the exception that it does not influence elf header flags. The usage example is gives in test file. llvm-svn: 202807
2014-03-04 17:54:09 +08:00
# RUN: llvm-mc -show-encoding -mcpu=mips32 -triple mips-unknown-unknown %s | FileCheck %s
Mips specific standalone assembler addressing mode %hi and %lo. The constructs %hi() and %lo() represent the high and low 16 bits of the address. Because the 16 bit offset field of an LW instruction is interpreted as signed, if bit 15 of the low part is 1 then the low part will act as a negative and 1 needs to be added to the high part. Contributer: Vladimir Medic llvm-svn: 175707
2013-02-21 10:09:31 +08:00
#
Mips assembler: .set reorder support Mips have delayslots for certain instructions like jumps and branches. These are instructions that follow the branch or jump and are executed before the jump or branch is completed. Early Mips compilers could not cope with delayslots and left them up to the assembler. The assembler would fill the delayslots with the appropriate instruction, usually just a nop to allow correct runtime behavior. The default behavior for this is set with .set reorder. To tell the assembler that you don't want it to mess with the delayslot one used .set noreorder. For backwards compatibility we need to support .set reorder and have it be the default behavior in the assembler. Our support for it is to insert a NOP directly after an instruction with a delayslot when in .set reorder mode. Contributer: Vladimir Medic llvm-svn: 180584
2013-04-26 07:31:35 +08:00
# CHECK: .text
# CHECK: $BB0_2:
[Mips] TargetStreamer Support for .abicalls and .set pic0. This patch adds .abicalls and .set pic0 support which affects the ELF ABI and its flags. In addition the patch uses a common interface for both the MipsTargetSteamer and MipsObjectStreamer that both the integrated and standalone assemblers will use for the output for these directives. llvm-svn: 198646
2014-01-07 07:27:31 +08:00
# CHECK: .abicalls
The Mips standalone assembler intial directive support. Actually these are just stubs for parsing the directives. Semantic support will come later. Test cases included Contributer: Vladimir Medic llvm-svn: 163364
2012-09-07 08:48:02 +08:00
$BB0_2:
reverting per request llvm-svn: 191992
2013-10-05 06:52:31 +08:00
.ent directives_test
[Mips] TargetStreamer Support for .abicalls and .set pic0. This patch adds .abicalls and .set pic0 support which affects the ELF ABI and its flags. In addition the patch uses a common interface for both the MipsTargetSteamer and MipsObjectStreamer that both the integrated and standalone assemblers will use for the output for these directives. llvm-svn: 198646
2014-01-07 07:27:31 +08:00
.abicalls
ELF symbol table field st_other support, excluding visibility bits. Mips specific standalone assembler directive "set at". This directive changes the general purpose register that the assembler will use when given the symbolic register name $at. This does not include negative testing. That will come in a future patch. A side affect of this patch recognizes the different GPR register names for temporaries between old abi and new abi so a test case for that is included. Contributer: Vladimir Medic llvm-svn: 175686
2013-02-21 07:11:17 +08:00
.frame $sp,0,$ra
.mask 0x00000000,0
.fmask 0x00000000,0
[mips] Making sure that a '.set noreorder' directive is correctly parsed and emitted and that no NOPs are emitted in a 'noreorder section'. llvm-svn: 204250
2014-03-20 00:20:19 +08:00
# CHECK: .set noreorder
Mips assembler: .set reorder support Mips have delayslots for certain instructions like jumps and branches. These are instructions that follow the branch or jump and are executed before the jump or branch is completed. Early Mips compilers could not cope with delayslots and left them up to the assembler. The assembler would fill the delayslots with the appropriate instruction, usually just a nop to allow correct runtime behavior. The default behavior for this is set with .set reorder. To tell the assembler that you don't want it to mess with the delayslot one used .set noreorder. For backwards compatibility we need to support .set reorder and have it be the default behavior in the assembler. Our support for it is to insert a NOP directly after an instruction with a delayslot when in .set reorder mode. Contributer: Vladimir Medic llvm-svn: 180584
2013-04-26 07:31:35 +08:00
# CHECK: b 1332 # encoding: [0x10,0x00,0x01,0x4d]
[mips] Making sure that a '.set noreorder' directive is correctly parsed and emitted and that no NOPs are emitted in a 'noreorder section'. llvm-svn: 204250
2014-03-20 00:20:19 +08:00
# CHECK-NOT: nop
Mips assembler: .set reorder support Mips have delayslots for certain instructions like jumps and branches. These are instructions that follow the branch or jump and are executed before the jump or branch is completed. Early Mips compilers could not cope with delayslots and left them up to the assembler. The assembler would fill the delayslots with the appropriate instruction, usually just a nop to allow correct runtime behavior. The default behavior for this is set with .set reorder. To tell the assembler that you don't want it to mess with the delayslot one used .set noreorder. For backwards compatibility we need to support .set reorder and have it be the default behavior in the assembler. Our support for it is to insert a NOP directly after an instruction with a delayslot when in .set reorder mode. Contributer: Vladimir Medic llvm-svn: 180584
2013-04-26 07:31:35 +08:00
# CHECK: j 1328 # encoding: [0x08,0x00,0x01,0x4c]
[mips] Making sure that a '.set noreorder' directive is correctly parsed and emitted and that no NOPs are emitted in a 'noreorder section'. llvm-svn: 204250
2014-03-20 00:20:19 +08:00
# CHECK-NOT: nop
Mips assembler: .set reorder support Mips have delayslots for certain instructions like jumps and branches. These are instructions that follow the branch or jump and are executed before the jump or branch is completed. Early Mips compilers could not cope with delayslots and left them up to the assembler. The assembler would fill the delayslots with the appropriate instruction, usually just a nop to allow correct runtime behavior. The default behavior for this is set with .set reorder. To tell the assembler that you don't want it to mess with the delayslot one used .set noreorder. For backwards compatibility we need to support .set reorder and have it be the default behavior in the assembler. Our support for it is to insert a NOP directly after an instruction with a delayslot when in .set reorder mode. Contributer: Vladimir Medic llvm-svn: 180584
2013-04-26 07:31:35 +08:00
# CHECK: jal 1328 # encoding: [0x0c,0x00,0x01,0x4c]
[mips] Making sure that a '.set noreorder' directive is correctly parsed and emitted and that no NOPs are emitted in a 'noreorder section'. llvm-svn: 204250
2014-03-20 00:20:19 +08:00
# CHECK-NOT: nop
[mips] [IAS] Emit .set macro/nomacro. Reviewers: dsanders Reviewed By: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D9563 llvm-svn: 237363
2015-05-14 21:42:10 +08:00
# CHECK: .set nomacro
Mips assembler: .set reorder support Mips have delayslots for certain instructions like jumps and branches. These are instructions that follow the branch or jump and are executed before the jump or branch is completed. Early Mips compilers could not cope with delayslots and left them up to the assembler. The assembler would fill the delayslots with the appropriate instruction, usually just a nop to allow correct runtime behavior. The default behavior for this is set with .set reorder. To tell the assembler that you don't want it to mess with the delayslot one used .set noreorder. For backwards compatibility we need to support .set reorder and have it be the default behavior in the assembler. Our support for it is to insert a NOP directly after an instruction with a delayslot when in .set reorder mode. Contributer: Vladimir Medic llvm-svn: 180584
2013-04-26 07:31:35 +08:00
ELF symbol table field st_other support, excluding visibility bits. Mips specific standalone assembler directive "set at". This directive changes the general purpose register that the assembler will use when given the symbolic register name $at. This does not include negative testing. That will come in a future patch. A side affect of this patch recognizes the different GPR register names for temporaries between old abi and new abi so a test case for that is included. Contributer: Vladimir Medic llvm-svn: 175686
2013-02-21 07:11:17 +08:00
.set noreorder
Mips assembler: .set reorder support Mips have delayslots for certain instructions like jumps and branches. These are instructions that follow the branch or jump and are executed before the jump or branch is completed. Early Mips compilers could not cope with delayslots and left them up to the assembler. The assembler would fill the delayslots with the appropriate instruction, usually just a nop to allow correct runtime behavior. The default behavior for this is set with .set reorder. To tell the assembler that you don't want it to mess with the delayslot one used .set noreorder. For backwards compatibility we need to support .set reorder and have it be the default behavior in the assembler. Our support for it is to insert a NOP directly after an instruction with a delayslot when in .set reorder mode. Contributer: Vladimir Medic llvm-svn: 180584
2013-04-26 07:31:35 +08:00
b 1332
j 1328
jal 1328
ELF symbol table field st_other support, excluding visibility bits. Mips specific standalone assembler directive "set at". This directive changes the general purpose register that the assembler will use when given the symbolic register name $at. This does not include negative testing. That will come in a future patch. A side affect of this patch recognizes the different GPR register names for temporaries between old abi and new abi so a test case for that is included. Contributer: Vladimir Medic llvm-svn: 175686
2013-02-21 07:11:17 +08:00
.set nomacro
.set noat
The Mips standalone assembler intial directive support. Actually these are just stubs for parsing the directives. Semantic support will come later. Test cases included Contributer: Vladimir Medic llvm-svn: 163364
2012-09-07 08:48:02 +08:00
$JTI0_0:
ELF symbol table field st_other support, excluding visibility bits. Mips specific standalone assembler directive "set at". This directive changes the general purpose register that the assembler will use when given the symbolic register name $at. This does not include negative testing. That will come in a future patch. A side affect of this patch recognizes the different GPR register names for temporaries between old abi and new abi so a test case for that is included. Contributer: Vladimir Medic llvm-svn: 175686
2013-02-21 07:11:17 +08:00
.gpword ($BB0_2)
Fix bug in .gpword directive parsing. llvm-svn: 194570
2013-11-13 21:18:04 +08:00
ELF symbol table field st_other support, excluding visibility bits. Mips specific standalone assembler directive "set at". This directive changes the general purpose register that the assembler will use when given the symbolic register name $at. This does not include negative testing. That will come in a future patch. A side affect of this patch recognizes the different GPR register names for temporaries between old abi and new abi so a test case for that is included. Contributer: Vladimir Medic llvm-svn: 175686
2013-02-21 07:11:17 +08:00
.word 0x77fffffc
This patch implements parsing the .word directive for the Mips assembler. Contributer: Vladimir Medic llvm-svn: 173407
2013-01-25 09:31:34 +08:00
# CHECK: $JTI0_0:
Implement gpword directive for mips, test case added. Stype changes using clang-format are also included. llvm-svn: 194145
2013-11-06 19:27:05 +08:00
# CHECK: .gpword ($BB0_2)
Fix bug in .gpword directive parsing. llvm-svn: 194570
2013-11-13 21:18:04 +08:00
# CHECK: .4byte 2013265916
ELF symbol table field st_other support, excluding visibility bits. Mips specific standalone assembler directive "set at". This directive changes the general purpose register that the assembler will use when given the symbolic register name $at. This does not include negative testing. That will come in a future patch. A side affect of this patch recognizes the different GPR register names for temporaries between old abi and new abi so a test case for that is included. Contributer: Vladimir Medic llvm-svn: 175686
2013-02-21 07:11:17 +08:00
.set at=$12
.set macro
[mips] [IAS] Emit .set macro/nomacro. Reviewers: dsanders Reviewed By: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D9563 llvm-svn: 237363
2015-05-14 21:42:10 +08:00
# CHECK: .set macro
[mips] Assembly parser must invoke the target streamer to handle .set reorder macro. llvm-svn: 203459
2014-03-10 21:21:10 +08:00
# CHECK: .set reorder
Mips assembler: .set reorder support Mips have delayslots for certain instructions like jumps and branches. These are instructions that follow the branch or jump and are executed before the jump or branch is completed. Early Mips compilers could not cope with delayslots and left them up to the assembler. The assembler would fill the delayslots with the appropriate instruction, usually just a nop to allow correct runtime behavior. The default behavior for this is set with .set reorder. To tell the assembler that you don't want it to mess with the delayslot one used .set noreorder. For backwards compatibility we need to support .set reorder and have it be the default behavior in the assembler. Our support for it is to insert a NOP directly after an instruction with a delayslot when in .set reorder mode. Contributer: Vladimir Medic llvm-svn: 180584
2013-04-26 07:31:35 +08:00
# CHECK: b 1332 # encoding: [0x10,0x00,0x01,0x4d]
# CHECK: nop # encoding: [0x00,0x00,0x00,0x00]
# CHECK: j 1328 # encoding: [0x08,0x00,0x01,0x4c]
# CHECK: nop # encoding: [0x00,0x00,0x00,0x00]
# CHECK: jal 1328 # encoding: [0x0c,0x00,0x01,0x4c]
# CHECK: nop # encoding: [0x00,0x00,0x00,0x00]
ELF symbol table field st_other support, excluding visibility bits. Mips specific standalone assembler directive "set at". This directive changes the general purpose register that the assembler will use when given the symbolic register name $at. This does not include negative testing. That will come in a future patch. A side affect of this patch recognizes the different GPR register names for temporaries between old abi and new abi so a test case for that is included. Contributer: Vladimir Medic llvm-svn: 175686
2013-02-21 07:11:17 +08:00
.set reorder
Method parseSetAssignment treats every operand with '$' sign as register and the parsing is directed to set alias for register. This will result in errors reported when expressions containing label references are parsed(for example long jumps) As we can't make a complete solution now it has been decided to enable .set directive to handle long jump expressions. This will cause parser to report errors when parsing integer based register assignments, for example: .set r3, will be reported as error. Still, the need for expressions is higher priority as the integer based register assignments are Mips specific and can be avoided using register names. llvm-svn: 196773
2013-12-09 19:03:25 +08:00
$BB0_4:
Mips assembler: .set reorder support Mips have delayslots for certain instructions like jumps and branches. These are instructions that follow the branch or jump and are executed before the jump or branch is completed. Early Mips compilers could not cope with delayslots and left them up to the assembler. The assembler would fill the delayslots with the appropriate instruction, usually just a nop to allow correct runtime behavior. The default behavior for this is set with .set reorder. To tell the assembler that you don't want it to mess with the delayslot one used .set noreorder. For backwards compatibility we need to support .set reorder and have it be the default behavior in the assembler. Our support for it is to insert a NOP directly after an instruction with a delayslot when in .set reorder mode. Contributer: Vladimir Medic llvm-svn: 180584
2013-04-26 07:31:35 +08:00
b 1332
j 1328
jal 1328
ELF symbol table field st_other support, excluding visibility bits. Mips specific standalone assembler directive "set at". This directive changes the general purpose register that the assembler will use when given the symbolic register name $at. This does not include negative testing. That will come in a future patch. A side affect of this patch recognizes the different GPR register names for temporaries between old abi and new abi so a test case for that is included. Contributer: Vladimir Medic llvm-svn: 175686
2013-02-21 07:11:17 +08:00
.set at=$a0
This patch enables the Mips .set directive to define aliases The .set directive in the Mips the assembler can be used to set the value of a symbol to an expression. This changes the symbol's value and type to conform to the expression's. Syntax: .set symbol, expression This patch implements the parsing of the above syntax and enables the parser to use defined symbols when parsing operands. Contributor: Vladimir Medic llvm-svn: 177667
2013-03-22 05:44:16 +08:00
.set STORE_MASK,$t7
.set FPU_MASK,$f7
Method parseSetAssignment treats every operand with '$' sign as register and the parsing is directed to set alias for register. This will result in errors reported when expressions containing label references are parsed(for example long jumps) As we can't make a complete solution now it has been decided to enable .set directive to handle long jump expressions. This will cause parser to report errors when parsing integer based register assignments, for example: .set r3, will be reported as error. Still, the need for expressions is higher priority as the integer based register assignments are Mips specific and can be avoided using register names. llvm-svn: 196773
2013-12-09 19:03:25 +08:00
.set $tmp7, $BB0_4-$BB0_2
Optimize register parsing for MipsAsmParser. Allow symbolic aliases for FPU registers. llvm-svn: 184411
2013-06-20 19:21:49 +08:00
.set f6,$f6
Add support for Mips break and syscall insructions. The corresponding test cases are added. llvm-svn: 185999
2013-07-10 18:18:10 +08:00
# CHECK: abs.s $f6, $f7 # encoding: [0x46,0x00,0x39,0x85]
[mips] Work around inconsistency in llvm-mc's placement of fixup markers Summary: Add a second fixup table to MipsAsmBackend::getFixupKindInfo() to correctly position llvm-mc's fixup placeholders for big-endian. See PR19836 for full details of the issue. To summarize, the fixup placeholders do not account for endianness properly and the implementations of getFixupKindInfo() for each target are measuring MCFixupKindInfo.TargetOffset from different ends of the instruction encoding to compensate. Reviewers: jkolek, zoran.jovanovic, vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3889 llvm-svn: 209514
2014-05-23 21:35:24 +08:00
# CHECK: lui $1, %hi($tmp7) # encoding: [0x3c,0x01,A,A]
[mips] Use MipsMCExpr instead of MCSymbolRefExpr for all relocations. Summary: This is much closer to the way MIPS relocation expressions work (%hi(foo + 2) rather than %hi(foo) + 2) and removes the need for the various bodges in MipsAsmParser::evaluateRelocExpr(). Removing those bodges ensures that the constant stored in MCValue is the full 32 or 64-bit (depending on ABI) offset from the symbol. This will be used to correct the %hi/%lo matching needed to sort the relocation table correctly. As part of this: * Gave MCExpr::print() the ability to omit parenthesis when emitting a symbol reference inside a MipsMCExpr operator like %hi(X). Without this we print things like %lo(($L1)). * %hi(%neg(%gprel(X))) is now three MipsMCExpr's instead of one. Most of the related special cases have been removed or moved to MipsMCExpr. We can remove the rest as we gain support for the less common relocations when they are not part of this specific combination. * Renamed MipsMCExpr::VariantKind and the enum prefix ('VK_') to avoid confusion with MCSymbolRefExpr::VariantKind and its prefix (also 'VK_'). * fixup_Mips_GOT_Local and fixup_Mips_GOT_Global were found to be identical and merged into fixup_Mips_GOT. * MO_GOT16 and MO_GOT turned out to be identical and have been merged into MO_GOT. * VK_Mips_GOT and VK_Mips_GOT16 turned out to be the same thing so they have been merged into MEK_GOT Reviewers: sdardis Subscribers: dsanders, sdardis, llvm-commits Differential Revision: http://reviews.llvm.org/D19716 llvm-svn: 268379
2016-05-03 21:35:44 +08:00
# CHECK: # fixup A - offset: 0, value: %hi($tmp7), kind: fixup_Mips_HI16
Optimize register parsing for MipsAsmParser. Allow symbolic aliases for FPU registers. llvm-svn: 184411
2013-06-20 19:21:49 +08:00
abs.s f6,FPU_MASK
Method parseSetAssignment treats every operand with '$' sign as register and the parsing is directed to set alias for register. This will result in errors reported when expressions containing label references are parsed(for example long jumps) As we can't make a complete solution now it has been decided to enable .set directive to handle long jump expressions. This will cause parser to report errors when parsing integer based register assignments, for example: .set r3, will be reported as error. Still, the need for expressions is higher priority as the integer based register assignments are Mips specific and can be avoided using register names. llvm-svn: 196773
2013-12-09 19:03:25 +08:00
lui $1, %hi($tmp7)
This patch implements .set mips32r2 directive and sets appropriate feature bits. It also introduces helper functions that are used to set and clear feature bits as necessary. This directive is a counterpart of -mips32r2 command line options with the exception that it does not influence elf header flags. The usage example is gives in test file. llvm-svn: 202807
2014-03-04 17:54:09 +08:00
# CHECK: .set mips32r2
# CHECK: ldxc1 $f0, $zero($5) # encoding: [0x4c,0xa0,0x00,0x01]
# CHECK: luxc1 $f0, $6($5) # encoding: [0x4c,0xa6,0x00,0x05]
# CHECK: lwxc1 $f6, $2($5) # encoding: [0x4c,0xa2,0x01,0x80]
.set mips32r2
ldxc1 $f0, $zero($5)
luxc1 $f0, $6($5)
lwxc1 $f6, $2($5)
This patch implements .set dsp directive and sets appropriate feature bits.This directive is a counterpart of -mattr=dsp command line option with the exception that it does not influence elf header flags. The usage example is gives in test file. llvm-svn: 202966
2014-03-05 19:05:09 +08:00
[mips] Add support to '.set mips64'. The '.set mips64' directive enables the feature Mips:FeatureMips64 from assembly. Note that it doesn't modify the ELF header as opposed to the use of -mips64 from the command-line. The reason for this is that we want to be as compatible as possible with existing assemblers like GAS. llvm-svn: 204817
2014-03-26 23:14:32 +08:00
# CHECK: .set mips64
# CHECK: dadd $3, $3, $3
.set mips64
dadd $3, $3, $3 # encoding: [0x00,0x62,0x18,0x2c]
[mips] Add support to '.set mips64r2'. The '.set mips64r2' directive enables the feature Mips:FeatureMips64r2 from assembly. Note that it doesn't modify the ELF header as opposed to the use of -mips64r2 from the command-line. The reason for this is that we want to be as compatible as possible with existing assemblers like GAS. llvm-svn: 204815
2014-03-26 22:52:22 +08:00
# CHECK: .set mips64r2
# CHECK: drotr $9, $6, 30 # encoding: [0x00,0x26,0x4f,0xba]
.set mips64r2
drotr $9, $6, 30
This patch implements .set dsp directive and sets appropriate feature bits.This directive is a counterpart of -mattr=dsp command line option with the exception that it does not influence elf header flags. The usage example is gives in test file. llvm-svn: 202966
2014-03-05 19:05:09 +08:00
# CHECK: .set dsp
# CHECK: lbux $7, $10($11) # encoding: [0x7d,0x6a,0x39,0x8a]
# CHECK: lhx $5, $6($7) # encoding: [0x7c,0xe6,0x29,0x0a]
.set dsp
lbux $7, $10($11)
lhx $5, $6($7)
[mips] implement .set dspr2 directive Implement .set dspr2 directive with appropriate feature bits. This directive is a counterpart of -mattr=dspr2 command line option with the exception that it does not influence elf header flags. Patch by Milos Stojanovic. Differential Revision: https://reviews.llvm.org/D38537 llvm-svn: 314994
2017-10-06 01:40:32 +08:00
# CHECK: .set dspr2
# CHECK: append $7, $10, 2 # encoding: [0x7d,0x47,0x10,0x31]
# CHECK: balign $5, $6, 3 # encoding: [0x7c,0xc5,0x1c,0x31]
.set dspr2
append $7, $10, 2
balign $5, $6, 3