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llvm-project/llvm/test/CodeGen/RISCV/inline-asm-d-constraint-f.ll

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[RISCV] Support 'f' Inline Assembly Constraint Summary: This adds the 'f' inline assembly constraint, as supported by GCC. An 'f'-constrained operand is passed in a floating point register. Exactly which kind of floating-point register (32-bit or 64-bit) is decided based on the operand type and the available standard extensions (-f and -d, respectively). This patch adds support in both the clang frontend, and LLVM itself. Reviewers: asb, lewis-revill Reviewed By: asb Subscribers: hiraditya, rbar, johnrusso, simoncook, apazos, sabuasal, niosHD, kito-cheng, shiva0217, jrtc27, MaskRay, zzheng, edward-jones, rogfer01, MartinMosbeck, brucehoult, the_o, rkruppe, PkmX, jocewei, psnobl, benna, Jim, s.egerton, cfe-commits, llvm-commits Tags: #clang, #llvm Differential Revision: https://reviews.llvm.org/D65500 llvm-svn: 367403
2019-07-31 17:45:55 +08:00
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=+d -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefix=RV32F %s
; RUN: llc -mtriple=riscv64 -mattr=+d -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefix=RV64F %s
@gd = external global double
define double @constraint_f_double(double %a) nounwind {
; RV32F-LABEL: constraint_f_double:
; RV32F: # %bb.0:
; RV32F-NEXT: addi sp, sp, -16
; RV32F-NEXT: sw a0, 8(sp)
; RV32F-NEXT: sw a1, 12(sp)
; RV32F-NEXT: fld ft0, 8(sp)
; RV32F-NEXT: lui a0, %hi(gd)
; RV32F-NEXT: fld ft1, %lo(gd)(a0)
; RV32F-NEXT: #APP
; RV32F-NEXT: fadd.d ft0, ft0, ft1
; RV32F-NEXT: #NO_APP
; RV32F-NEXT: fsd ft0, 8(sp)
; RV32F-NEXT: lw a0, 8(sp)
; RV32F-NEXT: lw a1, 12(sp)
; RV32F-NEXT: addi sp, sp, 16
; RV32F-NEXT: ret
;
; RV64F-LABEL: constraint_f_double:
; RV64F: # %bb.0:
[RISCV] Switch to the Machine Scheduler Most of the test changes are trivial instruction reorderings and differing register allocations, without any obvious performance impact. Differential Revision: https://reviews.llvm.org/D66973 llvm-svn: 372106
2019-09-17 19:15:35 +08:00
; RV64F-NEXT: lui a1, %hi(gd)
; RV64F-NEXT: fld ft0, %lo(gd)(a1)
; RV64F-NEXT: fmv.d.x ft1, a0
[RISCV] Support 'f' Inline Assembly Constraint Summary: This adds the 'f' inline assembly constraint, as supported by GCC. An 'f'-constrained operand is passed in a floating point register. Exactly which kind of floating-point register (32-bit or 64-bit) is decided based on the operand type and the available standard extensions (-f and -d, respectively). This patch adds support in both the clang frontend, and LLVM itself. Reviewers: asb, lewis-revill Reviewed By: asb Subscribers: hiraditya, rbar, johnrusso, simoncook, apazos, sabuasal, niosHD, kito-cheng, shiva0217, jrtc27, MaskRay, zzheng, edward-jones, rogfer01, MartinMosbeck, brucehoult, the_o, rkruppe, PkmX, jocewei, psnobl, benna, Jim, s.egerton, cfe-commits, llvm-commits Tags: #clang, #llvm Differential Revision: https://reviews.llvm.org/D65500 llvm-svn: 367403
2019-07-31 17:45:55 +08:00
; RV64F-NEXT: #APP
[RISCV] Switch to the Machine Scheduler Most of the test changes are trivial instruction reorderings and differing register allocations, without any obvious performance impact. Differential Revision: https://reviews.llvm.org/D66973 llvm-svn: 372106
2019-09-17 19:15:35 +08:00
; RV64F-NEXT: fadd.d ft0, ft1, ft0
[RISCV] Support 'f' Inline Assembly Constraint Summary: This adds the 'f' inline assembly constraint, as supported by GCC. An 'f'-constrained operand is passed in a floating point register. Exactly which kind of floating-point register (32-bit or 64-bit) is decided based on the operand type and the available standard extensions (-f and -d, respectively). This patch adds support in both the clang frontend, and LLVM itself. Reviewers: asb, lewis-revill Reviewed By: asb Subscribers: hiraditya, rbar, johnrusso, simoncook, apazos, sabuasal, niosHD, kito-cheng, shiva0217, jrtc27, MaskRay, zzheng, edward-jones, rogfer01, MartinMosbeck, brucehoult, the_o, rkruppe, PkmX, jocewei, psnobl, benna, Jim, s.egerton, cfe-commits, llvm-commits Tags: #clang, #llvm Differential Revision: https://reviews.llvm.org/D65500 llvm-svn: 367403
2019-07-31 17:45:55 +08:00
; RV64F-NEXT: #NO_APP
; RV64F-NEXT: fmv.x.d a0, ft0
; RV64F-NEXT: ret
%1 = load double, double* @gd
%2 = tail call double asm "fadd.d $0, $1, $2", "=f,f,f"(double %a, double %1)
ret double %2
}
[RISCV] Allow ABI Names in Inline Assembly Constraints Summary: Clang will replace references to registers using ABI names in inline assembly constraints with references to architecture names, but other frontends do not. LLVM uses the regular assembly parser to parse inline asm, so inline assembly strings can contain references to registers using their ABI names. This patch adds support for parsing constraints using either the ABI name or the architectural register name. This means we do not need to implement the ABI name replacement code in every single frontend, especially those like Rust which are a very thin shim on top of LLVM IR's inline asm, and that constraints can more closely match the assembly strings they refer to. Reviewers: asb, simoncook Reviewed By: simoncook Subscribers: hiraditya, rbar, johnrusso, JDevlieghere, apazos, sabuasal, niosHD, kito-cheng, shiva0217, jrtc27, MaskRay, zzheng, edward-jones, rogfer01, MartinMosbeck, brucehoult, the_o, rkruppe, PkmX, jocewei, psnobl, benna, Jim, s.egerton, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D65947 llvm-svn: 368303
2019-08-08 22:59:16 +08:00
define double @constraint_f_double_abi_name(double %a) nounwind {
; RV32F-LABEL: constraint_f_double_abi_name:
; RV32F: # %bb.0:
; RV32F-NEXT: addi sp, sp, -16
; RV32F-NEXT: sw a0, 8(sp)
; RV32F-NEXT: sw a1, 12(sp)
; RV32F-NEXT: fld fa1, 8(sp)
; RV32F-NEXT: lui a0, %hi(gd)
; RV32F-NEXT: fld fs0, %lo(gd)(a0)
; RV32F-NEXT: #APP
; RV32F-NEXT: fadd.d ft0, fa1, fs0
; RV32F-NEXT: #NO_APP
; RV32F-NEXT: fsd ft0, 8(sp)
; RV32F-NEXT: lw a0, 8(sp)
; RV32F-NEXT: lw a1, 12(sp)
; RV32F-NEXT: addi sp, sp, 16
; RV32F-NEXT: ret
;
; RV64F-LABEL: constraint_f_double_abi_name:
; RV64F: # %bb.0:
[RISCV] Switch to the Machine Scheduler Most of the test changes are trivial instruction reorderings and differing register allocations, without any obvious performance impact. Differential Revision: https://reviews.llvm.org/D66973 llvm-svn: 372106
2019-09-17 19:15:35 +08:00
; RV64F-NEXT: lui a1, %hi(gd)
; RV64F-NEXT: fld fs0, %lo(gd)(a1)
[RISCV] Allow ABI Names in Inline Assembly Constraints Summary: Clang will replace references to registers using ABI names in inline assembly constraints with references to architecture names, but other frontends do not. LLVM uses the regular assembly parser to parse inline asm, so inline assembly strings can contain references to registers using their ABI names. This patch adds support for parsing constraints using either the ABI name or the architectural register name. This means we do not need to implement the ABI name replacement code in every single frontend, especially those like Rust which are a very thin shim on top of LLVM IR's inline asm, and that constraints can more closely match the assembly strings they refer to. Reviewers: asb, simoncook Reviewed By: simoncook Subscribers: hiraditya, rbar, johnrusso, JDevlieghere, apazos, sabuasal, niosHD, kito-cheng, shiva0217, jrtc27, MaskRay, zzheng, edward-jones, rogfer01, MartinMosbeck, brucehoult, the_o, rkruppe, PkmX, jocewei, psnobl, benna, Jim, s.egerton, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D65947 llvm-svn: 368303
2019-08-08 22:59:16 +08:00
; RV64F-NEXT: fmv.d.x fa1, a0
; RV64F-NEXT: #APP
; RV64F-NEXT: fadd.d ft0, fa1, fs0
; RV64F-NEXT: #NO_APP
; RV64F-NEXT: fmv.x.d a0, ft0
; RV64F-NEXT: ret
%1 = load double, double* @gd
%2 = tail call double asm "fadd.d $0, $1, $2", "={ft0},{fa1},{fs0}"(double %a, double %1)
ret double %2
}