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llvm-project/llvm/test/CodeGen/PowerPC/vsx-fma-sp.ll

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Adding -verify-machineinstrs option to PowerPC tests Currently we have a number of tests that fail with -verify-machineinstrs. To detect this cases earlier we add the option to the testcases with the exception of tests that will currently fail with this option. PR 27456 keeps track of this failures. No code review, as discussed with Hal Finkel. llvm-svn: 277624
2016-08-04 02:17:35 +08:00
; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr8 -mattr=+vsx | FileCheck %s
; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr8 -mattr=+vsx -fast-isel -O0 | FileCheck -check-prefix=CHECK-FISL %s
[ScheduleDAGInstrs::buildSchedGraph()] Handling of memory dependecies rewritten. Recommited, after some fixing with test cases. Updated test cases: test/CodeGen/AArch64/arm64-misched-memdep-bug.ll test/CodeGen/AArch64/tailcall_misched_graph.ll Temporarily disabled test cases: test/CodeGen/AMDGPU/split-vector-memoperand-offsets.ll test/CodeGen/PowerPC/ppc64-fastcc.ll (partially updated) test/CodeGen/PowerPC/vsx-fma-m.ll test/CodeGen/PowerPC/vsx-fma-sp.ll http://reviews.llvm.org/D8705 Reviewers: Hal Finkel, Andy Trick. llvm-svn: 259673
2016-02-04 01:52:29 +08:00
; XFAIL: *
Add support for VSX FMA single-precision instructions to the PPC back end This patch corresponds to review: http://reviews.llvm.org/D9941 It adds the various FMA instructions introduced in the version 2.07 of the ISA along with the testing for them. These are operations on single precision scalar values in VSX registers. llvm-svn: 238578
2015-05-30 01:13:25 +08:00
define void @test1sp(float %a, float %b, float %c, float %e, float* nocapture %d) #0 {
entry:
%0 = tail call float @llvm.fma.f32(float %b, float %c, float %a)
store float %0, float* %d, align 4
%1 = tail call float @llvm.fma.f32(float %b, float %e, float %a)
%arrayidx1 = getelementptr inbounds float, float* %d, i64 1
store float %1, float* %arrayidx1, align 4
ret void
; CHECK-LABEL: @test1sp
; CHECK-DAG: li [[C1:[0-9]+]], 4
; CHECK-DAG: xsmaddmsp 3, 2, 1
; CHECK-DAG: xsmaddasp 1, 2, 4
; CHECK-DAG: stxsspx 3, 0, 7
; CHECK-DAG: stxsspx 1, 7, [[C1]]
; CHECK: blr
; CHECK-FISL-LABEL: @test1sp
; CHECK-FISL-DAG: fmr 0, 1
; CHECK-FISL-DAG: xsmaddasp 0, 2, 3
; CHECK-FISL-DAG: stxsspx 0, 0, 7
; CHECK-FISL-DAG: xsmaddasp 1, 2, 4
; CHECK-FISL-DAG: li [[C1:[0-9]+]], 4
; CHECK-FISL-DAG: stxsspx 1, 7, [[C1]]
; CHECK-FISL: blr
}
define void @test2sp(float %a, float %b, float %c, float %e, float %f, float* nocapture %d) #0 {
entry:
%0 = tail call float @llvm.fma.f32(float %b, float %c, float %a)
store float %0, float* %d, align 4
%1 = tail call float @llvm.fma.f32(float %b, float %e, float %a)
%arrayidx1 = getelementptr inbounds float, float* %d, i64 1
store float %1, float* %arrayidx1, align 4
%2 = tail call float @llvm.fma.f32(float %b, float %f, float %a)
%arrayidx2 = getelementptr inbounds float, float* %d, i64 2
store float %2, float* %arrayidx2, align 4
ret void
; CHECK-LABEL: @test2sp
; CHECK-DAG: li [[C1:[0-9]+]], 4
; CHECK-DAG: li [[C2:[0-9]+]], 8
[PowerPC] Fix the PPCInstrInfo::getInstrLatency implementation PowerPC uses itineraries to describe processor pipelines (and dispatch-group restrictions for P7/P8 cores). Unfortunately, the target-independent implementation of TII.getInstrLatency calls ItinData->getStageLatency, and that looks for the largest cycle count in the pipeline for any given instruction. This, however, yields the wrong answer for the PPC itineraries, because we don't encode the full pipeline. Because the functional units are fully pipelined, we only model the initial stages (there are no relevant hazards in the later stages to model), and so the technique employed by getStageLatency does not really work. Instead, we should take the maximum output operand latency, and that's what PPCInstrInfo::getInstrLatency now does. This caused some test-case churn, including two unfortunate side effects. First, the new arrangement of copies we get from function parameters now sometimes blocks VSX FMA mutation (a FIXME has been added to the code and the test cases), and we have one significant test-suite regression: SingleSource/Benchmarks/BenchmarkGame/spectral-norm 56.4185% +/- 18.9398% In this benchmark we have a loop with a vectorized FP divide, and it with the new scheduling both divides end up in the same dispatch group (which in this case seems to cause a problem, although why is not exactly clear). The grouping structure is hard to predict from the bottom of the loop, and there may not be much we can do to fix this. Very few other test-suite performance effects were really significant, but almost all weakly favor this change. However, in light of the issues highlighted above, I've left the old behavior available via a command-line flag. llvm-svn: 242188
2015-07-15 04:02:02 +08:00
; FIXME: We now miss this because of copy ordering at the MI level.
; CHECX-DAG: xsmaddmsp 3, 2, 1
; CHECX-DAG: xsmaddmsp 4, 2, 1
; CHECX-DAG: xsmaddasp 1, 2, 5
; CHECX-DAG: stxsspx 3, 0, 8
; CHECX-DAG: stxsspx 4, 8, [[C1]]
; CHECX-DAG: stxsspx 1, 8, [[C2]]
Add support for VSX FMA single-precision instructions to the PPC back end This patch corresponds to review: http://reviews.llvm.org/D9941 It adds the various FMA instructions introduced in the version 2.07 of the ISA along with the testing for them. These are operations on single precision scalar values in VSX registers. llvm-svn: 238578
2015-05-30 01:13:25 +08:00
; CHECK: blr
; CHECK-FISL-LABEL: @test2sp
; CHECK-FISL-DAG: fmr 0, 1
; CHECK-FISL-DAG: xsmaddasp 0, 2, 3
; CHECK-FISL-DAG: stxsspx 0, 0, 8
; CHECK-FISL-DAG: fmr 0, 1
; CHECK-FISL-DAG: xsmaddasp 0, 2, 4
; CHECK-FISL-DAG: li [[C1:[0-9]+]], 4
; CHECK-FISL-DAG: stxsspx 0, 8, [[C1]]
; CHECK-FISL-DAG: xsmaddasp 1, 2, 5
; CHECK-FISL-DAG: li [[C2:[0-9]+]], 8
; CHECK-FISL-DAG: stxsspx 1, 8, [[C2]]
; CHECK-FISL: blr
}
define void @test3sp(float %a, float %b, float %c, float %e, float %f, float* nocapture %d) #0 {
entry:
%0 = tail call float @llvm.fma.f32(float %b, float %c, float %a)
store float %0, float* %d, align 4
%1 = tail call float @llvm.fma.f32(float %b, float %e, float %a)
%2 = tail call float @llvm.fma.f32(float %b, float %c, float %1)
%arrayidx1 = getelementptr inbounds float, float* %d, i64 3
store float %2, float* %arrayidx1, align 4
%3 = tail call float @llvm.fma.f32(float %b, float %f, float %a)
%arrayidx2 = getelementptr inbounds float, float* %d, i64 2
store float %3, float* %arrayidx2, align 4
%arrayidx3 = getelementptr inbounds float, float* %d, i64 1
store float %1, float* %arrayidx3, align 4
ret void
; CHECK-LABEL: @test3sp
; CHECK-DAG: fmr [[F1:[0-9]+]], 1
; CHECK-DAG: li [[C1:[0-9]+]], 12
; CHECK-DAG: li [[C2:[0-9]+]], 8
; CHECK-DAG: li [[C3:[0-9]+]], 4
; CHECK-DAG: xsmaddmsp 4, 2, 1
; CHECK-DAG: xsmaddasp 1, 2, 5
; Note: We could convert this next FMA to M-type as well, but it would require
; re-ordering the instructions.
; CHECK-DAG: xsmaddasp [[F1]], 2, 3
; CHECK-DAG: xsmaddmsp 3, 2, 4
; CHECK-DAG: stxsspx [[F1]], 0, 8
; CHECK-DAG: stxsspx 3, 8, [[C1]]
; CHECK-DAG: stxsspx 1, 8, [[C2]]
; CHECK-DAG: stxsspx 4, 8, [[C3]]
; CHECK: blr
; CHECK-FISL-LABEL: @test3sp
; CHECK-FISL-DAG: fmr [[F1:[0-9]+]], 1
; CHECK-FISL-DAG: xsmaddasp [[F1]], 2, 4
; CHECK-FISL-DAG: fmr 4, [[F1]]
; CHECK-FISL-DAG: xsmaddasp 4, 2, 3
; CHECK-FISL-DAG: li [[C1:[0-9]+]], 12
; CHECK-FISL-DAG: stxsspx 4, 8, [[C1]]
; CHECK-FISL-DAG: xsmaddasp 1, 2, 5
; CHECK-FISL-DAG: li [[C2:[0-9]+]], 8
; CHECK-FISL-DAG: stxsspx 1, 8, [[C2]]
; CHECK-FISL-DAG: li [[C3:[0-9]+]], 4
; CHECK-FISL-DAG: stxsspx 0, 8, [[C3]]
; CHECK-FISL: blr
}
define void @test4sp(float %a, float %b, float %c, float %e, float %f, float* nocapture %d) #0 {
entry:
%0 = tail call float @llvm.fma.f32(float %b, float %c, float %a)
store float %0, float* %d, align 4
%1 = tail call float @llvm.fma.f32(float %b, float %e, float %a)
%arrayidx1 = getelementptr inbounds float, float* %d, i64 1
store float %1, float* %arrayidx1, align 4
%2 = tail call float @llvm.fma.f32(float %b, float %c, float %1)
%arrayidx3 = getelementptr inbounds float, float* %d, i64 3
store float %2, float* %arrayidx3, align 4
%3 = tail call float @llvm.fma.f32(float %b, float %f, float %a)
%arrayidx4 = getelementptr inbounds float, float* %d, i64 2
store float %3, float* %arrayidx4, align 4
ret void
; CHECK-LABEL: @test4sp
; CHECK-DAG: fmr [[F1:[0-9]+]], 1
; CHECK-DAG: li [[C1:[0-9]+]], 4
; CHECK-DAG: li [[C2:[0-9]+]], 8
; CHECK-DAG: xsmaddmsp 4, 2, 1
; Note: We could convert this next FMA to M-type as well, but it would require
; re-ordering the instructions.
; CHECK-DAG: xsmaddasp 1, 2, 5
; CHECK-DAG: xsmaddasp [[F1]], 2, 3
; CHECK-DAG: stxsspx [[F1]], 0, 8
; CHECK-DAG: stxsspx 4, 8, [[C1]]
; CHECK-DAG: li [[C3:[0-9]+]], 12
; CHECK-DAG: xsmaddasp 4, 2, 3
; CHECK-DAG: stxsspx 4, 8, [[C3]]
; CHECK-DAG: stxsspx 1, 8, [[C2]]
; CHECK: blr
; CHECK-FISL-LABEL: @test4sp
; CHECK-FISL-DAG: fmr [[F1:[0-9]+]], 1
; CHECK-FISL-DAG: xsmaddasp [[F1]], 2, 3
; CHECK-FISL-DAG: stxsspx 0, 0, 8
; CHECK-FISL-DAG: fmr [[F1]], 1
; CHECK-FISL-DAG: xsmaddasp [[F1]], 2, 4
; CHECK-FISL-DAG: li [[C3:[0-9]+]], 4
; CHECK-FISL-DAG: stxsspx 0, 8, [[C3]]
; CHECK-FISL-DAG: xsmaddasp 0, 2, 3
; CHECK-FISL-DAG: li [[C1:[0-9]+]], 12
; CHECK-FISL-DAG: stxsspx 0, 8, [[C1]]
; CHECK-FISL-DAG: xsmaddasp 1, 2, 5
; CHECK-FISL-DAG: li [[C2:[0-9]+]], 8
; CHECK-FISL-DAG: stxsspx 1, 8, [[C2]]
; CHECK-FISL: blr
}
declare float @llvm.fma.f32(float, float, float) #0