2019-06-12 10:45:27 +08:00
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mcpu=pwr8 -mtriple=powerpc64le-unknown-unknown \
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; RUN: -ppc-asm-full-reg-names -verify-machineinstrs -O2 < %s | FileCheck %s
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; RUN: llc -mcpu=pwr8 -mtriple=powerpc64-unknown-unknown \
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; RUN: -ppc-asm-full-reg-names -verify-machineinstrs -O2 < %s | FileCheck %s \
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; RUN: --check-prefix=CHECK-BE
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; RUN: llc -mcpu=pwr9 -mtriple=powerpc64le-unknown-unknown \
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; RUN: -ppc-asm-full-reg-names -verify-machineinstrs -O2 < %s | FileCheck %s \
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; RUN: --check-prefix=CHECK-P9
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; RUN: llc -mcpu=pwr9 -mtriple=powerpc64-unknown-unknown \
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; RUN: -ppc-asm-full-reg-names -verify-machineinstrs -O2 < %s | FileCheck %s \
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; RUN: --check-prefix=CHECK-P9-BE
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define dso_local i32 @poc(i32* %base, i32 %index, i1 %flag, i32 %default) {
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; CHECK-LABEL: poc:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: andi. r5, r5, 1
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; CHECK-NEXT: bc 4, gt, .LBB0_2
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; CHECK-NEXT: # %bb.1: # %true
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; CHECK-NEXT: extsw r4, r4
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; CHECK-NEXT: sldi r4, r4, 2
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; CHECK-NEXT: lwzx r3, r3, r4
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; CHECK-NEXT: blr
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; CHECK-NEXT: .LBB0_2: # %false
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; CHECK-NEXT: mr r3, r6
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; CHECK-NEXT: blr
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;
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; CHECK-BE-LABEL: poc:
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; CHECK-BE: # %bb.0: # %entry
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; CHECK-BE-NEXT: andi. r5, r5, 1
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; CHECK-BE-NEXT: bc 4, gt, .LBB0_2
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; CHECK-BE-NEXT: # %bb.1: # %true
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; CHECK-BE-NEXT: extsw r4, r4
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; CHECK-BE-NEXT: sldi r4, r4, 2
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; CHECK-BE-NEXT: lwzx r3, r3, r4
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; CHECK-BE-NEXT: blr
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; CHECK-BE-NEXT: .LBB0_2: # %false
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; CHECK-BE-NEXT: mr r3, r6
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; CHECK-BE-NEXT: blr
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;
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; CHECK-P9-LABEL: poc:
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; CHECK-P9: # %bb.0: # %entry
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; CHECK-P9-NEXT: andi. r5, r5, 1
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; CHECK-P9-NEXT: bc 4, gt, .LBB0_2
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; CHECK-P9-NEXT: # %bb.1: # %true
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2019-07-09 10:55:08 +08:00
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; CHECK-P9-NEXT: extswsli r4, r4, 2
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2019-06-12 10:45:27 +08:00
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; CHECK-P9-NEXT: lwzx r3, r3, r4
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; CHECK-P9-NEXT: blr
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; CHECK-P9-NEXT: .LBB0_2: # %false
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; CHECK-P9-NEXT: mr r3, r6
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; CHECK-P9-NEXT: blr
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;
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; CHECK-P9-BE-LABEL: poc:
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; CHECK-P9-BE: # %bb.0: # %entry
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; CHECK-P9-BE-NEXT: andi. r5, r5, 1
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; CHECK-P9-BE-NEXT: bc 4, gt, .LBB0_2
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; CHECK-P9-BE-NEXT: # %bb.1: # %true
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2019-07-09 10:55:08 +08:00
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; CHECK-P9-BE-NEXT: extswsli r4, r4, 2
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2019-06-12 10:45:27 +08:00
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; CHECK-P9-BE-NEXT: lwzx r3, r3, r4
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; CHECK-P9-BE-NEXT: blr
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; CHECK-P9-BE-NEXT: .LBB0_2: # %false
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; CHECK-P9-BE-NEXT: mr r3, r6
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; CHECK-P9-BE-NEXT: blr
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entry:
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%iconv = sext i32 %index to i64
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br i1 %flag, label %true, label %false
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true:
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%ptr = getelementptr inbounds i32, i32* %base, i64 %iconv
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%value = load i32, i32* %ptr, align 4
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ret i32 %value
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false:
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ret i32 %default
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}
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2019-07-09 10:55:08 +08:00
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define dso_local i64 @poc_i64(i64* %base, i32 %index, i1 %flag, i64 %default) {
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; CHECK-LABEL: poc_i64:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: andi. r5, r5, 1
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; CHECK-NEXT: bc 4, gt, .LBB1_2
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; CHECK-NEXT: # %bb.1: # %true
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; CHECK-NEXT: extsw r4, r4
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; CHECK-NEXT: sldi r4, r4, 3
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; CHECK-NEXT: ldx r3, r3, r4
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; CHECK-NEXT: blr
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; CHECK-NEXT: .LBB1_2: # %false
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; CHECK-NEXT: mr r3, r6
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; CHECK-NEXT: blr
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;
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; CHECK-BE-LABEL: poc_i64:
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; CHECK-BE: # %bb.0: # %entry
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; CHECK-BE-NEXT: andi. r5, r5, 1
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; CHECK-BE-NEXT: bc 4, gt, .LBB1_2
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; CHECK-BE-NEXT: # %bb.1: # %true
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; CHECK-BE-NEXT: extsw r4, r4
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; CHECK-BE-NEXT: sldi r4, r4, 3
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; CHECK-BE-NEXT: ldx r3, r3, r4
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; CHECK-BE-NEXT: blr
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; CHECK-BE-NEXT: .LBB1_2: # %false
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; CHECK-BE-NEXT: mr r3, r6
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; CHECK-BE-NEXT: blr
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;
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; CHECK-P9-LABEL: poc_i64:
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; CHECK-P9: # %bb.0: # %entry
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; CHECK-P9-NEXT: andi. r5, r5, 1
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; CHECK-P9-NEXT: bc 4, gt, .LBB1_2
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; CHECK-P9-NEXT: # %bb.1: # %true
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; CHECK-P9-NEXT: extswsli r4, r4, 3
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; CHECK-P9-NEXT: ldx r3, r3, r4
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; CHECK-P9-NEXT: blr
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; CHECK-P9-NEXT: .LBB1_2: # %false
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; CHECK-P9-NEXT: mr r3, r6
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; CHECK-P9-NEXT: blr
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;
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; CHECK-P9-BE-LABEL: poc_i64:
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; CHECK-P9-BE: # %bb.0: # %entry
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; CHECK-P9-BE-NEXT: andi. r5, r5, 1
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; CHECK-P9-BE-NEXT: bc 4, gt, .LBB1_2
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; CHECK-P9-BE-NEXT: # %bb.1: # %true
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; CHECK-P9-BE-NEXT: extswsli r4, r4, 3
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; CHECK-P9-BE-NEXT: ldx r3, r3, r4
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; CHECK-P9-BE-NEXT: blr
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; CHECK-P9-BE-NEXT: .LBB1_2: # %false
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; CHECK-P9-BE-NEXT: mr r3, r6
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; CHECK-P9-BE-NEXT: blr
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entry:
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%iconv = sext i32 %index to i64
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br i1 %flag, label %true, label %false
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true:
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%ptr = getelementptr inbounds i64, i64* %base, i64 %iconv
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%value = load i64, i64* %ptr, align 8
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ret i64 %value
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false:
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ret i64 %default
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}
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define dso_local i64 @no_extswsli(i64* %base, i32 %index, i1 %flag) {
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; CHECK-LABEL: no_extswsli:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: andi. r5, r5, 1
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; CHECK-NEXT: extsw r4, r4
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; CHECK-NEXT: bc 4, gt, .LBB2_2
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; CHECK-NEXT: # %bb.1: # %true
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; CHECK-NEXT: sldi r4, r4, 3
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; CHECK-NEXT: ldx r3, r3, r4
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; CHECK-NEXT: blr
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; CHECK-NEXT: .LBB2_2: # %false
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; CHECK-NEXT: mr r3, r4
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; CHECK-NEXT: blr
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;
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; CHECK-BE-LABEL: no_extswsli:
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; CHECK-BE: # %bb.0: # %entry
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; CHECK-BE-NEXT: andi. r5, r5, 1
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; CHECK-BE-NEXT: extsw r4, r4
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; CHECK-BE-NEXT: bc 4, gt, .LBB2_2
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; CHECK-BE-NEXT: # %bb.1: # %true
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; CHECK-BE-NEXT: sldi r4, r4, 3
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; CHECK-BE-NEXT: ldx r3, r3, r4
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; CHECK-BE-NEXT: blr
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; CHECK-BE-NEXT: .LBB2_2: # %false
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; CHECK-BE-NEXT: mr r3, r4
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; CHECK-BE-NEXT: blr
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;
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; CHECK-P9-LABEL: no_extswsli:
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; CHECK-P9: # %bb.0: # %entry
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; CHECK-P9-NEXT: extsw r4, r4
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; CHECK-P9-NEXT: andi. r5, r5, 1
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; CHECK-P9-NEXT: bc 4, gt, .LBB2_2
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; CHECK-P9-NEXT: # %bb.1: # %true
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; CHECK-P9-NEXT: sldi r4, r4, 3
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; CHECK-P9-NEXT: ldx r3, r3, r4
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; CHECK-P9-NEXT: blr
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; CHECK-P9-NEXT: .LBB2_2: # %false
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; CHECK-P9-NEXT: mr r3, r4
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; CHECK-P9-NEXT: blr
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;
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; CHECK-P9-BE-LABEL: no_extswsli:
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; CHECK-P9-BE: # %bb.0: # %entry
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; CHECK-P9-BE-NEXT: extsw r4, r4
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; CHECK-P9-BE-NEXT: andi. r5, r5, 1
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; CHECK-P9-BE-NEXT: bc 4, gt, .LBB2_2
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; CHECK-P9-BE-NEXT: # %bb.1: # %true
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; CHECK-P9-BE-NEXT: sldi r4, r4, 3
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; CHECK-P9-BE-NEXT: ldx r3, r3, r4
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; CHECK-P9-BE-NEXT: blr
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; CHECK-P9-BE-NEXT: .LBB2_2: # %false
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; CHECK-P9-BE-NEXT: mr r3, r4
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; CHECK-P9-BE-NEXT: blr
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entry:
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%iconv = sext i32 %index to i64
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br i1 %flag, label %true, label %false
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true:
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%ptr = getelementptr inbounds i64, i64* %base, i64 %iconv
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%value = load i64, i64* %ptr, align 8
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ret i64 %value
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false:
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ret i64 %iconv
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}
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