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llvm-project/llvm/test/CodeGen/AVR/rot.ll

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[AVR] Implement non-constant bit rotations This lets us do bit rotations of variable amount. llvm-svn: 301794
2017-05-01 17:48:55 +08:00
; RUN: llc < %s -march=avr | FileCheck %s
; Bit rotation tests.
; CHECK-LABEL: rol8:
define i8 @rol8(i8 %val, i8 %amt) {
; CHECK: andi r22, 7
[AVR] Improve inline rotate/shift expansions These expansions were rather inefficient and were done with more code than necessary. This change optimizes them to use expansions more similar to GCC. The code size is the same (when optimizing for code size) but somehow LLVM reorders blocks in a non-optimal way. Still, this should be an improvement with a reduction in code size of around 0.12% (when building compiler-rt). Differential Revision: https://reviews.llvm.org/D86418
2020-08-23 20:17:29 +08:00
; CHECK-NEXT: dec r22
; CHECK-NEXT: brmi .LBB0_2
[AVR] Implement non-constant bit rotations This lets us do bit rotations of variable amount. llvm-svn: 301794
2017-05-01 17:48:55 +08:00
[AVR] Fix private label prefix This is a small pet peeve from me. This change makes sure the AVR backend uses the correct private label prefix (.L) so that private labels are hidden in avr-objdump. Example code: define i8 @foo(i1 %cond) { br i1 %cond, label %then, label %else then: ret i8 3 else: ret i8 5 } When compiling this: llc -march=avr -filetype=obj -o test.o test.ll and then dumping it: avr-objdump -d test.o You would previously get an ugly temporary label: 00000000 <foo>: 0: 81 70 andi r24, 0x01 ; 1 2: 80 30 cpi r24, 0x00 ; 0 4: f9 f3 breq .-2 ; 0x4 <foo+0x4> 6: 83 e0 ldi r24, 0x03 ; 3 8: 08 95 ret 0000000a <LBB0_2>: a: 85 e0 ldi r24, 0x05 ; 5 c: 08 95 ret This patch fixes that, the output is now: 00000000 <foo>: 0: 81 70 andi r24, 0x01 ; 1 2: 80 30 cpi r24, 0x00 ; 0 4: 01 f0 breq .+0 ; 0x6 <foo+0x6> 6: 83 e0 ldi r24, 0x03 ; 3 8: 08 95 ret a: 85 e0 ldi r24, 0x05 ; 5 c: 08 95 ret Note that as you can see the breq operand is different. However it is still the same after linking: 4: 11 f0 breq .+4 Differential Revision: https://reviews.llvm.org/D75124
2020-02-26 00:15:34 +08:00
; CHECK-NEXT: .LBB0_1:
[AVR] Fix codegen for rotate instructions Summary: This patch introduces the ROLBRd and RORBRd pseudo-instructions, which implemenent the "traditional" rotate operations; instead of the AVR rotate instructions that use the carry bit. The code is not optimized at all. Especially when dealing with loops of rotate instructions, this codegen should be improved some day. Related bug: 41358 <https://bugs.llvm.org/show_bug.cgi?id=41358> //Note//: This is my first submitted patch. Reviewers: dylanmckay, Jim Reviewed By: dylanmckay Subscribers: hiraditya, llvm-commits, dylanmckay, dsprenkels Tags: #llvm Patched by dsprenkels (Daan Sprenkels) Differential Revision: https://reviews.llvm.org/D60365
2019-12-23 11:24:20 +08:00
; CHECK-NEXT: lsl r24
; CHECK-NEXT: adc r24, r1
[AVR] Improve inline rotate/shift expansions These expansions were rather inefficient and were done with more code than necessary. This change optimizes them to use expansions more similar to GCC. The code size is the same (when optimizing for code size) but somehow LLVM reorders blocks in a non-optimal way. Still, this should be an improvement with a reduction in code size of around 0.12% (when building compiler-rt). Differential Revision: https://reviews.llvm.org/D86418
2020-08-23 20:17:29 +08:00
; CHECK-NEXT: dec r22
; CHECK-NEXT: brpl .LBB0_1
[AVR] Implement non-constant bit rotations This lets us do bit rotations of variable amount. llvm-svn: 301794
2017-05-01 17:48:55 +08:00
[AVR] Fix private label prefix This is a small pet peeve from me. This change makes sure the AVR backend uses the correct private label prefix (.L) so that private labels are hidden in avr-objdump. Example code: define i8 @foo(i1 %cond) { br i1 %cond, label %then, label %else then: ret i8 3 else: ret i8 5 } When compiling this: llc -march=avr -filetype=obj -o test.o test.ll and then dumping it: avr-objdump -d test.o You would previously get an ugly temporary label: 00000000 <foo>: 0: 81 70 andi r24, 0x01 ; 1 2: 80 30 cpi r24, 0x00 ; 0 4: f9 f3 breq .-2 ; 0x4 <foo+0x4> 6: 83 e0 ldi r24, 0x03 ; 3 8: 08 95 ret 0000000a <LBB0_2>: a: 85 e0 ldi r24, 0x05 ; 5 c: 08 95 ret This patch fixes that, the output is now: 00000000 <foo>: 0: 81 70 andi r24, 0x01 ; 1 2: 80 30 cpi r24, 0x00 ; 0 4: 01 f0 breq .+0 ; 0x6 <foo+0x6> 6: 83 e0 ldi r24, 0x03 ; 3 8: 08 95 ret a: 85 e0 ldi r24, 0x05 ; 5 c: 08 95 ret Note that as you can see the breq operand is different. However it is still the same after linking: 4: 11 f0 breq .+4 Differential Revision: https://reviews.llvm.org/D75124
2020-02-26 00:15:34 +08:00
; CHECK-NEXT: .LBB0_2:
[AVR] Implement non-constant bit rotations This lets us do bit rotations of variable amount. llvm-svn: 301794
2017-05-01 17:48:55 +08:00
; CHECK-NEXT: ret
%mod = urem i8 %amt, 8
%inv = sub i8 8, %mod
%parta = shl i8 %val, %mod
%partb = lshr i8 %val, %inv
%rotl = or i8 %parta, %partb
ret i8 %rotl
}
; CHECK-LABEL: ror8:
define i8 @ror8(i8 %val, i8 %amt) {
; CHECK: andi r22, 7
[AVR] Improve inline rotate/shift expansions These expansions were rather inefficient and were done with more code than necessary. This change optimizes them to use expansions more similar to GCC. The code size is the same (when optimizing for code size) but somehow LLVM reorders blocks in a non-optimal way. Still, this should be an improvement with a reduction in code size of around 0.12% (when building compiler-rt). Differential Revision: https://reviews.llvm.org/D86418
2020-08-23 20:17:29 +08:00
; CHECK-NEXT: dec r22
; CHECK-NEXT: brmi .LBB1_2
[AVR] Implement non-constant bit rotations This lets us do bit rotations of variable amount. llvm-svn: 301794
2017-05-01 17:48:55 +08:00
[AVR] Fix private label prefix This is a small pet peeve from me. This change makes sure the AVR backend uses the correct private label prefix (.L) so that private labels are hidden in avr-objdump. Example code: define i8 @foo(i1 %cond) { br i1 %cond, label %then, label %else then: ret i8 3 else: ret i8 5 } When compiling this: llc -march=avr -filetype=obj -o test.o test.ll and then dumping it: avr-objdump -d test.o You would previously get an ugly temporary label: 00000000 <foo>: 0: 81 70 andi r24, 0x01 ; 1 2: 80 30 cpi r24, 0x00 ; 0 4: f9 f3 breq .-2 ; 0x4 <foo+0x4> 6: 83 e0 ldi r24, 0x03 ; 3 8: 08 95 ret 0000000a <LBB0_2>: a: 85 e0 ldi r24, 0x05 ; 5 c: 08 95 ret This patch fixes that, the output is now: 00000000 <foo>: 0: 81 70 andi r24, 0x01 ; 1 2: 80 30 cpi r24, 0x00 ; 0 4: 01 f0 breq .+0 ; 0x6 <foo+0x6> 6: 83 e0 ldi r24, 0x03 ; 3 8: 08 95 ret a: 85 e0 ldi r24, 0x05 ; 5 c: 08 95 ret Note that as you can see the breq operand is different. However it is still the same after linking: 4: 11 f0 breq .+4 Differential Revision: https://reviews.llvm.org/D75124
2020-02-26 00:15:34 +08:00
; CHECK-NEXT: .LBB1_1:
[AVR] Fix rotate instructions This patch fixes some issues with the RORB pseudo instruction. - A minor issue in which the instructions were said to use the SREG, which is not true. - An issue with the BLD instruction, which did not have an output operand. - A major issue in which invalid instructions were generated. The fix also reduce RORB from 4 to 3 instructions, so it's also a small optimization. These issues were flagged by the machine verifier. Differential Revision: https://reviews.llvm.org/D96957
2021-02-18 23:12:11 +08:00
; CHECK-NEXT: bst r24, 0
; CHECK-NEXT: ror r24
; CHECK-NEXT: bld r24, 7
[AVR] Improve inline rotate/shift expansions These expansions were rather inefficient and were done with more code than necessary. This change optimizes them to use expansions more similar to GCC. The code size is the same (when optimizing for code size) but somehow LLVM reorders blocks in a non-optimal way. Still, this should be an improvement with a reduction in code size of around 0.12% (when building compiler-rt). Differential Revision: https://reviews.llvm.org/D86418
2020-08-23 20:17:29 +08:00
; CHECK-NEXT: dec r22
; CHECK-NEXT: brpl .LBB1_1
[AVR] Implement non-constant bit rotations This lets us do bit rotations of variable amount. llvm-svn: 301794
2017-05-01 17:48:55 +08:00
[AVR] Fix private label prefix This is a small pet peeve from me. This change makes sure the AVR backend uses the correct private label prefix (.L) so that private labels are hidden in avr-objdump. Example code: define i8 @foo(i1 %cond) { br i1 %cond, label %then, label %else then: ret i8 3 else: ret i8 5 } When compiling this: llc -march=avr -filetype=obj -o test.o test.ll and then dumping it: avr-objdump -d test.o You would previously get an ugly temporary label: 00000000 <foo>: 0: 81 70 andi r24, 0x01 ; 1 2: 80 30 cpi r24, 0x00 ; 0 4: f9 f3 breq .-2 ; 0x4 <foo+0x4> 6: 83 e0 ldi r24, 0x03 ; 3 8: 08 95 ret 0000000a <LBB0_2>: a: 85 e0 ldi r24, 0x05 ; 5 c: 08 95 ret This patch fixes that, the output is now: 00000000 <foo>: 0: 81 70 andi r24, 0x01 ; 1 2: 80 30 cpi r24, 0x00 ; 0 4: 01 f0 breq .+0 ; 0x6 <foo+0x6> 6: 83 e0 ldi r24, 0x03 ; 3 8: 08 95 ret a: 85 e0 ldi r24, 0x05 ; 5 c: 08 95 ret Note that as you can see the breq operand is different. However it is still the same after linking: 4: 11 f0 breq .+4 Differential Revision: https://reviews.llvm.org/D75124
2020-02-26 00:15:34 +08:00
; CHECK-NEXT: .LBB1_2:
[AVR] Implement non-constant bit rotations This lets us do bit rotations of variable amount. llvm-svn: 301794
2017-05-01 17:48:55 +08:00
; CHECK-NEXT: ret
%mod = urem i8 %amt, 8
%inv = sub i8 8, %mod
%parta = lshr i8 %val, %mod
%partb = shl i8 %val, %inv
%rotr = or i8 %parta, %partb
ret i8 %rotr
}