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llvm-project/llvm/test/CodeGen/AVR/brind.ll

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[AVR] Fix incorrect register state for LDRdPtr Summary: LDRdPtr expanded from LDWRdPtr shouldn't define its second operand(SrcReg). The second operand is its source register. Add -verify-machineinstrs into command line of testcases can trigger this error. Reviewers: dylanmckay Reviewed By: dylanmckay Subscribers: hiraditya, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D75437
2020-03-03 16:52:20 +08:00
; RUN: llc -mattr=sram,eijmpcall < %s -march=avr -verify-machineinstrs | FileCheck %s
[AVR] Add the pseudo instruction expansion pass Summary: A lot of the pseudo instructions are required because LLVM assumes that all integers of the same size as the pointer size are legal. This means that it will not currently expand 16-bit instructions to their 8-bit variants because it thinks 16-bit types are legal for the operations. This also adds all of the CodeGen tests that required the pass to run. Reviewers: arsenm, kparzysz Subscribers: wdng, mgorny, modocache, llvm-commits Differential Revision: https://reviews.llvm.org/D26577 llvm-svn: 287162
2016-11-17 05:58:04 +08:00
Place the BlockAddress type in the address space of the containing function While this should not matter for most architectures (where the program address space is 0), it is important for CHERI (and therefore Arm Morello). We use address space 200 for all of our code pointers and without this change we assert in the SelectionDAG handling of BlockAddress nodes. It is also useful for AVR: previously programs targeting AVR that attempt to read their own machine code via a pointer to a label would instead read from RAM using a pointer relative to the the start of program flash. Reviewed By: dylanmckay, theraven Differential Revision: https://reviews.llvm.org/D48803
2021-07-02 18:25:43 +08:00
@brind.k = private unnamed_addr constant [2 x i8 addrspace(1)*] [i8 addrspace(1)* blockaddress(@brind, %return), i8 addrspace(1)* blockaddress(@brind, %b)], align 1
[AVR] Add the pseudo instruction expansion pass Summary: A lot of the pseudo instructions are required because LLVM assumes that all integers of the same size as the pointer size are legal. This means that it will not currently expand 16-bit instructions to their 8-bit variants because it thinks 16-bit types are legal for the operations. This also adds all of the CodeGen tests that required the pass to run. Reviewers: arsenm, kparzysz Subscribers: wdng, mgorny, modocache, llvm-commits Differential Revision: https://reviews.llvm.org/D26577 llvm-svn: 287162
2016-11-17 05:58:04 +08:00
define i8 @brind(i8 %p) {
; CHECK-LABEL: brind:
; CHECK: ijmp
entry:
%idxprom = sext i8 %p to i16
Place the BlockAddress type in the address space of the containing function While this should not matter for most architectures (where the program address space is 0), it is important for CHERI (and therefore Arm Morello). We use address space 200 for all of our code pointers and without this change we assert in the SelectionDAG handling of BlockAddress nodes. It is also useful for AVR: previously programs targeting AVR that attempt to read their own machine code via a pointer to a label would instead read from RAM using a pointer relative to the the start of program flash. Reviewed By: dylanmckay, theraven Differential Revision: https://reviews.llvm.org/D48803
2021-07-02 18:25:43 +08:00
%arrayidx = getelementptr inbounds [2 x i8 addrspace(1)*], [2 x i8 addrspace(1)*]* @brind.k, i16 0, i16 %idxprom
%s = load i8 addrspace(1)*, i8 addrspace(1)** %arrayidx
indirectbr i8 addrspace(1)* %s, [label %return, label %b]
[AVR] Add the pseudo instruction expansion pass Summary: A lot of the pseudo instructions are required because LLVM assumes that all integers of the same size as the pointer size are legal. This means that it will not currently expand 16-bit instructions to their 8-bit variants because it thinks 16-bit types are legal for the operations. This also adds all of the CodeGen tests that required the pass to run. Reviewers: arsenm, kparzysz Subscribers: wdng, mgorny, modocache, llvm-commits Differential Revision: https://reviews.llvm.org/D26577 llvm-svn: 287162
2016-11-17 05:58:04 +08:00
b:
br label %return
return:
%retval.0 = phi i8 [ 4, %b ], [ 2, %entry ]
ret i8 %retval.0
}