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llvm-project/llvm/test/CodeGen/X86/masked_store.ll

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[X86] Split masked load/store test files llvm-svn: 346889
2018-11-15 04:44:59 +08:00
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
[X86][SSE] Add SSE2/SSE42 masked load/store tests Now that the load/store tests are split the impact of running the tests on multiple (illegal) targets is a lot less impactful llvm-svn: 346896
2018-11-15 05:31:50 +08:00
; RUN: llc < %s -mtriple=x86_64-apple-darwin -mattr=sse2 | FileCheck %s --check-prefixes=SSE,SSE2
; RUN: llc < %s -mtriple=x86_64-apple-darwin -mattr=sse4.2 | FileCheck %s --check-prefixes=SSE,SSE4
; RUN: llc < %s -mtriple=x86_64-apple-darwin -mattr=avx | FileCheck %s --check-prefixes=AVX,AVX1OR2,AVX1
; RUN: llc < %s -mtriple=x86_64-apple-darwin -mattr=avx2 | FileCheck %s --check-prefixes=AVX,AVX1OR2,AVX2
; RUN: llc < %s -mtriple=x86_64-apple-darwin -mattr=avx512f | FileCheck %s --check-prefixes=AVX,AVX512,AVX512F
[X86][AVX] Add AVX512DQ coverage for masked memory ops tests (PR34584) llvm-svn: 359395
2019-04-28 18:02:34 +08:00
; RUN: llc < %s -mtriple=x86_64-apple-darwin -mattr=avx512f,avx512dq,avx512vl | FileCheck %s --check-prefixes=AVX,AVX512,AVX512VL,AVX512VLDQ
; RUN: llc < %s -mtriple=x86_64-apple-darwin -mattr=avx512f,avx512bw,avx512vl | FileCheck %s --check-prefixes=AVX,AVX512,AVX512VL,AVX512VLBW
[X86] Split masked load/store test files llvm-svn: 346889
2018-11-15 04:44:59 +08:00
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
;
; vXf64
;
define void @store_v1f64_v1i64(<1 x i64> %trigger, <1 x double>* %addr, <1 x double> %val) {
; SSE-LABEL: store_v1f64_v1i64:
[X86][SSE] Add SSE2/SSE42 masked load/store tests Now that the load/store tests are split the impact of running the tests on multiple (illegal) targets is a lot less impactful llvm-svn: 346896
2018-11-15 05:31:50 +08:00
; SSE: ## %bb.0:
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; SSE-NEXT: testq %rdi, %rdi
; SSE-NEXT: jns LBB0_2
[X86][SSE] Add SSE2/SSE42 masked load/store tests Now that the load/store tests are split the impact of running the tests on multiple (illegal) targets is a lot less impactful llvm-svn: 346896
2018-11-15 05:31:50 +08:00
; SSE-NEXT: ## %bb.1: ## %cond.store
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; SSE-NEXT: movsd %xmm0, (%rsi)
[X86][SSE] Add SSE2/SSE42 masked load/store tests Now that the load/store tests are split the impact of running the tests on multiple (illegal) targets is a lot less impactful llvm-svn: 346896
2018-11-15 05:31:50 +08:00
; SSE-NEXT: LBB0_2: ## %else
; SSE-NEXT: retq
;
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; AVX-LABEL: store_v1f64_v1i64:
[X86] Split masked load/store test files llvm-svn: 346889
2018-11-15 04:44:59 +08:00
; AVX: ## %bb.0:
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; AVX-NEXT: testq %rdi, %rdi
; AVX-NEXT: jns LBB0_2
[X86] Split masked load/store test files llvm-svn: 346889
2018-11-15 04:44:59 +08:00
; AVX-NEXT: ## %bb.1: ## %cond.store
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; AVX-NEXT: vmovsd %xmm0, (%rsi)
[X86] Split masked load/store test files llvm-svn: 346889
2018-11-15 04:44:59 +08:00
; AVX-NEXT: LBB0_2: ## %else
; AVX-NEXT: retq
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
%mask = icmp slt <1 x i64> %trigger, zeroinitializer
call void @llvm.masked.store.v1f64.p0v1f64(<1 x double> %val, <1 x double>* %addr, i32 4, <1 x i1> %mask)
[X86] Split masked load/store test files llvm-svn: 346889
2018-11-15 04:44:59 +08:00
ret void
}
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
define void @store_v2f64_v2i64(<2 x i64> %trigger, <2 x double>* %addr, <2 x double> %val) {
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE-LABEL: store_v2f64_v2i64:
; SSE: ## %bb.0:
; SSE-NEXT: movmskpd %xmm0, %eax
; SSE-NEXT: testb $1, %al
; SSE-NEXT: jne LBB1_1
; SSE-NEXT: ## %bb.2: ## %else
; SSE-NEXT: testb $2, %al
; SSE-NEXT: jne LBB1_3
; SSE-NEXT: LBB1_4: ## %else2
; SSE-NEXT: retq
; SSE-NEXT: LBB1_1: ## %cond.store
; SSE-NEXT: movlps %xmm1, (%rdi)
; SSE-NEXT: testb $2, %al
; SSE-NEXT: je LBB1_4
; SSE-NEXT: LBB1_3: ## %cond.store1
; SSE-NEXT: movhps %xmm1, 8(%rdi)
; SSE-NEXT: retq
[X86][SSE] Add SSE2/SSE42 masked load/store tests Now that the load/store tests are split the impact of running the tests on multiple (illegal) targets is a lot less impactful llvm-svn: 346896
2018-11-15 05:31:50 +08:00
;
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; AVX1OR2-LABEL: store_v2f64_v2i64:
; AVX1OR2: ## %bb.0:
; AVX1OR2-NEXT: vmaskmovpd %xmm1, %xmm0, (%rdi)
; AVX1OR2-NEXT: retq
[X86] Split masked load/store test files llvm-svn: 346889
2018-11-15 04:44:59 +08:00
;
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; AVX512F-LABEL: store_v2f64_v2i64:
[X86] Split masked load/store test files llvm-svn: 346889
2018-11-15 04:44:59 +08:00
; AVX512F: ## %bb.0:
; AVX512F-NEXT: ## kill: def $xmm1 killed $xmm1 def $zmm1
; AVX512F-NEXT: ## kill: def $xmm0 killed $xmm0 def $zmm0
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; AVX512F-NEXT: vpxor %xmm2, %xmm2, %xmm2
; AVX512F-NEXT: vpcmpgtq %zmm0, %zmm2, %k0
; AVX512F-NEXT: kshiftlw $14, %k0, %k0
; AVX512F-NEXT: kshiftrw $14, %k0, %k1
; AVX512F-NEXT: vmovupd %zmm1, (%rdi) {%k1}
[X86] Split masked load/store test files llvm-svn: 346889
2018-11-15 04:44:59 +08:00
; AVX512F-NEXT: vzeroupper
; AVX512F-NEXT: retq
;
[X86][AVX] Add AVX512DQ coverage for masked memory ops tests (PR34584) llvm-svn: 359395
2019-04-28 18:02:34 +08:00
; AVX512VLDQ-LABEL: store_v2f64_v2i64:
; AVX512VLDQ: ## %bb.0:
; AVX512VLDQ-NEXT: vpmovq2m %xmm0, %k1
; AVX512VLDQ-NEXT: vmovupd %xmm1, (%rdi) {%k1}
; AVX512VLDQ-NEXT: retq
;
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; AVX512VLBW-LABEL: store_v2f64_v2i64:
[X86][SSE] Add SSE2/SSE42 masked load/store tests Now that the load/store tests are split the impact of running the tests on multiple (illegal) targets is a lot less impactful llvm-svn: 346896
2018-11-15 05:31:50 +08:00
; AVX512VLBW: ## %bb.0:
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; AVX512VLBW-NEXT: vpxor %xmm2, %xmm2, %xmm2
; AVX512VLBW-NEXT: vpcmpgtq %xmm0, %xmm2, %k1
; AVX512VLBW-NEXT: vmovupd %xmm1, (%rdi) {%k1}
[X86][SSE] Add SSE2/SSE42 masked load/store tests Now that the load/store tests are split the impact of running the tests on multiple (illegal) targets is a lot less impactful llvm-svn: 346896
2018-11-15 05:31:50 +08:00
; AVX512VLBW-NEXT: retq
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
%mask = icmp slt <2 x i64> %trigger, zeroinitializer
call void @llvm.masked.store.v2f64.p0v2f64(<2 x double> %val, <2 x double>* %addr, i32 4, <2 x i1> %mask)
[X86] Split masked load/store test files llvm-svn: 346889
2018-11-15 04:44:59 +08:00
ret void
}
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
define void @store_v4f64_v4i64(<4 x i64> %trigger, <4 x double>* %addr, <4 x double> %val) {
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE-LABEL: store_v4f64_v4i64:
; SSE: ## %bb.0:
; SSE-NEXT: packssdw %xmm1, %xmm0
; SSE-NEXT: movmskps %xmm0, %eax
; SSE-NEXT: testb $1, %al
; SSE-NEXT: jne LBB2_1
; SSE-NEXT: ## %bb.2: ## %else
; SSE-NEXT: testb $2, %al
; SSE-NEXT: jne LBB2_3
; SSE-NEXT: LBB2_4: ## %else2
; SSE-NEXT: testb $4, %al
; SSE-NEXT: jne LBB2_5
; SSE-NEXT: LBB2_6: ## %else4
; SSE-NEXT: testb $8, %al
; SSE-NEXT: jne LBB2_7
; SSE-NEXT: LBB2_8: ## %else6
; SSE-NEXT: retq
; SSE-NEXT: LBB2_1: ## %cond.store
; SSE-NEXT: movlps %xmm2, (%rdi)
; SSE-NEXT: testb $2, %al
; SSE-NEXT: je LBB2_4
; SSE-NEXT: LBB2_3: ## %cond.store1
; SSE-NEXT: movhps %xmm2, 8(%rdi)
; SSE-NEXT: testb $4, %al
; SSE-NEXT: je LBB2_6
; SSE-NEXT: LBB2_5: ## %cond.store3
; SSE-NEXT: movlps %xmm3, 16(%rdi)
; SSE-NEXT: testb $8, %al
; SSE-NEXT: je LBB2_8
; SSE-NEXT: LBB2_7: ## %cond.store5
; SSE-NEXT: movhps %xmm3, 24(%rdi)
; SSE-NEXT: retq
[X86][SSE] Add SSE2/SSE42 masked load/store tests Now that the load/store tests are split the impact of running the tests on multiple (illegal) targets is a lot less impactful llvm-svn: 346896
2018-11-15 05:31:50 +08:00
;
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; AVX1OR2-LABEL: store_v4f64_v4i64:
; AVX1OR2: ## %bb.0:
; AVX1OR2-NEXT: vmaskmovpd %ymm1, %ymm0, (%rdi)
; AVX1OR2-NEXT: vzeroupper
; AVX1OR2-NEXT: retq
[X86] Split masked load/store test files llvm-svn: 346889
2018-11-15 04:44:59 +08:00
;
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; AVX512F-LABEL: store_v4f64_v4i64:
[X86] Split masked load/store test files llvm-svn: 346889
2018-11-15 04:44:59 +08:00
; AVX512F: ## %bb.0:
; AVX512F-NEXT: ## kill: def $ymm1 killed $ymm1 def $zmm1
; AVX512F-NEXT: ## kill: def $ymm0 killed $ymm0 def $zmm0
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; AVX512F-NEXT: vpxor %xmm2, %xmm2, %xmm2
; AVX512F-NEXT: vpcmpgtq %zmm0, %zmm2, %k0
; AVX512F-NEXT: kshiftlw $12, %k0, %k0
; AVX512F-NEXT: kshiftrw $12, %k0, %k1
; AVX512F-NEXT: vmovupd %zmm1, (%rdi) {%k1}
[X86] Split masked load/store test files llvm-svn: 346889
2018-11-15 04:44:59 +08:00
; AVX512F-NEXT: vzeroupper
; AVX512F-NEXT: retq
;
[X86][AVX] Add AVX512DQ coverage for masked memory ops tests (PR34584) llvm-svn: 359395
2019-04-28 18:02:34 +08:00
; AVX512VLDQ-LABEL: store_v4f64_v4i64:
; AVX512VLDQ: ## %bb.0:
; AVX512VLDQ-NEXT: vpmovq2m %ymm0, %k1
; AVX512VLDQ-NEXT: vmovupd %ymm1, (%rdi) {%k1}
; AVX512VLDQ-NEXT: vzeroupper
; AVX512VLDQ-NEXT: retq
;
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; AVX512VLBW-LABEL: store_v4f64_v4i64:
[X86][SSE] Add SSE2/SSE42 masked load/store tests Now that the load/store tests are split the impact of running the tests on multiple (illegal) targets is a lot less impactful llvm-svn: 346896
2018-11-15 05:31:50 +08:00
; AVX512VLBW: ## %bb.0:
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; AVX512VLBW-NEXT: vpxor %xmm2, %xmm2, %xmm2
; AVX512VLBW-NEXT: vpcmpgtq %ymm0, %ymm2, %k1
; AVX512VLBW-NEXT: vmovupd %ymm1, (%rdi) {%k1}
[X86][SSE] Add SSE2/SSE42 masked load/store tests Now that the load/store tests are split the impact of running the tests on multiple (illegal) targets is a lot less impactful llvm-svn: 346896
2018-11-15 05:31:50 +08:00
; AVX512VLBW-NEXT: vzeroupper
; AVX512VLBW-NEXT: retq
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
%mask = icmp slt <4 x i64> %trigger, zeroinitializer
call void @llvm.masked.store.v4f64.p0v4f64(<4 x double> %val, <4 x double>* %addr, i32 4, <4 x i1> %mask)
[X86] Split masked load/store test files llvm-svn: 346889
2018-11-15 04:44:59 +08:00
ret void
}
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
;
; vXf32
;
[X86] Split masked load/store test files llvm-svn: 346889
2018-11-15 04:44:59 +08:00
define void @store_v2f32_v2i32(<2 x i32> %trigger, <2 x float>* %addr, <2 x float> %val) {
[X86][SSE] Add SSE2/SSE42 masked load/store tests Now that the load/store tests are split the impact of running the tests on multiple (illegal) targets is a lot less impactful llvm-svn: 346896
2018-11-15 05:31:50 +08:00
; SSE2-LABEL: store_v2f32_v2i32:
; SSE2: ## %bb.0:
; SSE2-NEXT: pxor %xmm2, %xmm2
; SSE2-NEXT: pcmpeqd %xmm0, %xmm2
Recommit r367901 "[X86] Enable -x86-experimental-vector-widening-legalization by default." The assert that caused this to be reverted should be fixed now. Original commit message: This patch changes our defualt legalization behavior for 16, 32, and 64 bit vectors with i8/i16/i32/i64 scalar types from promotion to widening. For example, v8i8 will now be widened to v16i8 instead of promoted to v8i16. This keeps the elements widths the same and pads with undef elements. We believe this is a better legalization strategy. But it carries some issues due to the fragmented vector ISA. For example, i8 shifts and multiplies get widened and then later have to be promoted/split into vXi16 vectors. This has the potential to cause regressions so we wanted to get it in early in the 10.0 cycle so we have plenty of time to address them. Next steps will be to merge tests that explicitly test the command line option. And then we can remove the option and its associated code. llvm-svn: 368183
2019-08-08 00:24:26 +08:00
; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm2[0,0,1,1]
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE2-NEXT: movmskpd %xmm0, %eax
[X86][SSE] Add SSE2/SSE42 masked load/store tests Now that the load/store tests are split the impact of running the tests on multiple (illegal) targets is a lot less impactful llvm-svn: 346896
2018-11-15 05:31:50 +08:00
; SSE2-NEXT: testb $1, %al
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE2-NEXT: jne LBB3_1
; SSE2-NEXT: ## %bb.2: ## %else
; SSE2-NEXT: testb $2, %al
; SSE2-NEXT: jne LBB3_3
; SSE2-NEXT: LBB3_4: ## %else2
; SSE2-NEXT: retq
; SSE2-NEXT: LBB3_1: ## %cond.store
[X86][SSE] Add SSE2/SSE42 masked load/store tests Now that the load/store tests are split the impact of running the tests on multiple (illegal) targets is a lot less impactful llvm-svn: 346896
2018-11-15 05:31:50 +08:00
; SSE2-NEXT: movss %xmm1, (%rdi)
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE2-NEXT: testb $2, %al
[X86][SSE] Add SSE2/SSE42 masked load/store tests Now that the load/store tests are split the impact of running the tests on multiple (illegal) targets is a lot less impactful llvm-svn: 346896
2018-11-15 05:31:50 +08:00
; SSE2-NEXT: je LBB3_4
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE2-NEXT: LBB3_3: ## %cond.store1
[X86][SSE] Add SSE2/SSE42 masked load/store tests Now that the load/store tests are split the impact of running the tests on multiple (illegal) targets is a lot less impactful llvm-svn: 346896
2018-11-15 05:31:50 +08:00
; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[1,1,2,3]
; SSE2-NEXT: movss %xmm1, 4(%rdi)
; SSE2-NEXT: retq
;
; SSE4-LABEL: store_v2f32_v2i32:
; SSE4: ## %bb.0:
; SSE4-NEXT: pxor %xmm2, %xmm2
Recommit r367901 "[X86] Enable -x86-experimental-vector-widening-legalization by default." The assert that caused this to be reverted should be fixed now. Original commit message: This patch changes our defualt legalization behavior for 16, 32, and 64 bit vectors with i8/i16/i32/i64 scalar types from promotion to widening. For example, v8i8 will now be widened to v16i8 instead of promoted to v8i16. This keeps the elements widths the same and pads with undef elements. We believe this is a better legalization strategy. But it carries some issues due to the fragmented vector ISA. For example, i8 shifts and multiplies get widened and then later have to be promoted/split into vXi16 vectors. This has the potential to cause regressions so we wanted to get it in early in the 10.0 cycle so we have plenty of time to address them. Next steps will be to merge tests that explicitly test the command line option. And then we can remove the option and its associated code. llvm-svn: 368183
2019-08-08 00:24:26 +08:00
; SSE4-NEXT: pcmpeqd %xmm0, %xmm2
; SSE4-NEXT: pmovsxdq %xmm2, %xmm0
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE4-NEXT: movmskpd %xmm0, %eax
[X86][SSE] Add SSE2/SSE42 masked load/store tests Now that the load/store tests are split the impact of running the tests on multiple (illegal) targets is a lot less impactful llvm-svn: 346896
2018-11-15 05:31:50 +08:00
; SSE4-NEXT: testb $1, %al
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE4-NEXT: jne LBB3_1
; SSE4-NEXT: ## %bb.2: ## %else
; SSE4-NEXT: testb $2, %al
; SSE4-NEXT: jne LBB3_3
; SSE4-NEXT: LBB3_4: ## %else2
; SSE4-NEXT: retq
; SSE4-NEXT: LBB3_1: ## %cond.store
[X86][SSE] Add SSE2/SSE42 masked load/store tests Now that the load/store tests are split the impact of running the tests on multiple (illegal) targets is a lot less impactful llvm-svn: 346896
2018-11-15 05:31:50 +08:00
; SSE4-NEXT: movss %xmm1, (%rdi)
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE4-NEXT: testb $2, %al
[X86][SSE] Add SSE2/SSE42 masked load/store tests Now that the load/store tests are split the impact of running the tests on multiple (illegal) targets is a lot less impactful llvm-svn: 346896
2018-11-15 05:31:50 +08:00
; SSE4-NEXT: je LBB3_4
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE4-NEXT: LBB3_3: ## %cond.store1
[X86][SSE] Add SSE2/SSE42 masked load/store tests Now that the load/store tests are split the impact of running the tests on multiple (illegal) targets is a lot less impactful llvm-svn: 346896
2018-11-15 05:31:50 +08:00
; SSE4-NEXT: extractps $1, %xmm1, 4(%rdi)
; SSE4-NEXT: retq
;
Recommit r367901 "[X86] Enable -x86-experimental-vector-widening-legalization by default." The assert that caused this to be reverted should be fixed now. Original commit message: This patch changes our defualt legalization behavior for 16, 32, and 64 bit vectors with i8/i16/i32/i64 scalar types from promotion to widening. For example, v8i8 will now be widened to v16i8 instead of promoted to v8i16. This keeps the elements widths the same and pads with undef elements. We believe this is a better legalization strategy. But it carries some issues due to the fragmented vector ISA. For example, i8 shifts and multiplies get widened and then later have to be promoted/split into vXi16 vectors. This has the potential to cause regressions so we wanted to get it in early in the 10.0 cycle so we have plenty of time to address them. Next steps will be to merge tests that explicitly test the command line option. And then we can remove the option and its associated code. llvm-svn: 368183
2019-08-08 00:24:26 +08:00
; AVX1OR2-LABEL: store_v2f32_v2i32:
; AVX1OR2: ## %bb.0:
; AVX1OR2-NEXT: vpxor %xmm2, %xmm2, %xmm2
; AVX1OR2-NEXT: vpcmpeqd %xmm2, %xmm0, %xmm0
; AVX1OR2-NEXT: vmovq {{.*#+}} xmm0 = xmm0[0],zero
; AVX1OR2-NEXT: vmaskmovps %xmm1, %xmm0, (%rdi)
; AVX1OR2-NEXT: retq
[X86] Split masked load/store test files llvm-svn: 346889
2018-11-15 04:44:59 +08:00
;
; AVX512F-LABEL: store_v2f32_v2i32:
; AVX512F: ## %bb.0:
; AVX512F-NEXT: ## kill: def $xmm1 killed $xmm1 def $zmm1
Recommit r367901 "[X86] Enable -x86-experimental-vector-widening-legalization by default." The assert that caused this to be reverted should be fixed now. Original commit message: This patch changes our defualt legalization behavior for 16, 32, and 64 bit vectors with i8/i16/i32/i64 scalar types from promotion to widening. For example, v8i8 will now be widened to v16i8 instead of promoted to v8i16. This keeps the elements widths the same and pads with undef elements. We believe this is a better legalization strategy. But it carries some issues due to the fragmented vector ISA. For example, i8 shifts and multiplies get widened and then later have to be promoted/split into vXi16 vectors. This has the potential to cause regressions so we wanted to get it in early in the 10.0 cycle so we have plenty of time to address them. Next steps will be to merge tests that explicitly test the command line option. And then we can remove the option and its associated code. llvm-svn: 368183
2019-08-08 00:24:26 +08:00
; AVX512F-NEXT: ## kill: def $xmm0 killed $xmm0 def $zmm0
; AVX512F-NEXT: vptestnmd %zmm0, %zmm0, %k0
[X86] Split masked load/store test files llvm-svn: 346889
2018-11-15 04:44:59 +08:00
; AVX512F-NEXT: kshiftlw $14, %k0, %k0
; AVX512F-NEXT: kshiftrw $14, %k0, %k1
; AVX512F-NEXT: vmovups %zmm1, (%rdi) {%k1}
; AVX512F-NEXT: vzeroupper
; AVX512F-NEXT: retq
;
Recommit r367901 "[X86] Enable -x86-experimental-vector-widening-legalization by default." The assert that caused this to be reverted should be fixed now. Original commit message: This patch changes our defualt legalization behavior for 16, 32, and 64 bit vectors with i8/i16/i32/i64 scalar types from promotion to widening. For example, v8i8 will now be widened to v16i8 instead of promoted to v8i16. This keeps the elements widths the same and pads with undef elements. We believe this is a better legalization strategy. But it carries some issues due to the fragmented vector ISA. For example, i8 shifts and multiplies get widened and then later have to be promoted/split into vXi16 vectors. This has the potential to cause regressions so we wanted to get it in early in the 10.0 cycle so we have plenty of time to address them. Next steps will be to merge tests that explicitly test the command line option. And then we can remove the option and its associated code. llvm-svn: 368183
2019-08-08 00:24:26 +08:00
; AVX512VLDQ-LABEL: store_v2f32_v2i32:
; AVX512VLDQ: ## %bb.0:
; AVX512VLDQ-NEXT: vptestnmd %xmm0, %xmm0, %k0
; AVX512VLDQ-NEXT: kshiftlb $6, %k0, %k0
; AVX512VLDQ-NEXT: kshiftrb $6, %k0, %k1
; AVX512VLDQ-NEXT: vmovups %xmm1, (%rdi) {%k1}
; AVX512VLDQ-NEXT: retq
;
; AVX512VLBW-LABEL: store_v2f32_v2i32:
; AVX512VLBW: ## %bb.0:
; AVX512VLBW-NEXT: vptestnmd %xmm0, %xmm0, %k0
; AVX512VLBW-NEXT: kshiftlw $14, %k0, %k0
; AVX512VLBW-NEXT: kshiftrw $14, %k0, %k1
; AVX512VLBW-NEXT: vmovups %xmm1, (%rdi) {%k1}
; AVX512VLBW-NEXT: retq
[X86] Split masked load/store test files llvm-svn: 346889
2018-11-15 04:44:59 +08:00
%mask = icmp eq <2 x i32> %trigger, zeroinitializer
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
call void @llvm.masked.store.v2f32.p0v2f32(<2 x float> %val, <2 x float>* %addr, i32 4, <2 x i1> %mask)
[X86] Split masked load/store test files llvm-svn: 346889
2018-11-15 04:44:59 +08:00
ret void
}
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
define void @store_v4f32_v4i32(<4 x float> %x, <4 x float>* %ptr, <4 x float> %y, <4 x i32> %mask) {
; SSE2-LABEL: store_v4f32_v4i32:
[X86][SSE] Add SSE2/SSE42 masked load/store tests Now that the load/store tests are split the impact of running the tests on multiple (illegal) targets is a lot less impactful llvm-svn: 346896
2018-11-15 05:31:50 +08:00
; SSE2: ## %bb.0:
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE2-NEXT: movmskps %xmm2, %eax
[X86][SSE] Add SSE2/SSE42 masked load/store tests Now that the load/store tests are split the impact of running the tests on multiple (illegal) targets is a lot less impactful llvm-svn: 346896
2018-11-15 05:31:50 +08:00
; SSE2-NEXT: testb $1, %al
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE2-NEXT: jne LBB4_1
; SSE2-NEXT: ## %bb.2: ## %else
; SSE2-NEXT: testb $2, %al
; SSE2-NEXT: jne LBB4_3
; SSE2-NEXT: LBB4_4: ## %else2
; SSE2-NEXT: testb $4, %al
; SSE2-NEXT: jne LBB4_5
; SSE2-NEXT: LBB4_6: ## %else4
; SSE2-NEXT: testb $8, %al
; SSE2-NEXT: jne LBB4_7
; SSE2-NEXT: LBB4_8: ## %else6
; SSE2-NEXT: retq
; SSE2-NEXT: LBB4_1: ## %cond.store
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; SSE2-NEXT: movss %xmm0, (%rdi)
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE2-NEXT: testb $2, %al
[X86][SSE] Add SSE2/SSE42 masked load/store tests Now that the load/store tests are split the impact of running the tests on multiple (illegal) targets is a lot less impactful llvm-svn: 346896
2018-11-15 05:31:50 +08:00
; SSE2-NEXT: je LBB4_4
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE2-NEXT: LBB4_3: ## %cond.store1
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; SSE2-NEXT: movaps %xmm0, %xmm1
; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[1,1],xmm0[2,3]
; SSE2-NEXT: movss %xmm1, 4(%rdi)
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE2-NEXT: testb $4, %al
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; SSE2-NEXT: je LBB4_6
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE2-NEXT: LBB4_5: ## %cond.store3
; SSE2-NEXT: movaps %xmm0, %xmm1
; SSE2-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm0[1]
; SSE2-NEXT: movss %xmm1, 8(%rdi)
; SSE2-NEXT: testb $8, %al
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; SSE2-NEXT: je LBB4_8
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE2-NEXT: LBB4_7: ## %cond.store5
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[3,1,2,3]
; SSE2-NEXT: movss %xmm0, 12(%rdi)
[X86][SSE] Add SSE2/SSE42 masked load/store tests Now that the load/store tests are split the impact of running the tests on multiple (illegal) targets is a lot less impactful llvm-svn: 346896
2018-11-15 05:31:50 +08:00
; SSE2-NEXT: retq
;
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; SSE4-LABEL: store_v4f32_v4i32:
[X86][SSE] Add SSE2/SSE42 masked load/store tests Now that the load/store tests are split the impact of running the tests on multiple (illegal) targets is a lot less impactful llvm-svn: 346896
2018-11-15 05:31:50 +08:00
; SSE4: ## %bb.0:
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE4-NEXT: movmskps %xmm2, %eax
[X86][SSE] Add SSE2/SSE42 masked load/store tests Now that the load/store tests are split the impact of running the tests on multiple (illegal) targets is a lot less impactful llvm-svn: 346896
2018-11-15 05:31:50 +08:00
; SSE4-NEXT: testb $1, %al
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE4-NEXT: jne LBB4_1
; SSE4-NEXT: ## %bb.2: ## %else
; SSE4-NEXT: testb $2, %al
; SSE4-NEXT: jne LBB4_3
; SSE4-NEXT: LBB4_4: ## %else2
; SSE4-NEXT: testb $4, %al
; SSE4-NEXT: jne LBB4_5
; SSE4-NEXT: LBB4_6: ## %else4
; SSE4-NEXT: testb $8, %al
; SSE4-NEXT: jne LBB4_7
; SSE4-NEXT: LBB4_8: ## %else6
; SSE4-NEXT: retq
; SSE4-NEXT: LBB4_1: ## %cond.store
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; SSE4-NEXT: movss %xmm0, (%rdi)
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE4-NEXT: testb $2, %al
[X86][SSE] Add SSE2/SSE42 masked load/store tests Now that the load/store tests are split the impact of running the tests on multiple (illegal) targets is a lot less impactful llvm-svn: 346896
2018-11-15 05:31:50 +08:00
; SSE4-NEXT: je LBB4_4
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE4-NEXT: LBB4_3: ## %cond.store1
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; SSE4-NEXT: extractps $1, %xmm0, 4(%rdi)
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE4-NEXT: testb $4, %al
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; SSE4-NEXT: je LBB4_6
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE4-NEXT: LBB4_5: ## %cond.store3
[X86][SSE] Add SSE2/SSE42 masked load/store tests Now that the load/store tests are split the impact of running the tests on multiple (illegal) targets is a lot less impactful llvm-svn: 346896
2018-11-15 05:31:50 +08:00
; SSE4-NEXT: extractps $2, %xmm0, 8(%rdi)
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE4-NEXT: testb $8, %al
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; SSE4-NEXT: je LBB4_8
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE4-NEXT: LBB4_7: ## %cond.store5
[X86][SSE] Add SSE2/SSE42 masked load/store tests Now that the load/store tests are split the impact of running the tests on multiple (illegal) targets is a lot less impactful llvm-svn: 346896
2018-11-15 05:31:50 +08:00
; SSE4-NEXT: extractps $3, %xmm0, 12(%rdi)
; SSE4-NEXT: retq
;
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; AVX1OR2-LABEL: store_v4f32_v4i32:
[X86][SSE] Add SSE2/SSE42 masked load/store tests Now that the load/store tests are split the impact of running the tests on multiple (illegal) targets is a lot less impactful llvm-svn: 346896
2018-11-15 05:31:50 +08:00
; AVX1OR2: ## %bb.0:
; AVX1OR2-NEXT: vmaskmovps %xmm0, %xmm2, (%rdi)
; AVX1OR2-NEXT: retq
[X86] Split masked load/store test files llvm-svn: 346889
2018-11-15 04:44:59 +08:00
;
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; AVX512F-LABEL: store_v4f32_v4i32:
[X86] Split masked load/store test files llvm-svn: 346889
2018-11-15 04:44:59 +08:00
; AVX512F: ## %bb.0:
; AVX512F-NEXT: ## kill: def $xmm2 killed $xmm2 def $zmm2
; AVX512F-NEXT: ## kill: def $xmm0 killed $xmm0 def $zmm0
; AVX512F-NEXT: vpxor %xmm1, %xmm1, %xmm1
; AVX512F-NEXT: vpcmpgtd %zmm2, %zmm1, %k0
; AVX512F-NEXT: kshiftlw $12, %k0, %k0
; AVX512F-NEXT: kshiftrw $12, %k0, %k1
; AVX512F-NEXT: vmovups %zmm0, (%rdi) {%k1}
; AVX512F-NEXT: vzeroupper
; AVX512F-NEXT: retq
;
[X86][AVX] Add AVX512DQ coverage for masked memory ops tests (PR34584) llvm-svn: 359395
2019-04-28 18:02:34 +08:00
; AVX512VLDQ-LABEL: store_v4f32_v4i32:
; AVX512VLDQ: ## %bb.0:
; AVX512VLDQ-NEXT: vpmovd2m %xmm2, %k1
; AVX512VLDQ-NEXT: vmovups %xmm0, (%rdi) {%k1}
; AVX512VLDQ-NEXT: retq
;
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; AVX512VLBW-LABEL: store_v4f32_v4i32:
[X86][SSE] Add SSE2/SSE42 masked load/store tests Now that the load/store tests are split the impact of running the tests on multiple (illegal) targets is a lot less impactful llvm-svn: 346896
2018-11-15 05:31:50 +08:00
; AVX512VLBW: ## %bb.0:
; AVX512VLBW-NEXT: vpxor %xmm1, %xmm1, %xmm1
; AVX512VLBW-NEXT: vpcmpgtd %xmm2, %xmm1, %k1
; AVX512VLBW-NEXT: vmovups %xmm0, (%rdi) {%k1}
; AVX512VLBW-NEXT: retq
[X86] Split masked load/store test files llvm-svn: 346889
2018-11-15 04:44:59 +08:00
%bool_mask = icmp slt <4 x i32> %mask, zeroinitializer
call void @llvm.masked.store.v4f32.p0v4f32(<4 x float> %x, <4 x float>* %ptr, i32 1, <4 x i1> %bool_mask)
ret void
}
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
define void @store_v8f32_v8i32(<8 x float> %x, <8 x float>* %ptr, <8 x float> %y, <8 x i32> %mask) {
; SSE2-LABEL: store_v8f32_v8i32:
[X86][SSE] Add SSE2/SSE42 masked load/store tests Now that the load/store tests are split the impact of running the tests on multiple (illegal) targets is a lot less impactful llvm-svn: 346896
2018-11-15 05:31:50 +08:00
; SSE2: ## %bb.0:
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE2-NEXT: packssdw %xmm5, %xmm4
; SSE2-NEXT: packsswb %xmm0, %xmm4
; SSE2-NEXT: pmovmskb %xmm4, %eax
[X86][SSE] Add SSE2/SSE42 masked load/store tests Now that the load/store tests are split the impact of running the tests on multiple (illegal) targets is a lot less impactful llvm-svn: 346896
2018-11-15 05:31:50 +08:00
; SSE2-NEXT: testb $1, %al
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE2-NEXT: jne LBB5_1
; SSE2-NEXT: ## %bb.2: ## %else
; SSE2-NEXT: testb $2, %al
; SSE2-NEXT: jne LBB5_3
; SSE2-NEXT: LBB5_4: ## %else2
; SSE2-NEXT: testb $4, %al
; SSE2-NEXT: jne LBB5_5
; SSE2-NEXT: LBB5_6: ## %else4
; SSE2-NEXT: testb $8, %al
; SSE2-NEXT: jne LBB5_7
; SSE2-NEXT: LBB5_8: ## %else6
; SSE2-NEXT: testb $16, %al
; SSE2-NEXT: jne LBB5_9
; SSE2-NEXT: LBB5_10: ## %else8
; SSE2-NEXT: testb $32, %al
; SSE2-NEXT: jne LBB5_11
; SSE2-NEXT: LBB5_12: ## %else10
; SSE2-NEXT: testb $64, %al
; SSE2-NEXT: jne LBB5_13
; SSE2-NEXT: LBB5_14: ## %else12
; SSE2-NEXT: testb $-128, %al
; SSE2-NEXT: jne LBB5_15
; SSE2-NEXT: LBB5_16: ## %else14
; SSE2-NEXT: retq
; SSE2-NEXT: LBB5_1: ## %cond.store
[X86][AVX] Add PR34584 masked store test cases llvm-svn: 357757
2019-04-05 19:34:30 +08:00
; SSE2-NEXT: movd %xmm0, (%rdi)
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE2-NEXT: testb $2, %al
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; SSE2-NEXT: je LBB5_4
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE2-NEXT: LBB5_3: ## %cond.store1
[X86][AVX] Add PR34584 masked store test cases llvm-svn: 357757
2019-04-05 19:34:30 +08:00
; SSE2-NEXT: movdqa %xmm0, %xmm2
; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[1,1],xmm0[2,3]
; SSE2-NEXT: movss %xmm2, 4(%rdi)
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE2-NEXT: testb $4, %al
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; SSE2-NEXT: je LBB5_6
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE2-NEXT: LBB5_5: ## %cond.store3
; SSE2-NEXT: movaps %xmm0, %xmm2
; SSE2-NEXT: unpckhpd {{.*#+}} xmm2 = xmm2[1],xmm0[1]
; SSE2-NEXT: movss %xmm2, 8(%rdi)
; SSE2-NEXT: testb $8, %al
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; SSE2-NEXT: je LBB5_8
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE2-NEXT: LBB5_7: ## %cond.store5
[X86][AVX] Add PR34584 masked store test cases llvm-svn: 357757
2019-04-05 19:34:30 +08:00
; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[3,1,2,3]
; SSE2-NEXT: movss %xmm0, 12(%rdi)
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE2-NEXT: testb $16, %al
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; SSE2-NEXT: je LBB5_10
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE2-NEXT: LBB5_9: ## %cond.store7
[X86][AVX] Add PR34584 masked store test cases llvm-svn: 357757
2019-04-05 19:34:30 +08:00
; SSE2-NEXT: movss %xmm1, 16(%rdi)
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE2-NEXT: testb $32, %al
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; SSE2-NEXT: je LBB5_12
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE2-NEXT: LBB5_11: ## %cond.store9
[X86][AVX] Add PR34584 masked store test cases llvm-svn: 357757
2019-04-05 19:34:30 +08:00
; SSE2-NEXT: movaps %xmm1, %xmm0
; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[1,1],xmm1[2,3]
; SSE2-NEXT: movss %xmm0, 20(%rdi)
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE2-NEXT: testb $64, %al
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; SSE2-NEXT: je LBB5_14
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE2-NEXT: LBB5_13: ## %cond.store11
; SSE2-NEXT: movaps %xmm1, %xmm0
; SSE2-NEXT: unpckhpd {{.*#+}} xmm0 = xmm0[1],xmm1[1]
; SSE2-NEXT: movss %xmm0, 24(%rdi)
; SSE2-NEXT: testb $-128, %al
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; SSE2-NEXT: je LBB5_16
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE2-NEXT: LBB5_15: ## %cond.store13
[X86][AVX] Add PR34584 masked store test cases llvm-svn: 357757
2019-04-05 19:34:30 +08:00
; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[3,1,2,3]
; SSE2-NEXT: movss %xmm1, 28(%rdi)
[X86][SSE] Add SSE2/SSE42 masked load/store tests Now that the load/store tests are split the impact of running the tests on multiple (illegal) targets is a lot less impactful llvm-svn: 346896
2018-11-15 05:31:50 +08:00
; SSE2-NEXT: retq
;
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; SSE4-LABEL: store_v8f32_v8i32:
[X86][SSE] Add SSE2/SSE42 masked load/store tests Now that the load/store tests are split the impact of running the tests on multiple (illegal) targets is a lot less impactful llvm-svn: 346896
2018-11-15 05:31:50 +08:00
; SSE4: ## %bb.0:
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE4-NEXT: packssdw %xmm5, %xmm4
; SSE4-NEXT: packsswb %xmm0, %xmm4
; SSE4-NEXT: pmovmskb %xmm4, %eax
[X86][SSE] Add SSE2/SSE42 masked load/store tests Now that the load/store tests are split the impact of running the tests on multiple (illegal) targets is a lot less impactful llvm-svn: 346896
2018-11-15 05:31:50 +08:00
; SSE4-NEXT: testb $1, %al
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE4-NEXT: jne LBB5_1
; SSE4-NEXT: ## %bb.2: ## %else
; SSE4-NEXT: testb $2, %al
; SSE4-NEXT: jne LBB5_3
; SSE4-NEXT: LBB5_4: ## %else2
; SSE4-NEXT: testb $4, %al
; SSE4-NEXT: jne LBB5_5
; SSE4-NEXT: LBB5_6: ## %else4
; SSE4-NEXT: testb $8, %al
; SSE4-NEXT: jne LBB5_7
; SSE4-NEXT: LBB5_8: ## %else6
; SSE4-NEXT: testb $16, %al
; SSE4-NEXT: jne LBB5_9
; SSE4-NEXT: LBB5_10: ## %else8
; SSE4-NEXT: testb $32, %al
; SSE4-NEXT: jne LBB5_11
; SSE4-NEXT: LBB5_12: ## %else10
; SSE4-NEXT: testb $64, %al
; SSE4-NEXT: jne LBB5_13
; SSE4-NEXT: LBB5_14: ## %else12
; SSE4-NEXT: testb $-128, %al
; SSE4-NEXT: jne LBB5_15
; SSE4-NEXT: LBB5_16: ## %else14
; SSE4-NEXT: retq
; SSE4-NEXT: LBB5_1: ## %cond.store
[X86][AVX] Add PR34584 masked store test cases llvm-svn: 357757
2019-04-05 19:34:30 +08:00
; SSE4-NEXT: movd %xmm0, (%rdi)
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE4-NEXT: testb $2, %al
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; SSE4-NEXT: je LBB5_4
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE4-NEXT: LBB5_3: ## %cond.store1
[X86][AVX] Add PR34584 masked store test cases llvm-svn: 357757
2019-04-05 19:34:30 +08:00
; SSE4-NEXT: pextrd $1, %xmm0, 4(%rdi)
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE4-NEXT: testb $4, %al
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; SSE4-NEXT: je LBB5_6
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE4-NEXT: LBB5_5: ## %cond.store3
[X86][AVX] Add PR34584 masked store test cases llvm-svn: 357757
2019-04-05 19:34:30 +08:00
; SSE4-NEXT: pextrd $2, %xmm0, 8(%rdi)
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE4-NEXT: testb $8, %al
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; SSE4-NEXT: je LBB5_8
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE4-NEXT: LBB5_7: ## %cond.store5
[X86][AVX] Add PR34584 masked store test cases llvm-svn: 357757
2019-04-05 19:34:30 +08:00
; SSE4-NEXT: pextrd $3, %xmm0, 12(%rdi)
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE4-NEXT: testb $16, %al
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; SSE4-NEXT: je LBB5_10
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE4-NEXT: LBB5_9: ## %cond.store7
[X86][AVX] Add PR34584 masked store test cases llvm-svn: 357757
2019-04-05 19:34:30 +08:00
; SSE4-NEXT: movss %xmm1, 16(%rdi)
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE4-NEXT: testb $32, %al
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; SSE4-NEXT: je LBB5_12
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE4-NEXT: LBB5_11: ## %cond.store9
[X86][AVX] Add PR34584 masked store test cases llvm-svn: 357757
2019-04-05 19:34:30 +08:00
; SSE4-NEXT: extractps $1, %xmm1, 20(%rdi)
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE4-NEXT: testb $64, %al
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; SSE4-NEXT: je LBB5_14
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE4-NEXT: LBB5_13: ## %cond.store11
[X86][AVX] Add PR34584 masked store test cases llvm-svn: 357757
2019-04-05 19:34:30 +08:00
; SSE4-NEXT: extractps $2, %xmm1, 24(%rdi)
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE4-NEXT: testb $-128, %al
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; SSE4-NEXT: je LBB5_16
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE4-NEXT: LBB5_15: ## %cond.store13
[X86][AVX] Add PR34584 masked store test cases llvm-svn: 357757
2019-04-05 19:34:30 +08:00
; SSE4-NEXT: extractps $3, %xmm1, 28(%rdi)
; SSE4-NEXT: retq
;
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; AVX1OR2-LABEL: store_v8f32_v8i32:
[X86][AVX] Add PR34584 masked store test cases llvm-svn: 357757
2019-04-05 19:34:30 +08:00
; AVX1OR2: ## %bb.0:
; AVX1OR2-NEXT: vmaskmovps %ymm0, %ymm2, (%rdi)
; AVX1OR2-NEXT: vzeroupper
; AVX1OR2-NEXT: retq
;
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; AVX512F-LABEL: store_v8f32_v8i32:
[X86][AVX] Add PR34584 masked store test cases llvm-svn: 357757
2019-04-05 19:34:30 +08:00
; AVX512F: ## %bb.0:
; AVX512F-NEXT: ## kill: def $ymm2 killed $ymm2 def $zmm2
; AVX512F-NEXT: ## kill: def $ymm0 killed $ymm0 def $zmm0
; AVX512F-NEXT: vpxor %xmm1, %xmm1, %xmm1
; AVX512F-NEXT: vpcmpgtd %zmm2, %zmm1, %k0
; AVX512F-NEXT: kshiftlw $8, %k0, %k0
; AVX512F-NEXT: kshiftrw $8, %k0, %k1
; AVX512F-NEXT: vmovups %zmm0, (%rdi) {%k1}
; AVX512F-NEXT: vzeroupper
; AVX512F-NEXT: retq
;
[X86][AVX] Add AVX512DQ coverage for masked memory ops tests (PR34584) llvm-svn: 359395
2019-04-28 18:02:34 +08:00
; AVX512VLDQ-LABEL: store_v8f32_v8i32:
; AVX512VLDQ: ## %bb.0:
; AVX512VLDQ-NEXT: vpmovd2m %ymm2, %k1
; AVX512VLDQ-NEXT: vmovups %ymm0, (%rdi) {%k1}
; AVX512VLDQ-NEXT: vzeroupper
; AVX512VLDQ-NEXT: retq
;
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; AVX512VLBW-LABEL: store_v8f32_v8i32:
[X86][AVX] Add PR34584 masked store test cases llvm-svn: 357757
2019-04-05 19:34:30 +08:00
; AVX512VLBW: ## %bb.0:
; AVX512VLBW-NEXT: vpxor %xmm1, %xmm1, %xmm1
; AVX512VLBW-NEXT: vpcmpgtd %ymm2, %ymm1, %k1
; AVX512VLBW-NEXT: vmovups %ymm0, (%rdi) {%k1}
; AVX512VLBW-NEXT: vzeroupper
; AVX512VLBW-NEXT: retq
%bool_mask = icmp slt <8 x i32> %mask, zeroinitializer
call void @llvm.masked.store.v8f32.p0v8f32(<8 x float> %x, <8 x float>* %ptr, i32 1, <8 x i1> %bool_mask)
ret void
}
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
define void @store_v16f32_v16i32(<16 x float> %x, <16 x float>* %ptr, <16 x float> %y, <16 x i32> %mask) {
; SSE2-LABEL: store_v16f32_v16i32:
[X86][AVX] Add PR34584 masked store test cases llvm-svn: 357757
2019-04-05 19:34:30 +08:00
; SSE2: ## %bb.0:
; SSE2-NEXT: movdqa {{[0-9]+}}(%rsp), %xmm4
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE2-NEXT: movdqa {{[0-9]+}}(%rsp), %xmm5
; SSE2-NEXT: packssdw {{[0-9]+}}(%rsp), %xmm5
; SSE2-NEXT: packssdw {{[0-9]+}}(%rsp), %xmm4
; SSE2-NEXT: packsswb %xmm5, %xmm4
; SSE2-NEXT: pmovmskb %xmm4, %eax
[X86][AVX] Add PR34584 masked store test cases llvm-svn: 357757
2019-04-05 19:34:30 +08:00
; SSE2-NEXT: testb $1, %al
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE2-NEXT: jne LBB6_1
; SSE2-NEXT: ## %bb.2: ## %else
; SSE2-NEXT: testb $2, %al
; SSE2-NEXT: jne LBB6_3
; SSE2-NEXT: LBB6_4: ## %else2
; SSE2-NEXT: testb $4, %al
; SSE2-NEXT: jne LBB6_5
; SSE2-NEXT: LBB6_6: ## %else4
; SSE2-NEXT: testb $8, %al
; SSE2-NEXT: jne LBB6_7
; SSE2-NEXT: LBB6_8: ## %else6
; SSE2-NEXT: testb $16, %al
; SSE2-NEXT: jne LBB6_9
; SSE2-NEXT: LBB6_10: ## %else8
; SSE2-NEXT: testb $32, %al
; SSE2-NEXT: jne LBB6_11
; SSE2-NEXT: LBB6_12: ## %else10
; SSE2-NEXT: testb $64, %al
; SSE2-NEXT: jne LBB6_13
; SSE2-NEXT: LBB6_14: ## %else12
; SSE2-NEXT: testb $-128, %al
; SSE2-NEXT: jne LBB6_15
; SSE2-NEXT: LBB6_16: ## %else14
; SSE2-NEXT: testl $256, %eax ## imm = 0x100
; SSE2-NEXT: jne LBB6_17
; SSE2-NEXT: LBB6_18: ## %else16
; SSE2-NEXT: testl $512, %eax ## imm = 0x200
; SSE2-NEXT: jne LBB6_19
; SSE2-NEXT: LBB6_20: ## %else18
; SSE2-NEXT: testl $1024, %eax ## imm = 0x400
; SSE2-NEXT: jne LBB6_21
; SSE2-NEXT: LBB6_22: ## %else20
; SSE2-NEXT: testl $2048, %eax ## imm = 0x800
; SSE2-NEXT: jne LBB6_23
; SSE2-NEXT: LBB6_24: ## %else22
; SSE2-NEXT: testl $4096, %eax ## imm = 0x1000
; SSE2-NEXT: jne LBB6_25
; SSE2-NEXT: LBB6_26: ## %else24
; SSE2-NEXT: testl $8192, %eax ## imm = 0x2000
; SSE2-NEXT: jne LBB6_27
; SSE2-NEXT: LBB6_28: ## %else26
; SSE2-NEXT: testl $16384, %eax ## imm = 0x4000
; SSE2-NEXT: jne LBB6_29
; SSE2-NEXT: LBB6_30: ## %else28
; SSE2-NEXT: testl $32768, %eax ## imm = 0x8000
; SSE2-NEXT: jne LBB6_31
; SSE2-NEXT: LBB6_32: ## %else30
; SSE2-NEXT: retq
; SSE2-NEXT: LBB6_1: ## %cond.store
[X86][AVX] Add PR34584 masked store test cases llvm-svn: 357757
2019-04-05 19:34:30 +08:00
; SSE2-NEXT: movss %xmm0, (%rdi)
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE2-NEXT: testb $2, %al
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; SSE2-NEXT: je LBB6_4
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE2-NEXT: LBB6_3: ## %cond.store1
; SSE2-NEXT: movaps %xmm0, %xmm4
; SSE2-NEXT: shufps {{.*#+}} xmm4 = xmm4[1,1],xmm0[2,3]
; SSE2-NEXT: movss %xmm4, 4(%rdi)
; SSE2-NEXT: testb $4, %al
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; SSE2-NEXT: je LBB6_6
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE2-NEXT: LBB6_5: ## %cond.store3
[X86][AVX] Add PR34584 masked store test cases llvm-svn: 357757
2019-04-05 19:34:30 +08:00
; SSE2-NEXT: movaps %xmm0, %xmm4
; SSE2-NEXT: unpckhpd {{.*#+}} xmm4 = xmm4[1],xmm0[1]
; SSE2-NEXT: movss %xmm4, 8(%rdi)
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE2-NEXT: testb $8, %al
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; SSE2-NEXT: je LBB6_8
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE2-NEXT: LBB6_7: ## %cond.store5
[X86][AVX] Add PR34584 masked store test cases llvm-svn: 357757
2019-04-05 19:34:30 +08:00
; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[3,1,2,3]
; SSE2-NEXT: movss %xmm0, 12(%rdi)
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE2-NEXT: testb $16, %al
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; SSE2-NEXT: je LBB6_10
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE2-NEXT: LBB6_9: ## %cond.store7
[X86][AVX] Add PR34584 masked store test cases llvm-svn: 357757
2019-04-05 19:34:30 +08:00
; SSE2-NEXT: movss %xmm1, 16(%rdi)
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE2-NEXT: testb $32, %al
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; SSE2-NEXT: je LBB6_12
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE2-NEXT: LBB6_11: ## %cond.store9
[X86][AVX] Add PR34584 masked store test cases llvm-svn: 357757
2019-04-05 19:34:30 +08:00
; SSE2-NEXT: movaps %xmm1, %xmm0
; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[1,1],xmm1[2,3]
; SSE2-NEXT: movss %xmm0, 20(%rdi)
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE2-NEXT: testb $64, %al
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; SSE2-NEXT: je LBB6_14
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE2-NEXT: LBB6_13: ## %cond.store11
[X86][AVX] Add PR34584 masked store test cases llvm-svn: 357757
2019-04-05 19:34:30 +08:00
; SSE2-NEXT: movaps %xmm1, %xmm0
; SSE2-NEXT: unpckhpd {{.*#+}} xmm0 = xmm0[1],xmm1[1]
; SSE2-NEXT: movss %xmm0, 24(%rdi)
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE2-NEXT: testb $-128, %al
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; SSE2-NEXT: je LBB6_16
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE2-NEXT: LBB6_15: ## %cond.store13
[X86][AVX] Add PR34584 masked store test cases llvm-svn: 357757
2019-04-05 19:34:30 +08:00
; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[3,1,2,3]
; SSE2-NEXT: movss %xmm1, 28(%rdi)
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE2-NEXT: testl $256, %eax ## imm = 0x100
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; SSE2-NEXT: je LBB6_18
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE2-NEXT: LBB6_17: ## %cond.store15
[X86][AVX] Add PR34584 masked store test cases llvm-svn: 357757
2019-04-05 19:34:30 +08:00
; SSE2-NEXT: movss %xmm2, 32(%rdi)
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE2-NEXT: testl $512, %eax ## imm = 0x200
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; SSE2-NEXT: je LBB6_20
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE2-NEXT: LBB6_19: ## %cond.store17
; SSE2-NEXT: movaps %xmm2, %xmm0
; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[1,1],xmm2[2,3]
; SSE2-NEXT: movss %xmm0, 36(%rdi)
; SSE2-NEXT: testl $1024, %eax ## imm = 0x400
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; SSE2-NEXT: je LBB6_22
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE2-NEXT: LBB6_21: ## %cond.store19
[X86][AVX] Add PR34584 masked store test cases llvm-svn: 357757
2019-04-05 19:34:30 +08:00
; SSE2-NEXT: movaps %xmm2, %xmm0
; SSE2-NEXT: unpckhpd {{.*#+}} xmm0 = xmm0[1],xmm2[1]
; SSE2-NEXT: movss %xmm0, 40(%rdi)
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE2-NEXT: testl $2048, %eax ## imm = 0x800
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; SSE2-NEXT: je LBB6_24
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE2-NEXT: LBB6_23: ## %cond.store21
[X86][AVX] Add PR34584 masked store test cases llvm-svn: 357757
2019-04-05 19:34:30 +08:00
; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[3,1,2,3]
; SSE2-NEXT: movss %xmm2, 44(%rdi)
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE2-NEXT: testl $4096, %eax ## imm = 0x1000
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; SSE2-NEXT: je LBB6_26
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE2-NEXT: LBB6_25: ## %cond.store23
[X86][AVX] Add PR34584 masked store test cases llvm-svn: 357757
2019-04-05 19:34:30 +08:00
; SSE2-NEXT: movss %xmm3, 48(%rdi)
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE2-NEXT: testl $8192, %eax ## imm = 0x2000
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; SSE2-NEXT: je LBB6_28
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE2-NEXT: LBB6_27: ## %cond.store25
; SSE2-NEXT: movaps %xmm3, %xmm0
; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[1,1],xmm3[2,3]
; SSE2-NEXT: movss %xmm0, 52(%rdi)
; SSE2-NEXT: testl $16384, %eax ## imm = 0x4000
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; SSE2-NEXT: je LBB6_30
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE2-NEXT: LBB6_29: ## %cond.store27
[X86][AVX] Add PR34584 masked store test cases llvm-svn: 357757
2019-04-05 19:34:30 +08:00
; SSE2-NEXT: movaps %xmm3, %xmm0
; SSE2-NEXT: unpckhpd {{.*#+}} xmm0 = xmm0[1],xmm3[1]
; SSE2-NEXT: movss %xmm0, 56(%rdi)
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE2-NEXT: testl $32768, %eax ## imm = 0x8000
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; SSE2-NEXT: je LBB6_32
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE2-NEXT: LBB6_31: ## %cond.store29
[X86][AVX] Add PR34584 masked store test cases llvm-svn: 357757
2019-04-05 19:34:30 +08:00
; SSE2-NEXT: shufps {{.*#+}} xmm3 = xmm3[3,1,2,3]
; SSE2-NEXT: movss %xmm3, 60(%rdi)
; SSE2-NEXT: retq
;
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; SSE4-LABEL: store_v16f32_v16i32:
[X86][AVX] Add PR34584 masked store test cases llvm-svn: 357757
2019-04-05 19:34:30 +08:00
; SSE4: ## %bb.0:
; SSE4-NEXT: movdqa {{[0-9]+}}(%rsp), %xmm4
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE4-NEXT: movdqa {{[0-9]+}}(%rsp), %xmm5
; SSE4-NEXT: packssdw {{[0-9]+}}(%rsp), %xmm5
; SSE4-NEXT: packssdw {{[0-9]+}}(%rsp), %xmm4
; SSE4-NEXT: packsswb %xmm5, %xmm4
; SSE4-NEXT: pmovmskb %xmm4, %eax
[X86][AVX] Add PR34584 masked store test cases llvm-svn: 357757
2019-04-05 19:34:30 +08:00
; SSE4-NEXT: testb $1, %al
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE4-NEXT: jne LBB6_1
; SSE4-NEXT: ## %bb.2: ## %else
; SSE4-NEXT: testb $2, %al
; SSE4-NEXT: jne LBB6_3
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; SSE4-NEXT: LBB6_4: ## %else2
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE4-NEXT: testb $4, %al
; SSE4-NEXT: jne LBB6_5
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; SSE4-NEXT: LBB6_6: ## %else4
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE4-NEXT: testb $8, %al
; SSE4-NEXT: jne LBB6_7
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; SSE4-NEXT: LBB6_8: ## %else6
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE4-NEXT: testb $16, %al
; SSE4-NEXT: jne LBB6_9
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; SSE4-NEXT: LBB6_10: ## %else8
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE4-NEXT: testb $32, %al
; SSE4-NEXT: jne LBB6_11
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; SSE4-NEXT: LBB6_12: ## %else10
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE4-NEXT: testb $64, %al
; SSE4-NEXT: jne LBB6_13
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; SSE4-NEXT: LBB6_14: ## %else12
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE4-NEXT: testb $-128, %al
; SSE4-NEXT: jne LBB6_15
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; SSE4-NEXT: LBB6_16: ## %else14
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE4-NEXT: testl $256, %eax ## imm = 0x100
; SSE4-NEXT: jne LBB6_17
; SSE4-NEXT: LBB6_18: ## %else16
; SSE4-NEXT: testl $512, %eax ## imm = 0x200
; SSE4-NEXT: jne LBB6_19
; SSE4-NEXT: LBB6_20: ## %else18
; SSE4-NEXT: testl $1024, %eax ## imm = 0x400
; SSE4-NEXT: jne LBB6_21
; SSE4-NEXT: LBB6_22: ## %else20
; SSE4-NEXT: testl $2048, %eax ## imm = 0x800
; SSE4-NEXT: jne LBB6_23
; SSE4-NEXT: LBB6_24: ## %else22
; SSE4-NEXT: testl $4096, %eax ## imm = 0x1000
; SSE4-NEXT: jne LBB6_25
; SSE4-NEXT: LBB6_26: ## %else24
; SSE4-NEXT: testl $8192, %eax ## imm = 0x2000
; SSE4-NEXT: jne LBB6_27
; SSE4-NEXT: LBB6_28: ## %else26
; SSE4-NEXT: testl $16384, %eax ## imm = 0x4000
; SSE4-NEXT: jne LBB6_29
; SSE4-NEXT: LBB6_30: ## %else28
; SSE4-NEXT: testl $32768, %eax ## imm = 0x8000
; SSE4-NEXT: jne LBB6_31
; SSE4-NEXT: LBB6_32: ## %else30
; SSE4-NEXT: retq
; SSE4-NEXT: LBB6_1: ## %cond.store
; SSE4-NEXT: movss %xmm0, (%rdi)
; SSE4-NEXT: testb $2, %al
; SSE4-NEXT: je LBB6_4
; SSE4-NEXT: LBB6_3: ## %cond.store1
; SSE4-NEXT: extractps $1, %xmm0, 4(%rdi)
; SSE4-NEXT: testb $4, %al
; SSE4-NEXT: je LBB6_6
; SSE4-NEXT: LBB6_5: ## %cond.store3
; SSE4-NEXT: extractps $2, %xmm0, 8(%rdi)
; SSE4-NEXT: testb $8, %al
; SSE4-NEXT: je LBB6_8
; SSE4-NEXT: LBB6_7: ## %cond.store5
; SSE4-NEXT: extractps $3, %xmm0, 12(%rdi)
; SSE4-NEXT: testb $16, %al
; SSE4-NEXT: je LBB6_10
; SSE4-NEXT: LBB6_9: ## %cond.store7
; SSE4-NEXT: movss %xmm1, 16(%rdi)
; SSE4-NEXT: testb $32, %al
; SSE4-NEXT: je LBB6_12
; SSE4-NEXT: LBB6_11: ## %cond.store9
; SSE4-NEXT: extractps $1, %xmm1, 20(%rdi)
; SSE4-NEXT: testb $64, %al
; SSE4-NEXT: je LBB6_14
; SSE4-NEXT: LBB6_13: ## %cond.store11
; SSE4-NEXT: extractps $2, %xmm1, 24(%rdi)
; SSE4-NEXT: testb $-128, %al
; SSE4-NEXT: je LBB6_16
; SSE4-NEXT: LBB6_15: ## %cond.store13
; SSE4-NEXT: extractps $3, %xmm1, 28(%rdi)
; SSE4-NEXT: testl $256, %eax ## imm = 0x100
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; SSE4-NEXT: je LBB6_18
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE4-NEXT: LBB6_17: ## %cond.store15
[X86][AVX] Add PR34584 masked store test cases llvm-svn: 357757
2019-04-05 19:34:30 +08:00
; SSE4-NEXT: movss %xmm2, 32(%rdi)
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE4-NEXT: testl $512, %eax ## imm = 0x200
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; SSE4-NEXT: je LBB6_20
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE4-NEXT: LBB6_19: ## %cond.store17
[X86][AVX] Add PR34584 masked store test cases llvm-svn: 357757
2019-04-05 19:34:30 +08:00
; SSE4-NEXT: extractps $1, %xmm2, 36(%rdi)
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE4-NEXT: testl $1024, %eax ## imm = 0x400
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; SSE4-NEXT: je LBB6_22
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE4-NEXT: LBB6_21: ## %cond.store19
[X86][AVX] Add PR34584 masked store test cases llvm-svn: 357757
2019-04-05 19:34:30 +08:00
; SSE4-NEXT: extractps $2, %xmm2, 40(%rdi)
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE4-NEXT: testl $2048, %eax ## imm = 0x800
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; SSE4-NEXT: je LBB6_24
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE4-NEXT: LBB6_23: ## %cond.store21
[X86][AVX] Add PR34584 masked store test cases llvm-svn: 357757
2019-04-05 19:34:30 +08:00
; SSE4-NEXT: extractps $3, %xmm2, 44(%rdi)
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE4-NEXT: testl $4096, %eax ## imm = 0x1000
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; SSE4-NEXT: je LBB6_26
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE4-NEXT: LBB6_25: ## %cond.store23
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; SSE4-NEXT: movss %xmm3, 48(%rdi)
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE4-NEXT: testl $8192, %eax ## imm = 0x2000
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; SSE4-NEXT: je LBB6_28
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE4-NEXT: LBB6_27: ## %cond.store25
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; SSE4-NEXT: extractps $1, %xmm3, 52(%rdi)
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE4-NEXT: testl $16384, %eax ## imm = 0x4000
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; SSE4-NEXT: je LBB6_30
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE4-NEXT: LBB6_29: ## %cond.store27
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; SSE4-NEXT: extractps $2, %xmm3, 56(%rdi)
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE4-NEXT: testl $32768, %eax ## imm = 0x8000
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; SSE4-NEXT: je LBB6_32
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE4-NEXT: LBB6_31: ## %cond.store29
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; SSE4-NEXT: extractps $3, %xmm3, 60(%rdi)
; SSE4-NEXT: retq
;
; AVX1OR2-LABEL: store_v16f32_v16i32:
; AVX1OR2: ## %bb.0:
; AVX1OR2-NEXT: vmaskmovps %ymm1, %ymm5, 32(%rdi)
; AVX1OR2-NEXT: vmaskmovps %ymm0, %ymm4, (%rdi)
; AVX1OR2-NEXT: vzeroupper
; AVX1OR2-NEXT: retq
;
[X86][AVX] Add AVX512DQ coverage for masked memory ops tests (PR34584) llvm-svn: 359395
2019-04-28 18:02:34 +08:00
; AVX512F-LABEL: store_v16f32_v16i32:
; AVX512F: ## %bb.0:
; AVX512F-NEXT: vpxor %xmm1, %xmm1, %xmm1
; AVX512F-NEXT: vpcmpgtd %zmm2, %zmm1, %k1
; AVX512F-NEXT: vmovups %zmm0, (%rdi) {%k1}
; AVX512F-NEXT: vzeroupper
; AVX512F-NEXT: retq
;
; AVX512VLDQ-LABEL: store_v16f32_v16i32:
; AVX512VLDQ: ## %bb.0:
; AVX512VLDQ-NEXT: vpmovd2m %zmm2, %k1
; AVX512VLDQ-NEXT: vmovups %zmm0, (%rdi) {%k1}
; AVX512VLDQ-NEXT: vzeroupper
; AVX512VLDQ-NEXT: retq
;
; AVX512VLBW-LABEL: store_v16f32_v16i32:
; AVX512VLBW: ## %bb.0:
; AVX512VLBW-NEXT: vpxor %xmm1, %xmm1, %xmm1
; AVX512VLBW-NEXT: vpcmpgtd %zmm2, %zmm1, %k1
; AVX512VLBW-NEXT: vmovups %zmm0, (%rdi) {%k1}
; AVX512VLBW-NEXT: vzeroupper
; AVX512VLBW-NEXT: retq
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
%bool_mask = icmp slt <16 x i32> %mask, zeroinitializer
call void @llvm.masked.store.v16f32.p0v16f32(<16 x float> %x, <16 x float>* %ptr, i32 1, <16 x i1> %bool_mask)
ret void
}
;
; vXi64
;
define void @store_v2i64_v2i64(<2 x i64> %trigger, <2 x i64>* %addr, <2 x i64> %val) {
; SSE2-LABEL: store_v2i64_v2i64:
; SSE2: ## %bb.0:
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE2-NEXT: movmskpd %xmm0, %eax
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; SSE2-NEXT: testb $1, %al
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE2-NEXT: jne LBB7_1
; SSE2-NEXT: ## %bb.2: ## %else
; SSE2-NEXT: testb $2, %al
; SSE2-NEXT: jne LBB7_3
; SSE2-NEXT: LBB7_4: ## %else2
; SSE2-NEXT: retq
; SSE2-NEXT: LBB7_1: ## %cond.store
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; SSE2-NEXT: movq %xmm1, (%rdi)
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE2-NEXT: testb $2, %al
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; SSE2-NEXT: je LBB7_4
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE2-NEXT: LBB7_3: ## %cond.store1
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm1[2,3,0,1]
; SSE2-NEXT: movq %xmm0, 8(%rdi)
; SSE2-NEXT: retq
;
; SSE4-LABEL: store_v2i64_v2i64:
; SSE4: ## %bb.0:
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE4-NEXT: movmskpd %xmm0, %eax
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; SSE4-NEXT: testb $1, %al
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE4-NEXT: jne LBB7_1
; SSE4-NEXT: ## %bb.2: ## %else
; SSE4-NEXT: testb $2, %al
; SSE4-NEXT: jne LBB7_3
; SSE4-NEXT: LBB7_4: ## %else2
; SSE4-NEXT: retq
; SSE4-NEXT: LBB7_1: ## %cond.store
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; SSE4-NEXT: movq %xmm1, (%rdi)
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE4-NEXT: testb $2, %al
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; SSE4-NEXT: je LBB7_4
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE4-NEXT: LBB7_3: ## %cond.store1
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; SSE4-NEXT: pextrq $1, %xmm1, 8(%rdi)
; SSE4-NEXT: retq
;
; AVX1-LABEL: store_v2i64_v2i64:
; AVX1: ## %bb.0:
; AVX1-NEXT: vmaskmovpd %xmm1, %xmm0, (%rdi)
; AVX1-NEXT: retq
;
; AVX2-LABEL: store_v2i64_v2i64:
; AVX2: ## %bb.0:
; AVX2-NEXT: vpmaskmovq %xmm1, %xmm0, (%rdi)
; AVX2-NEXT: retq
;
; AVX512F-LABEL: store_v2i64_v2i64:
; AVX512F: ## %bb.0:
; AVX512F-NEXT: ## kill: def $xmm1 killed $xmm1 def $zmm1
; AVX512F-NEXT: ## kill: def $xmm0 killed $xmm0 def $zmm0
; AVX512F-NEXT: vpxor %xmm2, %xmm2, %xmm2
; AVX512F-NEXT: vpcmpgtq %zmm0, %zmm2, %k0
; AVX512F-NEXT: kshiftlw $14, %k0, %k0
; AVX512F-NEXT: kshiftrw $14, %k0, %k1
; AVX512F-NEXT: vmovdqu64 %zmm1, (%rdi) {%k1}
; AVX512F-NEXT: vzeroupper
; AVX512F-NEXT: retq
;
[X86][AVX] Add AVX512DQ coverage for masked memory ops tests (PR34584) llvm-svn: 359395
2019-04-28 18:02:34 +08:00
; AVX512VLDQ-LABEL: store_v2i64_v2i64:
; AVX512VLDQ: ## %bb.0:
; AVX512VLDQ-NEXT: vpmovq2m %xmm0, %k1
; AVX512VLDQ-NEXT: vmovdqu64 %xmm1, (%rdi) {%k1}
; AVX512VLDQ-NEXT: retq
;
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; AVX512VLBW-LABEL: store_v2i64_v2i64:
; AVX512VLBW: ## %bb.0:
; AVX512VLBW-NEXT: vpxor %xmm2, %xmm2, %xmm2
; AVX512VLBW-NEXT: vpcmpgtq %xmm0, %xmm2, %k1
; AVX512VLBW-NEXT: vmovdqu64 %xmm1, (%rdi) {%k1}
; AVX512VLBW-NEXT: retq
%mask = icmp slt <2 x i64> %trigger, zeroinitializer
call void @llvm.masked.store.v2i64.p0v2i64(<2 x i64> %val, <2 x i64>* %addr, i32 4, <2 x i1> %mask)
ret void
}
define void @store_v4i64_v4i64(<4 x i64> %trigger, <4 x i64>* %addr, <4 x i64> %val) {
; SSE2-LABEL: store_v4i64_v4i64:
; SSE2: ## %bb.0:
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE2-NEXT: packssdw %xmm1, %xmm0
; SSE2-NEXT: movmskps %xmm0, %eax
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; SSE2-NEXT: testb $1, %al
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE2-NEXT: jne LBB8_1
; SSE2-NEXT: ## %bb.2: ## %else
; SSE2-NEXT: testb $2, %al
; SSE2-NEXT: jne LBB8_3
; SSE2-NEXT: LBB8_4: ## %else2
; SSE2-NEXT: testb $4, %al
; SSE2-NEXT: jne LBB8_5
; SSE2-NEXT: LBB8_6: ## %else4
; SSE2-NEXT: testb $8, %al
; SSE2-NEXT: jne LBB8_7
; SSE2-NEXT: LBB8_8: ## %else6
; SSE2-NEXT: retq
; SSE2-NEXT: LBB8_1: ## %cond.store
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; SSE2-NEXT: movq %xmm2, (%rdi)
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE2-NEXT: testb $2, %al
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; SSE2-NEXT: je LBB8_4
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE2-NEXT: LBB8_3: ## %cond.store1
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm2[2,3,0,1]
; SSE2-NEXT: movq %xmm0, 8(%rdi)
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE2-NEXT: testb $4, %al
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; SSE2-NEXT: je LBB8_6
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE2-NEXT: LBB8_5: ## %cond.store3
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; SSE2-NEXT: movq %xmm3, 16(%rdi)
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE2-NEXT: testb $8, %al
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; SSE2-NEXT: je LBB8_8
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE2-NEXT: LBB8_7: ## %cond.store5
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm3[2,3,0,1]
; SSE2-NEXT: movq %xmm0, 24(%rdi)
; SSE2-NEXT: retq
;
; SSE4-LABEL: store_v4i64_v4i64:
; SSE4: ## %bb.0:
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE4-NEXT: packssdw %xmm1, %xmm0
; SSE4-NEXT: movmskps %xmm0, %eax
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; SSE4-NEXT: testb $1, %al
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE4-NEXT: jne LBB8_1
; SSE4-NEXT: ## %bb.2: ## %else
; SSE4-NEXT: testb $2, %al
; SSE4-NEXT: jne LBB8_3
; SSE4-NEXT: LBB8_4: ## %else2
; SSE4-NEXT: testb $4, %al
; SSE4-NEXT: jne LBB8_5
; SSE4-NEXT: LBB8_6: ## %else4
; SSE4-NEXT: testb $8, %al
; SSE4-NEXT: jne LBB8_7
; SSE4-NEXT: LBB8_8: ## %else6
; SSE4-NEXT: retq
; SSE4-NEXT: LBB8_1: ## %cond.store
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; SSE4-NEXT: movq %xmm2, (%rdi)
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE4-NEXT: testb $2, %al
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; SSE4-NEXT: je LBB8_4
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE4-NEXT: LBB8_3: ## %cond.store1
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; SSE4-NEXT: pextrq $1, %xmm2, 8(%rdi)
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE4-NEXT: testb $4, %al
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; SSE4-NEXT: je LBB8_6
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE4-NEXT: LBB8_5: ## %cond.store3
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; SSE4-NEXT: movq %xmm3, 16(%rdi)
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE4-NEXT: testb $8, %al
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; SSE4-NEXT: je LBB8_8
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE4-NEXT: LBB8_7: ## %cond.store5
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; SSE4-NEXT: pextrq $1, %xmm3, 24(%rdi)
; SSE4-NEXT: retq
;
; AVX1-LABEL: store_v4i64_v4i64:
; AVX1: ## %bb.0:
; AVX1-NEXT: vmaskmovpd %ymm1, %ymm0, (%rdi)
; AVX1-NEXT: vzeroupper
; AVX1-NEXT: retq
;
; AVX2-LABEL: store_v4i64_v4i64:
; AVX2: ## %bb.0:
; AVX2-NEXT: vpmaskmovq %ymm1, %ymm0, (%rdi)
; AVX2-NEXT: vzeroupper
; AVX2-NEXT: retq
;
; AVX512F-LABEL: store_v4i64_v4i64:
; AVX512F: ## %bb.0:
; AVX512F-NEXT: ## kill: def $ymm1 killed $ymm1 def $zmm1
; AVX512F-NEXT: ## kill: def $ymm0 killed $ymm0 def $zmm0
; AVX512F-NEXT: vpxor %xmm2, %xmm2, %xmm2
; AVX512F-NEXT: vpcmpgtq %zmm0, %zmm2, %k0
; AVX512F-NEXT: kshiftlw $12, %k0, %k0
; AVX512F-NEXT: kshiftrw $12, %k0, %k1
; AVX512F-NEXT: vmovdqu64 %zmm1, (%rdi) {%k1}
; AVX512F-NEXT: vzeroupper
; AVX512F-NEXT: retq
;
[X86][AVX] Add AVX512DQ coverage for masked memory ops tests (PR34584) llvm-svn: 359395
2019-04-28 18:02:34 +08:00
; AVX512VLDQ-LABEL: store_v4i64_v4i64:
; AVX512VLDQ: ## %bb.0:
; AVX512VLDQ-NEXT: vpmovq2m %ymm0, %k1
; AVX512VLDQ-NEXT: vmovdqu64 %ymm1, (%rdi) {%k1}
; AVX512VLDQ-NEXT: vzeroupper
; AVX512VLDQ-NEXT: retq
;
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; AVX512VLBW-LABEL: store_v4i64_v4i64:
; AVX512VLBW: ## %bb.0:
; AVX512VLBW-NEXT: vpxor %xmm2, %xmm2, %xmm2
; AVX512VLBW-NEXT: vpcmpgtq %ymm0, %ymm2, %k1
; AVX512VLBW-NEXT: vmovdqu64 %ymm1, (%rdi) {%k1}
; AVX512VLBW-NEXT: vzeroupper
; AVX512VLBW-NEXT: retq
%mask = icmp slt <4 x i64> %trigger, zeroinitializer
call void @llvm.masked.store.v4i64.p0v4i64(<4 x i64> %val, <4 x i64>* %addr, i32 4, <4 x i1> %mask)
ret void
}
;
; vXi32
;
define void @store_v1i32_v1i32(<1 x i32> %trigger, <1 x i32>* %addr, <1 x i32> %val) {
; SSE-LABEL: store_v1i32_v1i32:
; SSE: ## %bb.0:
; SSE-NEXT: testl %edi, %edi
; SSE-NEXT: jne LBB9_2
; SSE-NEXT: ## %bb.1: ## %cond.store
; SSE-NEXT: movl %edx, (%rsi)
; SSE-NEXT: LBB9_2: ## %else
; SSE-NEXT: retq
;
; AVX-LABEL: store_v1i32_v1i32:
; AVX: ## %bb.0:
; AVX-NEXT: testl %edi, %edi
; AVX-NEXT: jne LBB9_2
; AVX-NEXT: ## %bb.1: ## %cond.store
; AVX-NEXT: movl %edx, (%rsi)
; AVX-NEXT: LBB9_2: ## %else
; AVX-NEXT: retq
%mask = icmp eq <1 x i32> %trigger, zeroinitializer
call void @llvm.masked.store.v1i32.p0v1i32(<1 x i32> %val, <1 x i32>* %addr, i32 4, <1 x i1> %mask)
ret void
}
define void @store_v2i32_v2i32(<2 x i32> %trigger, <2 x i32>* %addr, <2 x i32> %val) {
; SSE2-LABEL: store_v2i32_v2i32:
; SSE2: ## %bb.0:
; SSE2-NEXT: pxor %xmm2, %xmm2
; SSE2-NEXT: pcmpeqd %xmm0, %xmm2
Recommit r367901 "[X86] Enable -x86-experimental-vector-widening-legalization by default." The assert that caused this to be reverted should be fixed now. Original commit message: This patch changes our defualt legalization behavior for 16, 32, and 64 bit vectors with i8/i16/i32/i64 scalar types from promotion to widening. For example, v8i8 will now be widened to v16i8 instead of promoted to v8i16. This keeps the elements widths the same and pads with undef elements. We believe this is a better legalization strategy. But it carries some issues due to the fragmented vector ISA. For example, i8 shifts and multiplies get widened and then later have to be promoted/split into vXi16 vectors. This has the potential to cause regressions so we wanted to get it in early in the 10.0 cycle so we have plenty of time to address them. Next steps will be to merge tests that explicitly test the command line option. And then we can remove the option and its associated code. llvm-svn: 368183
2019-08-08 00:24:26 +08:00
; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm2[0,0,1,1]
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE2-NEXT: movmskpd %xmm0, %eax
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; SSE2-NEXT: testb $1, %al
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE2-NEXT: jne LBB10_1
; SSE2-NEXT: ## %bb.2: ## %else
; SSE2-NEXT: testb $2, %al
; SSE2-NEXT: jne LBB10_3
; SSE2-NEXT: LBB10_4: ## %else2
; SSE2-NEXT: retq
; SSE2-NEXT: LBB10_1: ## %cond.store
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; SSE2-NEXT: movd %xmm1, (%rdi)
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE2-NEXT: testb $2, %al
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; SSE2-NEXT: je LBB10_4
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE2-NEXT: LBB10_3: ## %cond.store1
Recommit r367901 "[X86] Enable -x86-experimental-vector-widening-legalization by default." The assert that caused this to be reverted should be fixed now. Original commit message: This patch changes our defualt legalization behavior for 16, 32, and 64 bit vectors with i8/i16/i32/i64 scalar types from promotion to widening. For example, v8i8 will now be widened to v16i8 instead of promoted to v8i16. This keeps the elements widths the same and pads with undef elements. We believe this is a better legalization strategy. But it carries some issues due to the fragmented vector ISA. For example, i8 shifts and multiplies get widened and then later have to be promoted/split into vXi16 vectors. This has the potential to cause regressions so we wanted to get it in early in the 10.0 cycle so we have plenty of time to address them. Next steps will be to merge tests that explicitly test the command line option. And then we can remove the option and its associated code. llvm-svn: 368183
2019-08-08 00:24:26 +08:00
; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm1[1,1,2,3]
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; SSE2-NEXT: movd %xmm0, 4(%rdi)
; SSE2-NEXT: retq
;
; SSE4-LABEL: store_v2i32_v2i32:
; SSE4: ## %bb.0:
; SSE4-NEXT: pxor %xmm2, %xmm2
Recommit r367901 "[X86] Enable -x86-experimental-vector-widening-legalization by default." The assert that caused this to be reverted should be fixed now. Original commit message: This patch changes our defualt legalization behavior for 16, 32, and 64 bit vectors with i8/i16/i32/i64 scalar types from promotion to widening. For example, v8i8 will now be widened to v16i8 instead of promoted to v8i16. This keeps the elements widths the same and pads with undef elements. We believe this is a better legalization strategy. But it carries some issues due to the fragmented vector ISA. For example, i8 shifts and multiplies get widened and then later have to be promoted/split into vXi16 vectors. This has the potential to cause regressions so we wanted to get it in early in the 10.0 cycle so we have plenty of time to address them. Next steps will be to merge tests that explicitly test the command line option. And then we can remove the option and its associated code. llvm-svn: 368183
2019-08-08 00:24:26 +08:00
; SSE4-NEXT: pcmpeqd %xmm0, %xmm2
; SSE4-NEXT: pmovsxdq %xmm2, %xmm0
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE4-NEXT: movmskpd %xmm0, %eax
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; SSE4-NEXT: testb $1, %al
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE4-NEXT: jne LBB10_1
; SSE4-NEXT: ## %bb.2: ## %else
; SSE4-NEXT: testb $2, %al
; SSE4-NEXT: jne LBB10_3
; SSE4-NEXT: LBB10_4: ## %else2
; SSE4-NEXT: retq
; SSE4-NEXT: LBB10_1: ## %cond.store
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; SSE4-NEXT: movss %xmm1, (%rdi)
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE4-NEXT: testb $2, %al
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; SSE4-NEXT: je LBB10_4
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE4-NEXT: LBB10_3: ## %cond.store1
Recommit r367901 "[X86] Enable -x86-experimental-vector-widening-legalization by default." The assert that caused this to be reverted should be fixed now. Original commit message: This patch changes our defualt legalization behavior for 16, 32, and 64 bit vectors with i8/i16/i32/i64 scalar types from promotion to widening. For example, v8i8 will now be widened to v16i8 instead of promoted to v8i16. This keeps the elements widths the same and pads with undef elements. We believe this is a better legalization strategy. But it carries some issues due to the fragmented vector ISA. For example, i8 shifts and multiplies get widened and then later have to be promoted/split into vXi16 vectors. This has the potential to cause regressions so we wanted to get it in early in the 10.0 cycle so we have plenty of time to address them. Next steps will be to merge tests that explicitly test the command line option. And then we can remove the option and its associated code. llvm-svn: 368183
2019-08-08 00:24:26 +08:00
; SSE4-NEXT: extractps $1, %xmm1, 4(%rdi)
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; SSE4-NEXT: retq
;
; AVX1-LABEL: store_v2i32_v2i32:
; AVX1: ## %bb.0:
; AVX1-NEXT: vpxor %xmm2, %xmm2, %xmm2
Recommit r367901 "[X86] Enable -x86-experimental-vector-widening-legalization by default." The assert that caused this to be reverted should be fixed now. Original commit message: This patch changes our defualt legalization behavior for 16, 32, and 64 bit vectors with i8/i16/i32/i64 scalar types from promotion to widening. For example, v8i8 will now be widened to v16i8 instead of promoted to v8i16. This keeps the elements widths the same and pads with undef elements. We believe this is a better legalization strategy. But it carries some issues due to the fragmented vector ISA. For example, i8 shifts and multiplies get widened and then later have to be promoted/split into vXi16 vectors. This has the potential to cause regressions so we wanted to get it in early in the 10.0 cycle so we have plenty of time to address them. Next steps will be to merge tests that explicitly test the command line option. And then we can remove the option and its associated code. llvm-svn: 368183
2019-08-08 00:24:26 +08:00
; AVX1-NEXT: vpcmpeqd %xmm2, %xmm0, %xmm0
; AVX1-NEXT: vmovq {{.*#+}} xmm0 = xmm0[0],zero
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; AVX1-NEXT: vmaskmovps %xmm1, %xmm0, (%rdi)
; AVX1-NEXT: retq
;
; AVX2-LABEL: store_v2i32_v2i32:
; AVX2: ## %bb.0:
; AVX2-NEXT: vpxor %xmm2, %xmm2, %xmm2
Recommit r367901 "[X86] Enable -x86-experimental-vector-widening-legalization by default." The assert that caused this to be reverted should be fixed now. Original commit message: This patch changes our defualt legalization behavior for 16, 32, and 64 bit vectors with i8/i16/i32/i64 scalar types from promotion to widening. For example, v8i8 will now be widened to v16i8 instead of promoted to v8i16. This keeps the elements widths the same and pads with undef elements. We believe this is a better legalization strategy. But it carries some issues due to the fragmented vector ISA. For example, i8 shifts and multiplies get widened and then later have to be promoted/split into vXi16 vectors. This has the potential to cause regressions so we wanted to get it in early in the 10.0 cycle so we have plenty of time to address them. Next steps will be to merge tests that explicitly test the command line option. And then we can remove the option and its associated code. llvm-svn: 368183
2019-08-08 00:24:26 +08:00
; AVX2-NEXT: vpcmpeqd %xmm2, %xmm0, %xmm0
; AVX2-NEXT: vmovq {{.*#+}} xmm0 = xmm0[0],zero
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; AVX2-NEXT: vpmaskmovd %xmm1, %xmm0, (%rdi)
; AVX2-NEXT: retq
;
; AVX512F-LABEL: store_v2i32_v2i32:
; AVX512F: ## %bb.0:
Recommit r367901 "[X86] Enable -x86-experimental-vector-widening-legalization by default." The assert that caused this to be reverted should be fixed now. Original commit message: This patch changes our defualt legalization behavior for 16, 32, and 64 bit vectors with i8/i16/i32/i64 scalar types from promotion to widening. For example, v8i8 will now be widened to v16i8 instead of promoted to v8i16. This keeps the elements widths the same and pads with undef elements. We believe this is a better legalization strategy. But it carries some issues due to the fragmented vector ISA. For example, i8 shifts and multiplies get widened and then later have to be promoted/split into vXi16 vectors. This has the potential to cause regressions so we wanted to get it in early in the 10.0 cycle so we have plenty of time to address them. Next steps will be to merge tests that explicitly test the command line option. And then we can remove the option and its associated code. llvm-svn: 368183
2019-08-08 00:24:26 +08:00
; AVX512F-NEXT: ## kill: def $xmm1 killed $xmm1 def $zmm1
; AVX512F-NEXT: ## kill: def $xmm0 killed $xmm0 def $zmm0
; AVX512F-NEXT: vptestnmd %zmm0, %zmm0, %k0
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; AVX512F-NEXT: kshiftlw $14, %k0, %k0
; AVX512F-NEXT: kshiftrw $14, %k0, %k1
Recommit r367901 "[X86] Enable -x86-experimental-vector-widening-legalization by default." The assert that caused this to be reverted should be fixed now. Original commit message: This patch changes our defualt legalization behavior for 16, 32, and 64 bit vectors with i8/i16/i32/i64 scalar types from promotion to widening. For example, v8i8 will now be widened to v16i8 instead of promoted to v8i16. This keeps the elements widths the same and pads with undef elements. We believe this is a better legalization strategy. But it carries some issues due to the fragmented vector ISA. For example, i8 shifts and multiplies get widened and then later have to be promoted/split into vXi16 vectors. This has the potential to cause regressions so we wanted to get it in early in the 10.0 cycle so we have plenty of time to address them. Next steps will be to merge tests that explicitly test the command line option. And then we can remove the option and its associated code. llvm-svn: 368183
2019-08-08 00:24:26 +08:00
; AVX512F-NEXT: vmovdqu32 %zmm1, (%rdi) {%k1}
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; AVX512F-NEXT: vzeroupper
; AVX512F-NEXT: retq
;
Recommit r367901 "[X86] Enable -x86-experimental-vector-widening-legalization by default." The assert that caused this to be reverted should be fixed now. Original commit message: This patch changes our defualt legalization behavior for 16, 32, and 64 bit vectors with i8/i16/i32/i64 scalar types from promotion to widening. For example, v8i8 will now be widened to v16i8 instead of promoted to v8i16. This keeps the elements widths the same and pads with undef elements. We believe this is a better legalization strategy. But it carries some issues due to the fragmented vector ISA. For example, i8 shifts and multiplies get widened and then later have to be promoted/split into vXi16 vectors. This has the potential to cause regressions so we wanted to get it in early in the 10.0 cycle so we have plenty of time to address them. Next steps will be to merge tests that explicitly test the command line option. And then we can remove the option and its associated code. llvm-svn: 368183
2019-08-08 00:24:26 +08:00
; AVX512VLDQ-LABEL: store_v2i32_v2i32:
; AVX512VLDQ: ## %bb.0:
; AVX512VLDQ-NEXT: vptestnmd %xmm0, %xmm0, %k0
; AVX512VLDQ-NEXT: kshiftlb $6, %k0, %k0
; AVX512VLDQ-NEXT: kshiftrb $6, %k0, %k1
; AVX512VLDQ-NEXT: vmovdqu32 %xmm1, (%rdi) {%k1}
; AVX512VLDQ-NEXT: retq
;
; AVX512VLBW-LABEL: store_v2i32_v2i32:
; AVX512VLBW: ## %bb.0:
; AVX512VLBW-NEXT: vptestnmd %xmm0, %xmm0, %k0
; AVX512VLBW-NEXT: kshiftlw $14, %k0, %k0
; AVX512VLBW-NEXT: kshiftrw $14, %k0, %k1
; AVX512VLBW-NEXT: vmovdqu32 %xmm1, (%rdi) {%k1}
; AVX512VLBW-NEXT: retq
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
%mask = icmp eq <2 x i32> %trigger, zeroinitializer
call void @llvm.masked.store.v2i32.p0v2i32(<2 x i32> %val, <2 x i32>* %addr, i32 4, <2 x i1> %mask)
ret void
}
define void @store_v4i32_v4i32(<4 x i32> %trigger, <4 x i32>* %addr, <4 x i32> %val) {
; SSE2-LABEL: store_v4i32_v4i32:
; SSE2: ## %bb.0:
; SSE2-NEXT: pxor %xmm2, %xmm2
; SSE2-NEXT: pcmpeqd %xmm0, %xmm2
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE2-NEXT: movmskps %xmm2, %eax
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; SSE2-NEXT: testb $1, %al
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE2-NEXT: jne LBB11_1
; SSE2-NEXT: ## %bb.2: ## %else
; SSE2-NEXT: testb $2, %al
; SSE2-NEXT: jne LBB11_3
; SSE2-NEXT: LBB11_4: ## %else2
; SSE2-NEXT: testb $4, %al
; SSE2-NEXT: jne LBB11_5
; SSE2-NEXT: LBB11_6: ## %else4
; SSE2-NEXT: testb $8, %al
; SSE2-NEXT: jne LBB11_7
; SSE2-NEXT: LBB11_8: ## %else6
; SSE2-NEXT: retq
; SSE2-NEXT: LBB11_1: ## %cond.store
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; SSE2-NEXT: movd %xmm1, (%rdi)
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE2-NEXT: testb $2, %al
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; SSE2-NEXT: je LBB11_4
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE2-NEXT: LBB11_3: ## %cond.store1
; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm1[1,1,2,3]
; SSE2-NEXT: movd %xmm0, 4(%rdi)
; SSE2-NEXT: testb $4, %al
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; SSE2-NEXT: je LBB11_6
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE2-NEXT: LBB11_5: ## %cond.store3
; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm1[2,3,0,1]
; SSE2-NEXT: movd %xmm0, 8(%rdi)
; SSE2-NEXT: testb $8, %al
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; SSE2-NEXT: je LBB11_8
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE2-NEXT: LBB11_7: ## %cond.store5
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm1[3,1,2,3]
; SSE2-NEXT: movd %xmm0, 12(%rdi)
; SSE2-NEXT: retq
;
; SSE4-LABEL: store_v4i32_v4i32:
; SSE4: ## %bb.0:
; SSE4-NEXT: pxor %xmm2, %xmm2
; SSE4-NEXT: pcmpeqd %xmm0, %xmm2
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE4-NEXT: movmskps %xmm2, %eax
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; SSE4-NEXT: testb $1, %al
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE4-NEXT: jne LBB11_1
; SSE4-NEXT: ## %bb.2: ## %else
; SSE4-NEXT: testb $2, %al
; SSE4-NEXT: jne LBB11_3
; SSE4-NEXT: LBB11_4: ## %else2
; SSE4-NEXT: testb $4, %al
; SSE4-NEXT: jne LBB11_5
; SSE4-NEXT: LBB11_6: ## %else4
; SSE4-NEXT: testb $8, %al
; SSE4-NEXT: jne LBB11_7
; SSE4-NEXT: LBB11_8: ## %else6
; SSE4-NEXT: retq
; SSE4-NEXT: LBB11_1: ## %cond.store
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; SSE4-NEXT: movss %xmm1, (%rdi)
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE4-NEXT: testb $2, %al
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; SSE4-NEXT: je LBB11_4
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE4-NEXT: LBB11_3: ## %cond.store1
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; SSE4-NEXT: extractps $1, %xmm1, 4(%rdi)
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE4-NEXT: testb $4, %al
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; SSE4-NEXT: je LBB11_6
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE4-NEXT: LBB11_5: ## %cond.store3
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; SSE4-NEXT: extractps $2, %xmm1, 8(%rdi)
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE4-NEXT: testb $8, %al
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; SSE4-NEXT: je LBB11_8
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE4-NEXT: LBB11_7: ## %cond.store5
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; SSE4-NEXT: extractps $3, %xmm1, 12(%rdi)
; SSE4-NEXT: retq
;
; AVX1-LABEL: store_v4i32_v4i32:
; AVX1: ## %bb.0:
; AVX1-NEXT: vpxor %xmm2, %xmm2, %xmm2
; AVX1-NEXT: vpcmpeqd %xmm2, %xmm0, %xmm0
; AVX1-NEXT: vmaskmovps %xmm1, %xmm0, (%rdi)
; AVX1-NEXT: retq
;
; AVX2-LABEL: store_v4i32_v4i32:
; AVX2: ## %bb.0:
; AVX2-NEXT: vpxor %xmm2, %xmm2, %xmm2
; AVX2-NEXT: vpcmpeqd %xmm2, %xmm0, %xmm0
; AVX2-NEXT: vpmaskmovd %xmm1, %xmm0, (%rdi)
; AVX2-NEXT: retq
;
; AVX512F-LABEL: store_v4i32_v4i32:
; AVX512F: ## %bb.0:
; AVX512F-NEXT: ## kill: def $xmm1 killed $xmm1 def $zmm1
; AVX512F-NEXT: ## kill: def $xmm0 killed $xmm0 def $zmm0
; AVX512F-NEXT: vptestnmd %zmm0, %zmm0, %k0
; AVX512F-NEXT: kshiftlw $12, %k0, %k0
; AVX512F-NEXT: kshiftrw $12, %k0, %k1
; AVX512F-NEXT: vmovdqu32 %zmm1, (%rdi) {%k1}
; AVX512F-NEXT: vzeroupper
; AVX512F-NEXT: retq
;
[X86][AVX] Add AVX512DQ coverage for masked memory ops tests (PR34584) llvm-svn: 359395
2019-04-28 18:02:34 +08:00
; AVX512VL-LABEL: store_v4i32_v4i32:
; AVX512VL: ## %bb.0:
; AVX512VL-NEXT: vptestnmd %xmm0, %xmm0, %k1
; AVX512VL-NEXT: vmovdqu32 %xmm1, (%rdi) {%k1}
; AVX512VL-NEXT: retq
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
%mask = icmp eq <4 x i32> %trigger, zeroinitializer
call void @llvm.masked.store.v4i32.p0v4i32(<4 x i32> %val, <4 x i32>* %addr, i32 4, <4 x i1> %mask)
ret void
}
define void @store_v8i32_v8i32(<8 x i32> %trigger, <8 x i32>* %addr, <8 x i32> %val) {
; SSE2-LABEL: store_v8i32_v8i32:
; SSE2: ## %bb.0:
; SSE2-NEXT: pxor %xmm4, %xmm4
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE2-NEXT: pcmpeqd %xmm4, %xmm1
; SSE2-NEXT: pcmpeqd %xmm4, %xmm0
; SSE2-NEXT: packssdw %xmm1, %xmm0
; SSE2-NEXT: packsswb %xmm0, %xmm0
; SSE2-NEXT: pmovmskb %xmm0, %eax
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; SSE2-NEXT: testb $1, %al
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE2-NEXT: jne LBB12_1
; SSE2-NEXT: ## %bb.2: ## %else
; SSE2-NEXT: testb $2, %al
; SSE2-NEXT: jne LBB12_3
; SSE2-NEXT: LBB12_4: ## %else2
; SSE2-NEXT: testb $4, %al
; SSE2-NEXT: jne LBB12_5
; SSE2-NEXT: LBB12_6: ## %else4
; SSE2-NEXT: testb $8, %al
; SSE2-NEXT: jne LBB12_7
; SSE2-NEXT: LBB12_8: ## %else6
; SSE2-NEXT: testb $16, %al
; SSE2-NEXT: jne LBB12_9
; SSE2-NEXT: LBB12_10: ## %else8
; SSE2-NEXT: testb $32, %al
; SSE2-NEXT: jne LBB12_11
; SSE2-NEXT: LBB12_12: ## %else10
; SSE2-NEXT: testb $64, %al
; SSE2-NEXT: jne LBB12_13
; SSE2-NEXT: LBB12_14: ## %else12
; SSE2-NEXT: testb $-128, %al
; SSE2-NEXT: jne LBB12_15
; SSE2-NEXT: LBB12_16: ## %else14
; SSE2-NEXT: retq
; SSE2-NEXT: LBB12_1: ## %cond.store
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; SSE2-NEXT: movd %xmm2, (%rdi)
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE2-NEXT: testb $2, %al
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; SSE2-NEXT: je LBB12_4
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE2-NEXT: LBB12_3: ## %cond.store1
; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm2[1,1,2,3]
; SSE2-NEXT: movd %xmm0, 4(%rdi)
; SSE2-NEXT: testb $4, %al
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; SSE2-NEXT: je LBB12_6
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE2-NEXT: LBB12_5: ## %cond.store3
; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm2[2,3,0,1]
; SSE2-NEXT: movd %xmm0, 8(%rdi)
; SSE2-NEXT: testb $8, %al
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; SSE2-NEXT: je LBB12_8
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE2-NEXT: LBB12_7: ## %cond.store5
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm2[3,1,2,3]
; SSE2-NEXT: movd %xmm0, 12(%rdi)
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE2-NEXT: testb $16, %al
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; SSE2-NEXT: je LBB12_10
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE2-NEXT: LBB12_9: ## %cond.store7
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; SSE2-NEXT: movd %xmm3, 16(%rdi)
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE2-NEXT: testb $32, %al
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; SSE2-NEXT: je LBB12_12
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE2-NEXT: LBB12_11: ## %cond.store9
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm3[1,1,2,3]
; SSE2-NEXT: movd %xmm0, 20(%rdi)
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE2-NEXT: testb $64, %al
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; SSE2-NEXT: je LBB12_14
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE2-NEXT: LBB12_13: ## %cond.store11
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm3[2,3,0,1]
; SSE2-NEXT: movd %xmm0, 24(%rdi)
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE2-NEXT: testb $-128, %al
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; SSE2-NEXT: je LBB12_16
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE2-NEXT: LBB12_15: ## %cond.store13
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm3[3,1,2,3]
; SSE2-NEXT: movd %xmm0, 28(%rdi)
; SSE2-NEXT: retq
;
; SSE4-LABEL: store_v8i32_v8i32:
; SSE4: ## %bb.0:
; SSE4-NEXT: pxor %xmm4, %xmm4
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE4-NEXT: pcmpeqd %xmm4, %xmm1
; SSE4-NEXT: pcmpeqd %xmm4, %xmm0
; SSE4-NEXT: packssdw %xmm1, %xmm0
; SSE4-NEXT: packsswb %xmm0, %xmm0
; SSE4-NEXT: pmovmskb %xmm0, %eax
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; SSE4-NEXT: testb $1, %al
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE4-NEXT: jne LBB12_1
; SSE4-NEXT: ## %bb.2: ## %else
; SSE4-NEXT: testb $2, %al
; SSE4-NEXT: jne LBB12_3
; SSE4-NEXT: LBB12_4: ## %else2
; SSE4-NEXT: testb $4, %al
; SSE4-NEXT: jne LBB12_5
; SSE4-NEXT: LBB12_6: ## %else4
; SSE4-NEXT: testb $8, %al
; SSE4-NEXT: jne LBB12_7
; SSE4-NEXT: LBB12_8: ## %else6
; SSE4-NEXT: testb $16, %al
; SSE4-NEXT: jne LBB12_9
; SSE4-NEXT: LBB12_10: ## %else8
; SSE4-NEXT: testb $32, %al
; SSE4-NEXT: jne LBB12_11
; SSE4-NEXT: LBB12_12: ## %else10
; SSE4-NEXT: testb $64, %al
; SSE4-NEXT: jne LBB12_13
; SSE4-NEXT: LBB12_14: ## %else12
; SSE4-NEXT: testb $-128, %al
; SSE4-NEXT: jne LBB12_15
; SSE4-NEXT: LBB12_16: ## %else14
; SSE4-NEXT: retq
; SSE4-NEXT: LBB12_1: ## %cond.store
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; SSE4-NEXT: movss %xmm2, (%rdi)
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE4-NEXT: testb $2, %al
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; SSE4-NEXT: je LBB12_4
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE4-NEXT: LBB12_3: ## %cond.store1
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; SSE4-NEXT: extractps $1, %xmm2, 4(%rdi)
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE4-NEXT: testb $4, %al
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; SSE4-NEXT: je LBB12_6
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE4-NEXT: LBB12_5: ## %cond.store3
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; SSE4-NEXT: extractps $2, %xmm2, 8(%rdi)
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE4-NEXT: testb $8, %al
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; SSE4-NEXT: je LBB12_8
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE4-NEXT: LBB12_7: ## %cond.store5
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; SSE4-NEXT: extractps $3, %xmm2, 12(%rdi)
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE4-NEXT: testb $16, %al
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; SSE4-NEXT: je LBB12_10
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE4-NEXT: LBB12_9: ## %cond.store7
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; SSE4-NEXT: movss %xmm3, 16(%rdi)
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE4-NEXT: testb $32, %al
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; SSE4-NEXT: je LBB12_12
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE4-NEXT: LBB12_11: ## %cond.store9
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; SSE4-NEXT: extractps $1, %xmm3, 20(%rdi)
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE4-NEXT: testb $64, %al
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; SSE4-NEXT: je LBB12_14
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE4-NEXT: LBB12_13: ## %cond.store11
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; SSE4-NEXT: extractps $2, %xmm3, 24(%rdi)
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE4-NEXT: testb $-128, %al
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; SSE4-NEXT: je LBB12_16
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE4-NEXT: LBB12_15: ## %cond.store13
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; SSE4-NEXT: extractps $3, %xmm3, 28(%rdi)
; SSE4-NEXT: retq
;
; AVX1-LABEL: store_v8i32_v8i32:
; AVX1: ## %bb.0:
; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm2
; AVX1-NEXT: vpxor %xmm3, %xmm3, %xmm3
; AVX1-NEXT: vpcmpeqd %xmm3, %xmm2, %xmm2
; AVX1-NEXT: vpcmpeqd %xmm3, %xmm0, %xmm0
; AVX1-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm0
; AVX1-NEXT: vmaskmovps %ymm1, %ymm0, (%rdi)
; AVX1-NEXT: vzeroupper
; AVX1-NEXT: retq
;
; AVX2-LABEL: store_v8i32_v8i32:
; AVX2: ## %bb.0:
; AVX2-NEXT: vpxor %xmm2, %xmm2, %xmm2
; AVX2-NEXT: vpcmpeqd %ymm2, %ymm0, %ymm0
; AVX2-NEXT: vpmaskmovd %ymm1, %ymm0, (%rdi)
; AVX2-NEXT: vzeroupper
; AVX2-NEXT: retq
;
; AVX512F-LABEL: store_v8i32_v8i32:
; AVX512F: ## %bb.0:
; AVX512F-NEXT: ## kill: def $ymm1 killed $ymm1 def $zmm1
; AVX512F-NEXT: ## kill: def $ymm0 killed $ymm0 def $zmm0
; AVX512F-NEXT: vptestnmd %zmm0, %zmm0, %k0
; AVX512F-NEXT: kshiftlw $8, %k0, %k0
; AVX512F-NEXT: kshiftrw $8, %k0, %k1
; AVX512F-NEXT: vmovdqu32 %zmm1, (%rdi) {%k1}
; AVX512F-NEXT: vzeroupper
; AVX512F-NEXT: retq
;
[X86][AVX] Add AVX512DQ coverage for masked memory ops tests (PR34584) llvm-svn: 359395
2019-04-28 18:02:34 +08:00
; AVX512VL-LABEL: store_v8i32_v8i32:
; AVX512VL: ## %bb.0:
; AVX512VL-NEXT: vptestnmd %ymm0, %ymm0, %k1
; AVX512VL-NEXT: vmovdqu32 %ymm1, (%rdi) {%k1}
; AVX512VL-NEXT: vzeroupper
; AVX512VL-NEXT: retq
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
%mask = icmp eq <8 x i32> %trigger, zeroinitializer
call void @llvm.masked.store.v8i32.p0v8i32(<8 x i32> %val, <8 x i32>* %addr, i32 4, <8 x i1> %mask)
ret void
}
;
; vXi16
;
define void @store_v8i16_v8i16(<8 x i16> %trigger, <8 x i16>* %addr, <8 x i16> %val) {
; SSE2-LABEL: store_v8i16_v8i16:
; SSE2: ## %bb.0:
; SSE2-NEXT: pxor %xmm2, %xmm2
; SSE2-NEXT: pcmpeqw %xmm0, %xmm2
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE2-NEXT: packsswb %xmm0, %xmm2
; SSE2-NEXT: pmovmskb %xmm2, %eax
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; SSE2-NEXT: testb $1, %al
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE2-NEXT: jne LBB13_1
; SSE2-NEXT: ## %bb.2: ## %else
; SSE2-NEXT: testb $2, %al
; SSE2-NEXT: jne LBB13_3
; SSE2-NEXT: LBB13_4: ## %else2
; SSE2-NEXT: testb $4, %al
; SSE2-NEXT: jne LBB13_5
; SSE2-NEXT: LBB13_6: ## %else4
; SSE2-NEXT: testb $8, %al
; SSE2-NEXT: jne LBB13_7
; SSE2-NEXT: LBB13_8: ## %else6
; SSE2-NEXT: testb $16, %al
; SSE2-NEXT: jne LBB13_9
; SSE2-NEXT: LBB13_10: ## %else8
; SSE2-NEXT: testb $32, %al
; SSE2-NEXT: jne LBB13_11
; SSE2-NEXT: LBB13_12: ## %else10
; SSE2-NEXT: testb $64, %al
; SSE2-NEXT: jne LBB13_13
; SSE2-NEXT: LBB13_14: ## %else12
; SSE2-NEXT: testb $-128, %al
; SSE2-NEXT: jne LBB13_15
; SSE2-NEXT: LBB13_16: ## %else14
; SSE2-NEXT: retq
; SSE2-NEXT: LBB13_1: ## %cond.store
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; SSE2-NEXT: movd %xmm1, %ecx
; SSE2-NEXT: movw %cx, (%rdi)
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE2-NEXT: testb $2, %al
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; SSE2-NEXT: je LBB13_4
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE2-NEXT: LBB13_3: ## %cond.store1
; SSE2-NEXT: pextrw $1, %xmm1, %ecx
; SSE2-NEXT: movw %cx, 2(%rdi)
; SSE2-NEXT: testb $4, %al
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; SSE2-NEXT: je LBB13_6
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE2-NEXT: LBB13_5: ## %cond.store3
; SSE2-NEXT: pextrw $2, %xmm1, %ecx
; SSE2-NEXT: movw %cx, 4(%rdi)
; SSE2-NEXT: testb $8, %al
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; SSE2-NEXT: je LBB13_8
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE2-NEXT: LBB13_7: ## %cond.store5
; SSE2-NEXT: pextrw $3, %xmm1, %ecx
; SSE2-NEXT: movw %cx, 6(%rdi)
; SSE2-NEXT: testb $16, %al
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; SSE2-NEXT: je LBB13_10
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE2-NEXT: LBB13_9: ## %cond.store7
; SSE2-NEXT: pextrw $4, %xmm1, %ecx
; SSE2-NEXT: movw %cx, 8(%rdi)
; SSE2-NEXT: testb $32, %al
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; SSE2-NEXT: je LBB13_12
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE2-NEXT: LBB13_11: ## %cond.store9
; SSE2-NEXT: pextrw $5, %xmm1, %ecx
; SSE2-NEXT: movw %cx, 10(%rdi)
; SSE2-NEXT: testb $64, %al
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; SSE2-NEXT: je LBB13_14
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE2-NEXT: LBB13_13: ## %cond.store11
; SSE2-NEXT: pextrw $6, %xmm1, %ecx
; SSE2-NEXT: movw %cx, 12(%rdi)
; SSE2-NEXT: testb $-128, %al
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; SSE2-NEXT: je LBB13_16
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE2-NEXT: LBB13_15: ## %cond.store13
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; SSE2-NEXT: pextrw $7, %xmm1, %eax
; SSE2-NEXT: movw %ax, 14(%rdi)
; SSE2-NEXT: retq
;
; SSE4-LABEL: store_v8i16_v8i16:
; SSE4: ## %bb.0:
; SSE4-NEXT: pxor %xmm2, %xmm2
; SSE4-NEXT: pcmpeqw %xmm0, %xmm2
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE4-NEXT: packsswb %xmm0, %xmm2
; SSE4-NEXT: pmovmskb %xmm2, %eax
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; SSE4-NEXT: testb $1, %al
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE4-NEXT: jne LBB13_1
; SSE4-NEXT: ## %bb.2: ## %else
; SSE4-NEXT: testb $2, %al
; SSE4-NEXT: jne LBB13_3
; SSE4-NEXT: LBB13_4: ## %else2
; SSE4-NEXT: testb $4, %al
; SSE4-NEXT: jne LBB13_5
; SSE4-NEXT: LBB13_6: ## %else4
; SSE4-NEXT: testb $8, %al
; SSE4-NEXT: jne LBB13_7
; SSE4-NEXT: LBB13_8: ## %else6
; SSE4-NEXT: testb $16, %al
; SSE4-NEXT: jne LBB13_9
; SSE4-NEXT: LBB13_10: ## %else8
; SSE4-NEXT: testb $32, %al
; SSE4-NEXT: jne LBB13_11
; SSE4-NEXT: LBB13_12: ## %else10
; SSE4-NEXT: testb $64, %al
; SSE4-NEXT: jne LBB13_13
; SSE4-NEXT: LBB13_14: ## %else12
; SSE4-NEXT: testb $-128, %al
; SSE4-NEXT: jne LBB13_15
; SSE4-NEXT: LBB13_16: ## %else14
; SSE4-NEXT: retq
; SSE4-NEXT: LBB13_1: ## %cond.store
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; SSE4-NEXT: pextrw $0, %xmm1, (%rdi)
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE4-NEXT: testb $2, %al
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; SSE4-NEXT: je LBB13_4
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE4-NEXT: LBB13_3: ## %cond.store1
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; SSE4-NEXT: pextrw $1, %xmm1, 2(%rdi)
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE4-NEXT: testb $4, %al
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; SSE4-NEXT: je LBB13_6
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE4-NEXT: LBB13_5: ## %cond.store3
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; SSE4-NEXT: pextrw $2, %xmm1, 4(%rdi)
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE4-NEXT: testb $8, %al
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; SSE4-NEXT: je LBB13_8
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE4-NEXT: LBB13_7: ## %cond.store5
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; SSE4-NEXT: pextrw $3, %xmm1, 6(%rdi)
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE4-NEXT: testb $16, %al
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; SSE4-NEXT: je LBB13_10
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE4-NEXT: LBB13_9: ## %cond.store7
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; SSE4-NEXT: pextrw $4, %xmm1, 8(%rdi)
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE4-NEXT: testb $32, %al
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; SSE4-NEXT: je LBB13_12
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE4-NEXT: LBB13_11: ## %cond.store9
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; SSE4-NEXT: pextrw $5, %xmm1, 10(%rdi)
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE4-NEXT: testb $64, %al
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; SSE4-NEXT: je LBB13_14
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE4-NEXT: LBB13_13: ## %cond.store11
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; SSE4-NEXT: pextrw $6, %xmm1, 12(%rdi)
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE4-NEXT: testb $-128, %al
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; SSE4-NEXT: je LBB13_16
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE4-NEXT: LBB13_15: ## %cond.store13
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; SSE4-NEXT: pextrw $7, %xmm1, 14(%rdi)
; SSE4-NEXT: retq
;
; AVX1OR2-LABEL: store_v8i16_v8i16:
; AVX1OR2: ## %bb.0:
; AVX1OR2-NEXT: vpxor %xmm2, %xmm2, %xmm2
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX1OR2-NEXT: vpcmpeqw %xmm2, %xmm0, %xmm0
; AVX1OR2-NEXT: vpacksswb %xmm0, %xmm0, %xmm0
; AVX1OR2-NEXT: vpmovmskb %xmm0, %eax
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; AVX1OR2-NEXT: testb $1, %al
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX1OR2-NEXT: jne LBB13_1
; AVX1OR2-NEXT: ## %bb.2: ## %else
; AVX1OR2-NEXT: testb $2, %al
; AVX1OR2-NEXT: jne LBB13_3
; AVX1OR2-NEXT: LBB13_4: ## %else2
; AVX1OR2-NEXT: testb $4, %al
; AVX1OR2-NEXT: jne LBB13_5
; AVX1OR2-NEXT: LBB13_6: ## %else4
; AVX1OR2-NEXT: testb $8, %al
; AVX1OR2-NEXT: jne LBB13_7
; AVX1OR2-NEXT: LBB13_8: ## %else6
; AVX1OR2-NEXT: testb $16, %al
; AVX1OR2-NEXT: jne LBB13_9
; AVX1OR2-NEXT: LBB13_10: ## %else8
; AVX1OR2-NEXT: testb $32, %al
; AVX1OR2-NEXT: jne LBB13_11
; AVX1OR2-NEXT: LBB13_12: ## %else10
; AVX1OR2-NEXT: testb $64, %al
; AVX1OR2-NEXT: jne LBB13_13
; AVX1OR2-NEXT: LBB13_14: ## %else12
; AVX1OR2-NEXT: testb $-128, %al
; AVX1OR2-NEXT: jne LBB13_15
; AVX1OR2-NEXT: LBB13_16: ## %else14
; AVX1OR2-NEXT: retq
; AVX1OR2-NEXT: LBB13_1: ## %cond.store
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; AVX1OR2-NEXT: vpextrw $0, %xmm1, (%rdi)
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX1OR2-NEXT: testb $2, %al
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; AVX1OR2-NEXT: je LBB13_4
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX1OR2-NEXT: LBB13_3: ## %cond.store1
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; AVX1OR2-NEXT: vpextrw $1, %xmm1, 2(%rdi)
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX1OR2-NEXT: testb $4, %al
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; AVX1OR2-NEXT: je LBB13_6
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX1OR2-NEXT: LBB13_5: ## %cond.store3
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; AVX1OR2-NEXT: vpextrw $2, %xmm1, 4(%rdi)
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX1OR2-NEXT: testb $8, %al
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; AVX1OR2-NEXT: je LBB13_8
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX1OR2-NEXT: LBB13_7: ## %cond.store5
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; AVX1OR2-NEXT: vpextrw $3, %xmm1, 6(%rdi)
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX1OR2-NEXT: testb $16, %al
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; AVX1OR2-NEXT: je LBB13_10
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX1OR2-NEXT: LBB13_9: ## %cond.store7
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; AVX1OR2-NEXT: vpextrw $4, %xmm1, 8(%rdi)
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX1OR2-NEXT: testb $32, %al
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; AVX1OR2-NEXT: je LBB13_12
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX1OR2-NEXT: LBB13_11: ## %cond.store9
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; AVX1OR2-NEXT: vpextrw $5, %xmm1, 10(%rdi)
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX1OR2-NEXT: testb $64, %al
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; AVX1OR2-NEXT: je LBB13_14
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX1OR2-NEXT: LBB13_13: ## %cond.store11
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; AVX1OR2-NEXT: vpextrw $6, %xmm1, 12(%rdi)
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX1OR2-NEXT: testb $-128, %al
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; AVX1OR2-NEXT: je LBB13_16
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX1OR2-NEXT: LBB13_15: ## %cond.store13
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; AVX1OR2-NEXT: vpextrw $7, %xmm1, 14(%rdi)
; AVX1OR2-NEXT: retq
;
; AVX512F-LABEL: store_v8i16_v8i16:
; AVX512F: ## %bb.0:
; AVX512F-NEXT: vpxor %xmm2, %xmm2, %xmm2
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX512F-NEXT: vpcmpeqw %xmm2, %xmm0, %xmm0
; AVX512F-NEXT: vpmovsxwq %xmm0, %zmm0
; AVX512F-NEXT: vptestmq %zmm0, %zmm0, %k0
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; AVX512F-NEXT: kmovw %k0, %eax
; AVX512F-NEXT: testb $1, %al
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX512F-NEXT: jne LBB13_1
; AVX512F-NEXT: ## %bb.2: ## %else
; AVX512F-NEXT: testb $2, %al
; AVX512F-NEXT: jne LBB13_3
; AVX512F-NEXT: LBB13_4: ## %else2
; AVX512F-NEXT: testb $4, %al
; AVX512F-NEXT: jne LBB13_5
; AVX512F-NEXT: LBB13_6: ## %else4
; AVX512F-NEXT: testb $8, %al
; AVX512F-NEXT: jne LBB13_7
; AVX512F-NEXT: LBB13_8: ## %else6
; AVX512F-NEXT: testb $16, %al
; AVX512F-NEXT: jne LBB13_9
; AVX512F-NEXT: LBB13_10: ## %else8
; AVX512F-NEXT: testb $32, %al
; AVX512F-NEXT: jne LBB13_11
; AVX512F-NEXT: LBB13_12: ## %else10
; AVX512F-NEXT: testb $64, %al
; AVX512F-NEXT: jne LBB13_13
; AVX512F-NEXT: LBB13_14: ## %else12
; AVX512F-NEXT: testb $-128, %al
; AVX512F-NEXT: jne LBB13_15
; AVX512F-NEXT: LBB13_16: ## %else14
; AVX512F-NEXT: vzeroupper
; AVX512F-NEXT: retq
; AVX512F-NEXT: LBB13_1: ## %cond.store
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; AVX512F-NEXT: vpextrw $0, %xmm1, (%rdi)
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX512F-NEXT: testb $2, %al
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; AVX512F-NEXT: je LBB13_4
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX512F-NEXT: LBB13_3: ## %cond.store1
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; AVX512F-NEXT: vpextrw $1, %xmm1, 2(%rdi)
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX512F-NEXT: testb $4, %al
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; AVX512F-NEXT: je LBB13_6
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX512F-NEXT: LBB13_5: ## %cond.store3
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; AVX512F-NEXT: vpextrw $2, %xmm1, 4(%rdi)
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX512F-NEXT: testb $8, %al
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; AVX512F-NEXT: je LBB13_8
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX512F-NEXT: LBB13_7: ## %cond.store5
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; AVX512F-NEXT: vpextrw $3, %xmm1, 6(%rdi)
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX512F-NEXT: testb $16, %al
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; AVX512F-NEXT: je LBB13_10
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX512F-NEXT: LBB13_9: ## %cond.store7
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; AVX512F-NEXT: vpextrw $4, %xmm1, 8(%rdi)
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX512F-NEXT: testb $32, %al
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; AVX512F-NEXT: je LBB13_12
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX512F-NEXT: LBB13_11: ## %cond.store9
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; AVX512F-NEXT: vpextrw $5, %xmm1, 10(%rdi)
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX512F-NEXT: testb $64, %al
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; AVX512F-NEXT: je LBB13_14
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX512F-NEXT: LBB13_13: ## %cond.store11
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; AVX512F-NEXT: vpextrw $6, %xmm1, 12(%rdi)
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX512F-NEXT: testb $-128, %al
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; AVX512F-NEXT: je LBB13_16
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX512F-NEXT: LBB13_15: ## %cond.store13
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; AVX512F-NEXT: vpextrw $7, %xmm1, 14(%rdi)
; AVX512F-NEXT: vzeroupper
; AVX512F-NEXT: retq
;
[X86][AVX] Add AVX512DQ coverage for masked memory ops tests (PR34584) llvm-svn: 359395
2019-04-28 18:02:34 +08:00
; AVX512VLDQ-LABEL: store_v8i16_v8i16:
; AVX512VLDQ: ## %bb.0:
; AVX512VLDQ-NEXT: vpxor %xmm2, %xmm2, %xmm2
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX512VLDQ-NEXT: vpcmpeqw %xmm2, %xmm0, %xmm0
; AVX512VLDQ-NEXT: vpmovsxwd %xmm0, %ymm0
; AVX512VLDQ-NEXT: vpmovd2m %ymm0, %k0
[X86][AVX] Add AVX512DQ coverage for masked memory ops tests (PR34584) llvm-svn: 359395
2019-04-28 18:02:34 +08:00
; AVX512VLDQ-NEXT: kmovw %k0, %eax
; AVX512VLDQ-NEXT: testb $1, %al
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX512VLDQ-NEXT: jne LBB13_1
; AVX512VLDQ-NEXT: ## %bb.2: ## %else
; AVX512VLDQ-NEXT: testb $2, %al
; AVX512VLDQ-NEXT: jne LBB13_3
; AVX512VLDQ-NEXT: LBB13_4: ## %else2
; AVX512VLDQ-NEXT: testb $4, %al
; AVX512VLDQ-NEXT: jne LBB13_5
; AVX512VLDQ-NEXT: LBB13_6: ## %else4
; AVX512VLDQ-NEXT: testb $8, %al
; AVX512VLDQ-NEXT: jne LBB13_7
; AVX512VLDQ-NEXT: LBB13_8: ## %else6
; AVX512VLDQ-NEXT: testb $16, %al
; AVX512VLDQ-NEXT: jne LBB13_9
; AVX512VLDQ-NEXT: LBB13_10: ## %else8
; AVX512VLDQ-NEXT: testb $32, %al
; AVX512VLDQ-NEXT: jne LBB13_11
; AVX512VLDQ-NEXT: LBB13_12: ## %else10
; AVX512VLDQ-NEXT: testb $64, %al
; AVX512VLDQ-NEXT: jne LBB13_13
; AVX512VLDQ-NEXT: LBB13_14: ## %else12
; AVX512VLDQ-NEXT: testb $-128, %al
; AVX512VLDQ-NEXT: jne LBB13_15
; AVX512VLDQ-NEXT: LBB13_16: ## %else14
; AVX512VLDQ-NEXT: vzeroupper
; AVX512VLDQ-NEXT: retq
; AVX512VLDQ-NEXT: LBB13_1: ## %cond.store
; AVX512VLDQ-NEXT: vpextrw $0, %xmm1, (%rdi)
; AVX512VLDQ-NEXT: testb $2, %al
[X86][AVX] Add AVX512DQ coverage for masked memory ops tests (PR34584) llvm-svn: 359395
2019-04-28 18:02:34 +08:00
; AVX512VLDQ-NEXT: je LBB13_4
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX512VLDQ-NEXT: LBB13_3: ## %cond.store1
[X86][AVX] Add AVX512DQ coverage for masked memory ops tests (PR34584) llvm-svn: 359395
2019-04-28 18:02:34 +08:00
; AVX512VLDQ-NEXT: vpextrw $1, %xmm1, 2(%rdi)
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX512VLDQ-NEXT: testb $4, %al
[X86][AVX] Add AVX512DQ coverage for masked memory ops tests (PR34584) llvm-svn: 359395
2019-04-28 18:02:34 +08:00
; AVX512VLDQ-NEXT: je LBB13_6
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX512VLDQ-NEXT: LBB13_5: ## %cond.store3
[X86][AVX] Add AVX512DQ coverage for masked memory ops tests (PR34584) llvm-svn: 359395
2019-04-28 18:02:34 +08:00
; AVX512VLDQ-NEXT: vpextrw $2, %xmm1, 4(%rdi)
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX512VLDQ-NEXT: testb $8, %al
[X86][AVX] Add AVX512DQ coverage for masked memory ops tests (PR34584) llvm-svn: 359395
2019-04-28 18:02:34 +08:00
; AVX512VLDQ-NEXT: je LBB13_8
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX512VLDQ-NEXT: LBB13_7: ## %cond.store5
[X86][AVX] Add AVX512DQ coverage for masked memory ops tests (PR34584) llvm-svn: 359395
2019-04-28 18:02:34 +08:00
; AVX512VLDQ-NEXT: vpextrw $3, %xmm1, 6(%rdi)
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX512VLDQ-NEXT: testb $16, %al
[X86][AVX] Add AVX512DQ coverage for masked memory ops tests (PR34584) llvm-svn: 359395
2019-04-28 18:02:34 +08:00
; AVX512VLDQ-NEXT: je LBB13_10
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX512VLDQ-NEXT: LBB13_9: ## %cond.store7
[X86][AVX] Add AVX512DQ coverage for masked memory ops tests (PR34584) llvm-svn: 359395
2019-04-28 18:02:34 +08:00
; AVX512VLDQ-NEXT: vpextrw $4, %xmm1, 8(%rdi)
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX512VLDQ-NEXT: testb $32, %al
[X86][AVX] Add AVX512DQ coverage for masked memory ops tests (PR34584) llvm-svn: 359395
2019-04-28 18:02:34 +08:00
; AVX512VLDQ-NEXT: je LBB13_12
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX512VLDQ-NEXT: LBB13_11: ## %cond.store9
[X86][AVX] Add AVX512DQ coverage for masked memory ops tests (PR34584) llvm-svn: 359395
2019-04-28 18:02:34 +08:00
; AVX512VLDQ-NEXT: vpextrw $5, %xmm1, 10(%rdi)
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX512VLDQ-NEXT: testb $64, %al
[X86][AVX] Add AVX512DQ coverage for masked memory ops tests (PR34584) llvm-svn: 359395
2019-04-28 18:02:34 +08:00
; AVX512VLDQ-NEXT: je LBB13_14
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX512VLDQ-NEXT: LBB13_13: ## %cond.store11
[X86][AVX] Add AVX512DQ coverage for masked memory ops tests (PR34584) llvm-svn: 359395
2019-04-28 18:02:34 +08:00
; AVX512VLDQ-NEXT: vpextrw $6, %xmm1, 12(%rdi)
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX512VLDQ-NEXT: testb $-128, %al
[X86][AVX] Add AVX512DQ coverage for masked memory ops tests (PR34584) llvm-svn: 359395
2019-04-28 18:02:34 +08:00
; AVX512VLDQ-NEXT: je LBB13_16
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX512VLDQ-NEXT: LBB13_15: ## %cond.store13
[X86][AVX] Add AVX512DQ coverage for masked memory ops tests (PR34584) llvm-svn: 359395
2019-04-28 18:02:34 +08:00
; AVX512VLDQ-NEXT: vpextrw $7, %xmm1, 14(%rdi)
; AVX512VLDQ-NEXT: vzeroupper
; AVX512VLDQ-NEXT: retq
;
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; AVX512VLBW-LABEL: store_v8i16_v8i16:
; AVX512VLBW: ## %bb.0:
; AVX512VLBW-NEXT: vptestnmw %xmm0, %xmm0, %k1
; AVX512VLBW-NEXT: vmovdqu16 %xmm1, (%rdi) {%k1}
; AVX512VLBW-NEXT: retq
%mask = icmp eq <8 x i16> %trigger, zeroinitializer
call void @llvm.masked.store.v8i16.p0v8i16(<8 x i16> %val, <8 x i16>* %addr, i32 4, <8 x i1> %mask)
ret void
}
define void @store_v16i16_v16i16(<16 x i16> %trigger, <16 x i16>* %addr, <16 x i16> %val) {
; SSE2-LABEL: store_v16i16_v16i16:
; SSE2: ## %bb.0:
; SSE2-NEXT: pxor %xmm4, %xmm4
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE2-NEXT: pcmpeqw %xmm4, %xmm1
; SSE2-NEXT: pcmpeqw %xmm4, %xmm0
; SSE2-NEXT: packsswb %xmm1, %xmm0
; SSE2-NEXT: pmovmskb %xmm0, %eax
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; SSE2-NEXT: testb $1, %al
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE2-NEXT: jne LBB14_1
; SSE2-NEXT: ## %bb.2: ## %else
; SSE2-NEXT: testb $2, %al
; SSE2-NEXT: jne LBB14_3
; SSE2-NEXT: LBB14_4: ## %else2
; SSE2-NEXT: testb $4, %al
; SSE2-NEXT: jne LBB14_5
; SSE2-NEXT: LBB14_6: ## %else4
; SSE2-NEXT: testb $8, %al
; SSE2-NEXT: jne LBB14_7
; SSE2-NEXT: LBB14_8: ## %else6
; SSE2-NEXT: testb $16, %al
; SSE2-NEXT: jne LBB14_9
; SSE2-NEXT: LBB14_10: ## %else8
; SSE2-NEXT: testb $32, %al
; SSE2-NEXT: jne LBB14_11
; SSE2-NEXT: LBB14_12: ## %else10
; SSE2-NEXT: testb $64, %al
; SSE2-NEXT: jne LBB14_13
; SSE2-NEXT: LBB14_14: ## %else12
; SSE2-NEXT: testb $-128, %al
; SSE2-NEXT: jne LBB14_15
; SSE2-NEXT: LBB14_16: ## %else14
; SSE2-NEXT: testl $256, %eax ## imm = 0x100
; SSE2-NEXT: jne LBB14_17
; SSE2-NEXT: LBB14_18: ## %else16
; SSE2-NEXT: testl $512, %eax ## imm = 0x200
; SSE2-NEXT: jne LBB14_19
; SSE2-NEXT: LBB14_20: ## %else18
; SSE2-NEXT: testl $1024, %eax ## imm = 0x400
; SSE2-NEXT: jne LBB14_21
; SSE2-NEXT: LBB14_22: ## %else20
; SSE2-NEXT: testl $2048, %eax ## imm = 0x800
; SSE2-NEXT: jne LBB14_23
; SSE2-NEXT: LBB14_24: ## %else22
; SSE2-NEXT: testl $4096, %eax ## imm = 0x1000
; SSE2-NEXT: jne LBB14_25
; SSE2-NEXT: LBB14_26: ## %else24
; SSE2-NEXT: testl $8192, %eax ## imm = 0x2000
; SSE2-NEXT: jne LBB14_27
; SSE2-NEXT: LBB14_28: ## %else26
; SSE2-NEXT: testl $16384, %eax ## imm = 0x4000
; SSE2-NEXT: jne LBB14_29
; SSE2-NEXT: LBB14_30: ## %else28
; SSE2-NEXT: testl $32768, %eax ## imm = 0x8000
; SSE2-NEXT: jne LBB14_31
; SSE2-NEXT: LBB14_32: ## %else30
; SSE2-NEXT: retq
; SSE2-NEXT: LBB14_1: ## %cond.store
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; SSE2-NEXT: movd %xmm2, %ecx
; SSE2-NEXT: movw %cx, (%rdi)
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE2-NEXT: testb $2, %al
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; SSE2-NEXT: je LBB14_4
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE2-NEXT: LBB14_3: ## %cond.store1
; SSE2-NEXT: pextrw $1, %xmm2, %ecx
; SSE2-NEXT: movw %cx, 2(%rdi)
; SSE2-NEXT: testb $4, %al
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; SSE2-NEXT: je LBB14_6
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE2-NEXT: LBB14_5: ## %cond.store3
; SSE2-NEXT: pextrw $2, %xmm2, %ecx
; SSE2-NEXT: movw %cx, 4(%rdi)
; SSE2-NEXT: testb $8, %al
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; SSE2-NEXT: je LBB14_8
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE2-NEXT: LBB14_7: ## %cond.store5
; SSE2-NEXT: pextrw $3, %xmm2, %ecx
; SSE2-NEXT: movw %cx, 6(%rdi)
; SSE2-NEXT: testb $16, %al
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; SSE2-NEXT: je LBB14_10
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE2-NEXT: LBB14_9: ## %cond.store7
; SSE2-NEXT: pextrw $4, %xmm2, %ecx
; SSE2-NEXT: movw %cx, 8(%rdi)
; SSE2-NEXT: testb $32, %al
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; SSE2-NEXT: je LBB14_12
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE2-NEXT: LBB14_11: ## %cond.store9
; SSE2-NEXT: pextrw $5, %xmm2, %ecx
; SSE2-NEXT: movw %cx, 10(%rdi)
; SSE2-NEXT: testb $64, %al
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; SSE2-NEXT: je LBB14_14
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE2-NEXT: LBB14_13: ## %cond.store11
; SSE2-NEXT: pextrw $6, %xmm2, %ecx
; SSE2-NEXT: movw %cx, 12(%rdi)
; SSE2-NEXT: testb $-128, %al
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; SSE2-NEXT: je LBB14_16
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE2-NEXT: LBB14_15: ## %cond.store13
; SSE2-NEXT: pextrw $7, %xmm2, %ecx
; SSE2-NEXT: movw %cx, 14(%rdi)
; SSE2-NEXT: testl $256, %eax ## imm = 0x100
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; SSE2-NEXT: je LBB14_18
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE2-NEXT: LBB14_17: ## %cond.store15
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; SSE2-NEXT: movd %xmm3, %ecx
; SSE2-NEXT: movw %cx, 16(%rdi)
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE2-NEXT: testl $512, %eax ## imm = 0x200
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; SSE2-NEXT: je LBB14_20
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE2-NEXT: LBB14_19: ## %cond.store17
; SSE2-NEXT: pextrw $1, %xmm3, %ecx
; SSE2-NEXT: movw %cx, 18(%rdi)
; SSE2-NEXT: testl $1024, %eax ## imm = 0x400
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; SSE2-NEXT: je LBB14_22
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE2-NEXT: LBB14_21: ## %cond.store19
; SSE2-NEXT: pextrw $2, %xmm3, %ecx
; SSE2-NEXT: movw %cx, 20(%rdi)
; SSE2-NEXT: testl $2048, %eax ## imm = 0x800
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; SSE2-NEXT: je LBB14_24
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE2-NEXT: LBB14_23: ## %cond.store21
; SSE2-NEXT: pextrw $3, %xmm3, %ecx
; SSE2-NEXT: movw %cx, 22(%rdi)
; SSE2-NEXT: testl $4096, %eax ## imm = 0x1000
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; SSE2-NEXT: je LBB14_26
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE2-NEXT: LBB14_25: ## %cond.store23
; SSE2-NEXT: pextrw $4, %xmm3, %ecx
; SSE2-NEXT: movw %cx, 24(%rdi)
; SSE2-NEXT: testl $8192, %eax ## imm = 0x2000
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; SSE2-NEXT: je LBB14_28
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE2-NEXT: LBB14_27: ## %cond.store25
; SSE2-NEXT: pextrw $5, %xmm3, %ecx
; SSE2-NEXT: movw %cx, 26(%rdi)
; SSE2-NEXT: testl $16384, %eax ## imm = 0x4000
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; SSE2-NEXT: je LBB14_30
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE2-NEXT: LBB14_29: ## %cond.store27
; SSE2-NEXT: pextrw $6, %xmm3, %ecx
; SSE2-NEXT: movw %cx, 28(%rdi)
; SSE2-NEXT: testl $32768, %eax ## imm = 0x8000
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; SSE2-NEXT: je LBB14_32
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE2-NEXT: LBB14_31: ## %cond.store29
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; SSE2-NEXT: pextrw $7, %xmm3, %eax
; SSE2-NEXT: movw %ax, 30(%rdi)
; SSE2-NEXT: retq
;
; SSE4-LABEL: store_v16i16_v16i16:
; SSE4: ## %bb.0:
; SSE4-NEXT: pxor %xmm4, %xmm4
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE4-NEXT: pcmpeqw %xmm4, %xmm1
; SSE4-NEXT: pcmpeqw %xmm4, %xmm0
; SSE4-NEXT: packsswb %xmm1, %xmm0
; SSE4-NEXT: pmovmskb %xmm0, %eax
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; SSE4-NEXT: testb $1, %al
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE4-NEXT: jne LBB14_1
; SSE4-NEXT: ## %bb.2: ## %else
; SSE4-NEXT: testb $2, %al
; SSE4-NEXT: jne LBB14_3
; SSE4-NEXT: LBB14_4: ## %else2
; SSE4-NEXT: testb $4, %al
; SSE4-NEXT: jne LBB14_5
; SSE4-NEXT: LBB14_6: ## %else4
; SSE4-NEXT: testb $8, %al
; SSE4-NEXT: jne LBB14_7
; SSE4-NEXT: LBB14_8: ## %else6
; SSE4-NEXT: testb $16, %al
; SSE4-NEXT: jne LBB14_9
; SSE4-NEXT: LBB14_10: ## %else8
; SSE4-NEXT: testb $32, %al
; SSE4-NEXT: jne LBB14_11
; SSE4-NEXT: LBB14_12: ## %else10
; SSE4-NEXT: testb $64, %al
; SSE4-NEXT: jne LBB14_13
; SSE4-NEXT: LBB14_14: ## %else12
; SSE4-NEXT: testb $-128, %al
; SSE4-NEXT: jne LBB14_15
; SSE4-NEXT: LBB14_16: ## %else14
; SSE4-NEXT: testl $256, %eax ## imm = 0x100
; SSE4-NEXT: jne LBB14_17
; SSE4-NEXT: LBB14_18: ## %else16
; SSE4-NEXT: testl $512, %eax ## imm = 0x200
; SSE4-NEXT: jne LBB14_19
; SSE4-NEXT: LBB14_20: ## %else18
; SSE4-NEXT: testl $1024, %eax ## imm = 0x400
; SSE4-NEXT: jne LBB14_21
; SSE4-NEXT: LBB14_22: ## %else20
; SSE4-NEXT: testl $2048, %eax ## imm = 0x800
; SSE4-NEXT: jne LBB14_23
; SSE4-NEXT: LBB14_24: ## %else22
; SSE4-NEXT: testl $4096, %eax ## imm = 0x1000
; SSE4-NEXT: jne LBB14_25
; SSE4-NEXT: LBB14_26: ## %else24
; SSE4-NEXT: testl $8192, %eax ## imm = 0x2000
; SSE4-NEXT: jne LBB14_27
; SSE4-NEXT: LBB14_28: ## %else26
; SSE4-NEXT: testl $16384, %eax ## imm = 0x4000
; SSE4-NEXT: jne LBB14_29
; SSE4-NEXT: LBB14_30: ## %else28
; SSE4-NEXT: testl $32768, %eax ## imm = 0x8000
; SSE4-NEXT: jne LBB14_31
; SSE4-NEXT: LBB14_32: ## %else30
; SSE4-NEXT: retq
; SSE4-NEXT: LBB14_1: ## %cond.store
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; SSE4-NEXT: pextrw $0, %xmm2, (%rdi)
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE4-NEXT: testb $2, %al
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; SSE4-NEXT: je LBB14_4
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE4-NEXT: LBB14_3: ## %cond.store1
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; SSE4-NEXT: pextrw $1, %xmm2, 2(%rdi)
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE4-NEXT: testb $4, %al
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; SSE4-NEXT: je LBB14_6
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE4-NEXT: LBB14_5: ## %cond.store3
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; SSE4-NEXT: pextrw $2, %xmm2, 4(%rdi)
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE4-NEXT: testb $8, %al
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; SSE4-NEXT: je LBB14_8
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE4-NEXT: LBB14_7: ## %cond.store5
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; SSE4-NEXT: pextrw $3, %xmm2, 6(%rdi)
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE4-NEXT: testb $16, %al
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; SSE4-NEXT: je LBB14_10
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE4-NEXT: LBB14_9: ## %cond.store7
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; SSE4-NEXT: pextrw $4, %xmm2, 8(%rdi)
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE4-NEXT: testb $32, %al
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; SSE4-NEXT: je LBB14_12
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE4-NEXT: LBB14_11: ## %cond.store9
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; SSE4-NEXT: pextrw $5, %xmm2, 10(%rdi)
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE4-NEXT: testb $64, %al
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; SSE4-NEXT: je LBB14_14
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE4-NEXT: LBB14_13: ## %cond.store11
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; SSE4-NEXT: pextrw $6, %xmm2, 12(%rdi)
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE4-NEXT: testb $-128, %al
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; SSE4-NEXT: je LBB14_16
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE4-NEXT: LBB14_15: ## %cond.store13
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; SSE4-NEXT: pextrw $7, %xmm2, 14(%rdi)
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE4-NEXT: testl $256, %eax ## imm = 0x100
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; SSE4-NEXT: je LBB14_18
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE4-NEXT: LBB14_17: ## %cond.store15
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; SSE4-NEXT: pextrw $0, %xmm3, 16(%rdi)
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE4-NEXT: testl $512, %eax ## imm = 0x200
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; SSE4-NEXT: je LBB14_20
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE4-NEXT: LBB14_19: ## %cond.store17
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; SSE4-NEXT: pextrw $1, %xmm3, 18(%rdi)
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE4-NEXT: testl $1024, %eax ## imm = 0x400
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; SSE4-NEXT: je LBB14_22
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE4-NEXT: LBB14_21: ## %cond.store19
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; SSE4-NEXT: pextrw $2, %xmm3, 20(%rdi)
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE4-NEXT: testl $2048, %eax ## imm = 0x800
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; SSE4-NEXT: je LBB14_24
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE4-NEXT: LBB14_23: ## %cond.store21
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; SSE4-NEXT: pextrw $3, %xmm3, 22(%rdi)
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE4-NEXT: testl $4096, %eax ## imm = 0x1000
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; SSE4-NEXT: je LBB14_26
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE4-NEXT: LBB14_25: ## %cond.store23
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; SSE4-NEXT: pextrw $4, %xmm3, 24(%rdi)
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE4-NEXT: testl $8192, %eax ## imm = 0x2000
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; SSE4-NEXT: je LBB14_28
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE4-NEXT: LBB14_27: ## %cond.store25
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; SSE4-NEXT: pextrw $5, %xmm3, 26(%rdi)
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE4-NEXT: testl $16384, %eax ## imm = 0x4000
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; SSE4-NEXT: je LBB14_30
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE4-NEXT: LBB14_29: ## %cond.store27
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; SSE4-NEXT: pextrw $6, %xmm3, 28(%rdi)
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE4-NEXT: testl $32768, %eax ## imm = 0x8000
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; SSE4-NEXT: je LBB14_32
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE4-NEXT: LBB14_31: ## %cond.store29
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; SSE4-NEXT: pextrw $7, %xmm3, 30(%rdi)
; SSE4-NEXT: retq
;
; AVX1-LABEL: store_v16i16_v16i16:
; AVX1: ## %bb.0:
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm2
; AVX1-NEXT: vpxor %xmm3, %xmm3, %xmm3
; AVX1-NEXT: vpcmpeqw %xmm3, %xmm2, %xmm2
; AVX1-NEXT: vpcmpeqw %xmm3, %xmm0, %xmm0
; AVX1-NEXT: vpacksswb %xmm2, %xmm0, %xmm0
; AVX1-NEXT: vpmovmskb %xmm0, %eax
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; AVX1-NEXT: testb $1, %al
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX1-NEXT: jne LBB14_1
; AVX1-NEXT: ## %bb.2: ## %else
; AVX1-NEXT: testb $2, %al
; AVX1-NEXT: jne LBB14_3
; AVX1-NEXT: LBB14_4: ## %else2
; AVX1-NEXT: testb $4, %al
; AVX1-NEXT: jne LBB14_5
; AVX1-NEXT: LBB14_6: ## %else4
; AVX1-NEXT: testb $8, %al
; AVX1-NEXT: jne LBB14_7
; AVX1-NEXT: LBB14_8: ## %else6
; AVX1-NEXT: testb $16, %al
; AVX1-NEXT: jne LBB14_9
; AVX1-NEXT: LBB14_10: ## %else8
; AVX1-NEXT: testb $32, %al
; AVX1-NEXT: jne LBB14_11
; AVX1-NEXT: LBB14_12: ## %else10
; AVX1-NEXT: testb $64, %al
; AVX1-NEXT: jne LBB14_13
; AVX1-NEXT: LBB14_14: ## %else12
; AVX1-NEXT: testb $-128, %al
; AVX1-NEXT: je LBB14_16
; AVX1-NEXT: LBB14_15: ## %cond.store13
; AVX1-NEXT: vpextrw $7, %xmm1, 14(%rdi)
; AVX1-NEXT: LBB14_16: ## %else14
; AVX1-NEXT: testl $256, %eax ## imm = 0x100
; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm0
; AVX1-NEXT: jne LBB14_17
; AVX1-NEXT: ## %bb.18: ## %else16
; AVX1-NEXT: testl $512, %eax ## imm = 0x200
; AVX1-NEXT: jne LBB14_19
; AVX1-NEXT: LBB14_20: ## %else18
; AVX1-NEXT: testl $1024, %eax ## imm = 0x400
; AVX1-NEXT: jne LBB14_21
; AVX1-NEXT: LBB14_22: ## %else20
; AVX1-NEXT: testl $2048, %eax ## imm = 0x800
; AVX1-NEXT: jne LBB14_23
; AVX1-NEXT: LBB14_24: ## %else22
; AVX1-NEXT: testl $4096, %eax ## imm = 0x1000
; AVX1-NEXT: jne LBB14_25
; AVX1-NEXT: LBB14_26: ## %else24
; AVX1-NEXT: testl $8192, %eax ## imm = 0x2000
; AVX1-NEXT: jne LBB14_27
; AVX1-NEXT: LBB14_28: ## %else26
; AVX1-NEXT: testl $16384, %eax ## imm = 0x4000
; AVX1-NEXT: jne LBB14_29
; AVX1-NEXT: LBB14_30: ## %else28
; AVX1-NEXT: testl $32768, %eax ## imm = 0x8000
; AVX1-NEXT: jne LBB14_31
; AVX1-NEXT: LBB14_32: ## %else30
; AVX1-NEXT: vzeroupper
; AVX1-NEXT: retq
; AVX1-NEXT: LBB14_1: ## %cond.store
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; AVX1-NEXT: vpextrw $0, %xmm1, (%rdi)
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX1-NEXT: testb $2, %al
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; AVX1-NEXT: je LBB14_4
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX1-NEXT: LBB14_3: ## %cond.store1
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; AVX1-NEXT: vpextrw $1, %xmm1, 2(%rdi)
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX1-NEXT: testb $4, %al
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; AVX1-NEXT: je LBB14_6
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX1-NEXT: LBB14_5: ## %cond.store3
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; AVX1-NEXT: vpextrw $2, %xmm1, 4(%rdi)
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX1-NEXT: testb $8, %al
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; AVX1-NEXT: je LBB14_8
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX1-NEXT: LBB14_7: ## %cond.store5
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; AVX1-NEXT: vpextrw $3, %xmm1, 6(%rdi)
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX1-NEXT: testb $16, %al
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; AVX1-NEXT: je LBB14_10
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX1-NEXT: LBB14_9: ## %cond.store7
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; AVX1-NEXT: vpextrw $4, %xmm1, 8(%rdi)
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX1-NEXT: testb $32, %al
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; AVX1-NEXT: je LBB14_12
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX1-NEXT: LBB14_11: ## %cond.store9
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; AVX1-NEXT: vpextrw $5, %xmm1, 10(%rdi)
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX1-NEXT: testb $64, %al
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; AVX1-NEXT: je LBB14_14
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX1-NEXT: LBB14_13: ## %cond.store11
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; AVX1-NEXT: vpextrw $6, %xmm1, 12(%rdi)
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX1-NEXT: testb $-128, %al
; AVX1-NEXT: jne LBB14_15
; AVX1-NEXT: jmp LBB14_16
; AVX1-NEXT: LBB14_17: ## %cond.store15
[MIR] Add simple PRE pass to MachineCSE This is the second part of the commit fixing PR38917 (hoisting partitially redundant machine instruction). Most of PRE (partitial redundancy elimination) and CSE work is done on LLVM IR, but some of redundancy arises during DAG legalization. Machine CSE is not enough to deal with it. This simple PRE implementation works a little bit intricately: it passes before CSE, looking for partitial redundancy and transforming it to fully redundancy, anticipating that the next CSE step will eliminate this created redundancy. If CSE doesn't eliminate this, than created instruction will remain dead and eliminated later by Remove Dead Machine Instructions pass. The third part of the commit is supposed to refactor MachineCSE, to make it more clear and to merge MachinePRE with MachineCSE, so one need no rely on further Remove Dead pass to clear instrs not eliminated by CSE. First step: https://reviews.llvm.org/D54839 Fixes llvm.org/PR38917 This is fixed recommit of r361356 after PowerPC64 multistage build failure. llvm-svn: 362901
2019-06-09 20:15:47 +08:00
; AVX1-NEXT: vpextrw $0, %xmm0, 16(%rdi)
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX1-NEXT: testl $512, %eax ## imm = 0x200
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; AVX1-NEXT: je LBB14_20
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX1-NEXT: LBB14_19: ## %cond.store17
[MIR] Add simple PRE pass to MachineCSE This is the second part of the commit fixing PR38917 (hoisting partitially redundant machine instruction). Most of PRE (partitial redundancy elimination) and CSE work is done on LLVM IR, but some of redundancy arises during DAG legalization. Machine CSE is not enough to deal with it. This simple PRE implementation works a little bit intricately: it passes before CSE, looking for partitial redundancy and transforming it to fully redundancy, anticipating that the next CSE step will eliminate this created redundancy. If CSE doesn't eliminate this, than created instruction will remain dead and eliminated later by Remove Dead Machine Instructions pass. The third part of the commit is supposed to refactor MachineCSE, to make it more clear and to merge MachinePRE with MachineCSE, so one need no rely on further Remove Dead pass to clear instrs not eliminated by CSE. First step: https://reviews.llvm.org/D54839 Fixes llvm.org/PR38917 This is fixed recommit of r361356 after PowerPC64 multistage build failure. llvm-svn: 362901
2019-06-09 20:15:47 +08:00
; AVX1-NEXT: vpextrw $1, %xmm0, 18(%rdi)
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX1-NEXT: testl $1024, %eax ## imm = 0x400
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; AVX1-NEXT: je LBB14_22
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX1-NEXT: LBB14_21: ## %cond.store19
[MIR] Add simple PRE pass to MachineCSE This is the second part of the commit fixing PR38917 (hoisting partitially redundant machine instruction). Most of PRE (partitial redundancy elimination) and CSE work is done on LLVM IR, but some of redundancy arises during DAG legalization. Machine CSE is not enough to deal with it. This simple PRE implementation works a little bit intricately: it passes before CSE, looking for partitial redundancy and transforming it to fully redundancy, anticipating that the next CSE step will eliminate this created redundancy. If CSE doesn't eliminate this, than created instruction will remain dead and eliminated later by Remove Dead Machine Instructions pass. The third part of the commit is supposed to refactor MachineCSE, to make it more clear and to merge MachinePRE with MachineCSE, so one need no rely on further Remove Dead pass to clear instrs not eliminated by CSE. First step: https://reviews.llvm.org/D54839 Fixes llvm.org/PR38917 This is fixed recommit of r361356 after PowerPC64 multistage build failure. llvm-svn: 362901
2019-06-09 20:15:47 +08:00
; AVX1-NEXT: vpextrw $2, %xmm0, 20(%rdi)
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX1-NEXT: testl $2048, %eax ## imm = 0x800
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; AVX1-NEXT: je LBB14_24
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX1-NEXT: LBB14_23: ## %cond.store21
[MIR] Add simple PRE pass to MachineCSE This is the second part of the commit fixing PR38917 (hoisting partitially redundant machine instruction). Most of PRE (partitial redundancy elimination) and CSE work is done on LLVM IR, but some of redundancy arises during DAG legalization. Machine CSE is not enough to deal with it. This simple PRE implementation works a little bit intricately: it passes before CSE, looking for partitial redundancy and transforming it to fully redundancy, anticipating that the next CSE step will eliminate this created redundancy. If CSE doesn't eliminate this, than created instruction will remain dead and eliminated later by Remove Dead Machine Instructions pass. The third part of the commit is supposed to refactor MachineCSE, to make it more clear and to merge MachinePRE with MachineCSE, so one need no rely on further Remove Dead pass to clear instrs not eliminated by CSE. First step: https://reviews.llvm.org/D54839 Fixes llvm.org/PR38917 This is fixed recommit of r361356 after PowerPC64 multistage build failure. llvm-svn: 362901
2019-06-09 20:15:47 +08:00
; AVX1-NEXT: vpextrw $3, %xmm0, 22(%rdi)
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX1-NEXT: testl $4096, %eax ## imm = 0x1000
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; AVX1-NEXT: je LBB14_26
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX1-NEXT: LBB14_25: ## %cond.store23
[MIR] Add simple PRE pass to MachineCSE This is the second part of the commit fixing PR38917 (hoisting partitially redundant machine instruction). Most of PRE (partitial redundancy elimination) and CSE work is done on LLVM IR, but some of redundancy arises during DAG legalization. Machine CSE is not enough to deal with it. This simple PRE implementation works a little bit intricately: it passes before CSE, looking for partitial redundancy and transforming it to fully redundancy, anticipating that the next CSE step will eliminate this created redundancy. If CSE doesn't eliminate this, than created instruction will remain dead and eliminated later by Remove Dead Machine Instructions pass. The third part of the commit is supposed to refactor MachineCSE, to make it more clear and to merge MachinePRE with MachineCSE, so one need no rely on further Remove Dead pass to clear instrs not eliminated by CSE. First step: https://reviews.llvm.org/D54839 Fixes llvm.org/PR38917 This is fixed recommit of r361356 after PowerPC64 multistage build failure. llvm-svn: 362901
2019-06-09 20:15:47 +08:00
; AVX1-NEXT: vpextrw $4, %xmm0, 24(%rdi)
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX1-NEXT: testl $8192, %eax ## imm = 0x2000
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; AVX1-NEXT: je LBB14_28
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX1-NEXT: LBB14_27: ## %cond.store25
[MIR] Add simple PRE pass to MachineCSE This is the second part of the commit fixing PR38917 (hoisting partitially redundant machine instruction). Most of PRE (partitial redundancy elimination) and CSE work is done on LLVM IR, but some of redundancy arises during DAG legalization. Machine CSE is not enough to deal with it. This simple PRE implementation works a little bit intricately: it passes before CSE, looking for partitial redundancy and transforming it to fully redundancy, anticipating that the next CSE step will eliminate this created redundancy. If CSE doesn't eliminate this, than created instruction will remain dead and eliminated later by Remove Dead Machine Instructions pass. The third part of the commit is supposed to refactor MachineCSE, to make it more clear and to merge MachinePRE with MachineCSE, so one need no rely on further Remove Dead pass to clear instrs not eliminated by CSE. First step: https://reviews.llvm.org/D54839 Fixes llvm.org/PR38917 This is fixed recommit of r361356 after PowerPC64 multistage build failure. llvm-svn: 362901
2019-06-09 20:15:47 +08:00
; AVX1-NEXT: vpextrw $5, %xmm0, 26(%rdi)
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX1-NEXT: testl $16384, %eax ## imm = 0x4000
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; AVX1-NEXT: je LBB14_30
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX1-NEXT: LBB14_29: ## %cond.store27
[MIR] Add simple PRE pass to MachineCSE This is the second part of the commit fixing PR38917 (hoisting partitially redundant machine instruction). Most of PRE (partitial redundancy elimination) and CSE work is done on LLVM IR, but some of redundancy arises during DAG legalization. Machine CSE is not enough to deal with it. This simple PRE implementation works a little bit intricately: it passes before CSE, looking for partitial redundancy and transforming it to fully redundancy, anticipating that the next CSE step will eliminate this created redundancy. If CSE doesn't eliminate this, than created instruction will remain dead and eliminated later by Remove Dead Machine Instructions pass. The third part of the commit is supposed to refactor MachineCSE, to make it more clear and to merge MachinePRE with MachineCSE, so one need no rely on further Remove Dead pass to clear instrs not eliminated by CSE. First step: https://reviews.llvm.org/D54839 Fixes llvm.org/PR38917 This is fixed recommit of r361356 after PowerPC64 multistage build failure. llvm-svn: 362901
2019-06-09 20:15:47 +08:00
; AVX1-NEXT: vpextrw $6, %xmm0, 28(%rdi)
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX1-NEXT: testl $32768, %eax ## imm = 0x8000
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; AVX1-NEXT: je LBB14_32
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX1-NEXT: LBB14_31: ## %cond.store29
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; AVX1-NEXT: vpextrw $7, %xmm0, 30(%rdi)
; AVX1-NEXT: vzeroupper
; AVX1-NEXT: retq
;
; AVX2-LABEL: store_v16i16_v16i16:
; AVX2: ## %bb.0:
; AVX2-NEXT: vpxor %xmm2, %xmm2, %xmm2
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX2-NEXT: vpcmpeqw %ymm2, %ymm0, %ymm0
; AVX2-NEXT: vextracti128 $1, %ymm0, %xmm2
; AVX2-NEXT: vpacksswb %xmm2, %xmm0, %xmm0
; AVX2-NEXT: vpmovmskb %xmm0, %eax
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; AVX2-NEXT: testb $1, %al
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX2-NEXT: jne LBB14_1
; AVX2-NEXT: ## %bb.2: ## %else
; AVX2-NEXT: testb $2, %al
; AVX2-NEXT: jne LBB14_3
; AVX2-NEXT: LBB14_4: ## %else2
; AVX2-NEXT: testb $4, %al
; AVX2-NEXT: jne LBB14_5
; AVX2-NEXT: LBB14_6: ## %else4
; AVX2-NEXT: testb $8, %al
; AVX2-NEXT: jne LBB14_7
; AVX2-NEXT: LBB14_8: ## %else6
; AVX2-NEXT: testb $16, %al
; AVX2-NEXT: jne LBB14_9
; AVX2-NEXT: LBB14_10: ## %else8
; AVX2-NEXT: testb $32, %al
; AVX2-NEXT: jne LBB14_11
; AVX2-NEXT: LBB14_12: ## %else10
; AVX2-NEXT: testb $64, %al
; AVX2-NEXT: jne LBB14_13
; AVX2-NEXT: LBB14_14: ## %else12
; AVX2-NEXT: testb $-128, %al
; AVX2-NEXT: je LBB14_16
; AVX2-NEXT: LBB14_15: ## %cond.store13
; AVX2-NEXT: vpextrw $7, %xmm1, 14(%rdi)
; AVX2-NEXT: LBB14_16: ## %else14
; AVX2-NEXT: testl $256, %eax ## imm = 0x100
; AVX2-NEXT: vextracti128 $1, %ymm1, %xmm0
; AVX2-NEXT: jne LBB14_17
; AVX2-NEXT: ## %bb.18: ## %else16
; AVX2-NEXT: testl $512, %eax ## imm = 0x200
; AVX2-NEXT: jne LBB14_19
; AVX2-NEXT: LBB14_20: ## %else18
; AVX2-NEXT: testl $1024, %eax ## imm = 0x400
; AVX2-NEXT: jne LBB14_21
; AVX2-NEXT: LBB14_22: ## %else20
; AVX2-NEXT: testl $2048, %eax ## imm = 0x800
; AVX2-NEXT: jne LBB14_23
; AVX2-NEXT: LBB14_24: ## %else22
; AVX2-NEXT: testl $4096, %eax ## imm = 0x1000
; AVX2-NEXT: jne LBB14_25
; AVX2-NEXT: LBB14_26: ## %else24
; AVX2-NEXT: testl $8192, %eax ## imm = 0x2000
; AVX2-NEXT: jne LBB14_27
; AVX2-NEXT: LBB14_28: ## %else26
; AVX2-NEXT: testl $16384, %eax ## imm = 0x4000
; AVX2-NEXT: jne LBB14_29
; AVX2-NEXT: LBB14_30: ## %else28
; AVX2-NEXT: testl $32768, %eax ## imm = 0x8000
; AVX2-NEXT: jne LBB14_31
; AVX2-NEXT: LBB14_32: ## %else30
; AVX2-NEXT: vzeroupper
; AVX2-NEXT: retq
; AVX2-NEXT: LBB14_1: ## %cond.store
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; AVX2-NEXT: vpextrw $0, %xmm1, (%rdi)
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX2-NEXT: testb $2, %al
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; AVX2-NEXT: je LBB14_4
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX2-NEXT: LBB14_3: ## %cond.store1
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; AVX2-NEXT: vpextrw $1, %xmm1, 2(%rdi)
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX2-NEXT: testb $4, %al
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; AVX2-NEXT: je LBB14_6
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX2-NEXT: LBB14_5: ## %cond.store3
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; AVX2-NEXT: vpextrw $2, %xmm1, 4(%rdi)
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX2-NEXT: testb $8, %al
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; AVX2-NEXT: je LBB14_8
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX2-NEXT: LBB14_7: ## %cond.store5
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; AVX2-NEXT: vpextrw $3, %xmm1, 6(%rdi)
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX2-NEXT: testb $16, %al
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; AVX2-NEXT: je LBB14_10
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX2-NEXT: LBB14_9: ## %cond.store7
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; AVX2-NEXT: vpextrw $4, %xmm1, 8(%rdi)
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX2-NEXT: testb $32, %al
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; AVX2-NEXT: je LBB14_12
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX2-NEXT: LBB14_11: ## %cond.store9
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; AVX2-NEXT: vpextrw $5, %xmm1, 10(%rdi)
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX2-NEXT: testb $64, %al
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; AVX2-NEXT: je LBB14_14
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX2-NEXT: LBB14_13: ## %cond.store11
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; AVX2-NEXT: vpextrw $6, %xmm1, 12(%rdi)
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX2-NEXT: testb $-128, %al
; AVX2-NEXT: jne LBB14_15
; AVX2-NEXT: jmp LBB14_16
; AVX2-NEXT: LBB14_17: ## %cond.store15
[X86][SSE] X86TargetLowering::isCommutativeBinOp - add PCMPEQ Allows narrowInsertExtractVectorBinOp to reduce vector size llvm-svn: 364432
2019-06-26 22:40:49 +08:00
; AVX2-NEXT: vpextrw $0, %xmm0, 16(%rdi)
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX2-NEXT: testl $512, %eax ## imm = 0x200
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; AVX2-NEXT: je LBB14_20
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX2-NEXT: LBB14_19: ## %cond.store17
[X86][SSE] X86TargetLowering::isCommutativeBinOp - add PCMPEQ Allows narrowInsertExtractVectorBinOp to reduce vector size llvm-svn: 364432
2019-06-26 22:40:49 +08:00
; AVX2-NEXT: vpextrw $1, %xmm0, 18(%rdi)
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX2-NEXT: testl $1024, %eax ## imm = 0x400
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; AVX2-NEXT: je LBB14_22
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX2-NEXT: LBB14_21: ## %cond.store19
[X86][SSE] X86TargetLowering::isCommutativeBinOp - add PCMPEQ Allows narrowInsertExtractVectorBinOp to reduce vector size llvm-svn: 364432
2019-06-26 22:40:49 +08:00
; AVX2-NEXT: vpextrw $2, %xmm0, 20(%rdi)
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX2-NEXT: testl $2048, %eax ## imm = 0x800
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; AVX2-NEXT: je LBB14_24
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX2-NEXT: LBB14_23: ## %cond.store21
[X86][SSE] X86TargetLowering::isCommutativeBinOp - add PCMPEQ Allows narrowInsertExtractVectorBinOp to reduce vector size llvm-svn: 364432
2019-06-26 22:40:49 +08:00
; AVX2-NEXT: vpextrw $3, %xmm0, 22(%rdi)
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX2-NEXT: testl $4096, %eax ## imm = 0x1000
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; AVX2-NEXT: je LBB14_26
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX2-NEXT: LBB14_25: ## %cond.store23
[X86][SSE] X86TargetLowering::isCommutativeBinOp - add PCMPEQ Allows narrowInsertExtractVectorBinOp to reduce vector size llvm-svn: 364432
2019-06-26 22:40:49 +08:00
; AVX2-NEXT: vpextrw $4, %xmm0, 24(%rdi)
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX2-NEXT: testl $8192, %eax ## imm = 0x2000
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; AVX2-NEXT: je LBB14_28
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX2-NEXT: LBB14_27: ## %cond.store25
[X86][SSE] X86TargetLowering::isCommutativeBinOp - add PCMPEQ Allows narrowInsertExtractVectorBinOp to reduce vector size llvm-svn: 364432
2019-06-26 22:40:49 +08:00
; AVX2-NEXT: vpextrw $5, %xmm0, 26(%rdi)
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX2-NEXT: testl $16384, %eax ## imm = 0x4000
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; AVX2-NEXT: je LBB14_30
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX2-NEXT: LBB14_29: ## %cond.store27
[X86][SSE] X86TargetLowering::isCommutativeBinOp - add PCMPEQ Allows narrowInsertExtractVectorBinOp to reduce vector size llvm-svn: 364432
2019-06-26 22:40:49 +08:00
; AVX2-NEXT: vpextrw $6, %xmm0, 28(%rdi)
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX2-NEXT: testl $32768, %eax ## imm = 0x8000
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; AVX2-NEXT: je LBB14_32
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX2-NEXT: LBB14_31: ## %cond.store29
[X86][SSE] X86TargetLowering::isCommutativeBinOp - add PCMPEQ Allows narrowInsertExtractVectorBinOp to reduce vector size llvm-svn: 364432
2019-06-26 22:40:49 +08:00
; AVX2-NEXT: vpextrw $7, %xmm0, 30(%rdi)
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; AVX2-NEXT: vzeroupper
; AVX2-NEXT: retq
;
; AVX512F-LABEL: store_v16i16_v16i16:
; AVX512F: ## %bb.0:
; AVX512F-NEXT: vpxor %xmm2, %xmm2, %xmm2
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX512F-NEXT: vpcmpeqw %ymm2, %ymm0, %ymm0
; AVX512F-NEXT: vpmovsxwd %ymm0, %zmm0
; AVX512F-NEXT: vptestmd %zmm0, %zmm0, %k0
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; AVX512F-NEXT: kmovw %k0, %eax
; AVX512F-NEXT: testb $1, %al
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX512F-NEXT: jne LBB14_1
; AVX512F-NEXT: ## %bb.2: ## %else
; AVX512F-NEXT: testb $2, %al
; AVX512F-NEXT: jne LBB14_3
; AVX512F-NEXT: LBB14_4: ## %else2
; AVX512F-NEXT: testb $4, %al
; AVX512F-NEXT: jne LBB14_5
; AVX512F-NEXT: LBB14_6: ## %else4
; AVX512F-NEXT: testb $8, %al
; AVX512F-NEXT: jne LBB14_7
; AVX512F-NEXT: LBB14_8: ## %else6
; AVX512F-NEXT: testb $16, %al
; AVX512F-NEXT: jne LBB14_9
; AVX512F-NEXT: LBB14_10: ## %else8
; AVX512F-NEXT: testb $32, %al
; AVX512F-NEXT: jne LBB14_11
; AVX512F-NEXT: LBB14_12: ## %else10
; AVX512F-NEXT: testb $64, %al
; AVX512F-NEXT: jne LBB14_13
; AVX512F-NEXT: LBB14_14: ## %else12
; AVX512F-NEXT: testb $-128, %al
; AVX512F-NEXT: je LBB14_16
; AVX512F-NEXT: LBB14_15: ## %cond.store13
; AVX512F-NEXT: vpextrw $7, %xmm1, 14(%rdi)
; AVX512F-NEXT: LBB14_16: ## %else14
; AVX512F-NEXT: testl $256, %eax ## imm = 0x100
; AVX512F-NEXT: vextracti128 $1, %ymm1, %xmm0
; AVX512F-NEXT: jne LBB14_17
; AVX512F-NEXT: ## %bb.18: ## %else16
; AVX512F-NEXT: testl $512, %eax ## imm = 0x200
; AVX512F-NEXT: jne LBB14_19
; AVX512F-NEXT: LBB14_20: ## %else18
; AVX512F-NEXT: testl $1024, %eax ## imm = 0x400
; AVX512F-NEXT: jne LBB14_21
; AVX512F-NEXT: LBB14_22: ## %else20
; AVX512F-NEXT: testl $2048, %eax ## imm = 0x800
; AVX512F-NEXT: jne LBB14_23
; AVX512F-NEXT: LBB14_24: ## %else22
; AVX512F-NEXT: testl $4096, %eax ## imm = 0x1000
; AVX512F-NEXT: jne LBB14_25
; AVX512F-NEXT: LBB14_26: ## %else24
; AVX512F-NEXT: testl $8192, %eax ## imm = 0x2000
; AVX512F-NEXT: jne LBB14_27
; AVX512F-NEXT: LBB14_28: ## %else26
; AVX512F-NEXT: testl $16384, %eax ## imm = 0x4000
; AVX512F-NEXT: jne LBB14_29
; AVX512F-NEXT: LBB14_30: ## %else28
; AVX512F-NEXT: testl $32768, %eax ## imm = 0x8000
; AVX512F-NEXT: jne LBB14_31
; AVX512F-NEXT: LBB14_32: ## %else30
; AVX512F-NEXT: vzeroupper
; AVX512F-NEXT: retq
; AVX512F-NEXT: LBB14_1: ## %cond.store
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; AVX512F-NEXT: vpextrw $0, %xmm1, (%rdi)
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX512F-NEXT: testb $2, %al
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; AVX512F-NEXT: je LBB14_4
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX512F-NEXT: LBB14_3: ## %cond.store1
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; AVX512F-NEXT: vpextrw $1, %xmm1, 2(%rdi)
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX512F-NEXT: testb $4, %al
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; AVX512F-NEXT: je LBB14_6
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX512F-NEXT: LBB14_5: ## %cond.store3
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; AVX512F-NEXT: vpextrw $2, %xmm1, 4(%rdi)
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX512F-NEXT: testb $8, %al
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; AVX512F-NEXT: je LBB14_8
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX512F-NEXT: LBB14_7: ## %cond.store5
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; AVX512F-NEXT: vpextrw $3, %xmm1, 6(%rdi)
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX512F-NEXT: testb $16, %al
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; AVX512F-NEXT: je LBB14_10
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX512F-NEXT: LBB14_9: ## %cond.store7
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; AVX512F-NEXT: vpextrw $4, %xmm1, 8(%rdi)
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX512F-NEXT: testb $32, %al
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; AVX512F-NEXT: je LBB14_12
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX512F-NEXT: LBB14_11: ## %cond.store9
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; AVX512F-NEXT: vpextrw $5, %xmm1, 10(%rdi)
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX512F-NEXT: testb $64, %al
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; AVX512F-NEXT: je LBB14_14
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX512F-NEXT: LBB14_13: ## %cond.store11
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; AVX512F-NEXT: vpextrw $6, %xmm1, 12(%rdi)
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX512F-NEXT: testb $-128, %al
; AVX512F-NEXT: jne LBB14_15
; AVX512F-NEXT: jmp LBB14_16
; AVX512F-NEXT: LBB14_17: ## %cond.store15
; AVX512F-NEXT: vpextrw $0, %xmm0, 16(%rdi)
; AVX512F-NEXT: testl $512, %eax ## imm = 0x200
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; AVX512F-NEXT: je LBB14_20
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX512F-NEXT: LBB14_19: ## %cond.store17
; AVX512F-NEXT: vpextrw $1, %xmm0, 18(%rdi)
; AVX512F-NEXT: testl $1024, %eax ## imm = 0x400
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; AVX512F-NEXT: je LBB14_22
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX512F-NEXT: LBB14_21: ## %cond.store19
; AVX512F-NEXT: vpextrw $2, %xmm0, 20(%rdi)
; AVX512F-NEXT: testl $2048, %eax ## imm = 0x800
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; AVX512F-NEXT: je LBB14_24
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX512F-NEXT: LBB14_23: ## %cond.store21
; AVX512F-NEXT: vpextrw $3, %xmm0, 22(%rdi)
; AVX512F-NEXT: testl $4096, %eax ## imm = 0x1000
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; AVX512F-NEXT: je LBB14_26
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX512F-NEXT: LBB14_25: ## %cond.store23
; AVX512F-NEXT: vpextrw $4, %xmm0, 24(%rdi)
; AVX512F-NEXT: testl $8192, %eax ## imm = 0x2000
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; AVX512F-NEXT: je LBB14_28
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX512F-NEXT: LBB14_27: ## %cond.store25
; AVX512F-NEXT: vpextrw $5, %xmm0, 26(%rdi)
; AVX512F-NEXT: testl $16384, %eax ## imm = 0x4000
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; AVX512F-NEXT: je LBB14_30
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX512F-NEXT: LBB14_29: ## %cond.store27
; AVX512F-NEXT: vpextrw $6, %xmm0, 28(%rdi)
; AVX512F-NEXT: testl $32768, %eax ## imm = 0x8000
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; AVX512F-NEXT: je LBB14_32
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX512F-NEXT: LBB14_31: ## %cond.store29
; AVX512F-NEXT: vpextrw $7, %xmm0, 30(%rdi)
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; AVX512F-NEXT: vzeroupper
; AVX512F-NEXT: retq
;
[X86][AVX] Add AVX512DQ coverage for masked memory ops tests (PR34584) llvm-svn: 359395
2019-04-28 18:02:34 +08:00
; AVX512VLDQ-LABEL: store_v16i16_v16i16:
; AVX512VLDQ: ## %bb.0:
; AVX512VLDQ-NEXT: vpxor %xmm2, %xmm2, %xmm2
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX512VLDQ-NEXT: vpcmpeqw %ymm2, %ymm0, %ymm0
; AVX512VLDQ-NEXT: vpmovsxwd %ymm0, %zmm0
; AVX512VLDQ-NEXT: vpmovd2m %zmm0, %k0
[X86][AVX] Add AVX512DQ coverage for masked memory ops tests (PR34584) llvm-svn: 359395
2019-04-28 18:02:34 +08:00
; AVX512VLDQ-NEXT: kmovw %k0, %eax
; AVX512VLDQ-NEXT: testb $1, %al
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX512VLDQ-NEXT: jne LBB14_1
; AVX512VLDQ-NEXT: ## %bb.2: ## %else
; AVX512VLDQ-NEXT: testb $2, %al
; AVX512VLDQ-NEXT: jne LBB14_3
; AVX512VLDQ-NEXT: LBB14_4: ## %else2
; AVX512VLDQ-NEXT: testb $4, %al
; AVX512VLDQ-NEXT: jne LBB14_5
; AVX512VLDQ-NEXT: LBB14_6: ## %else4
; AVX512VLDQ-NEXT: testb $8, %al
; AVX512VLDQ-NEXT: jne LBB14_7
; AVX512VLDQ-NEXT: LBB14_8: ## %else6
; AVX512VLDQ-NEXT: testb $16, %al
; AVX512VLDQ-NEXT: jne LBB14_9
; AVX512VLDQ-NEXT: LBB14_10: ## %else8
; AVX512VLDQ-NEXT: testb $32, %al
; AVX512VLDQ-NEXT: jne LBB14_11
; AVX512VLDQ-NEXT: LBB14_12: ## %else10
; AVX512VLDQ-NEXT: testb $64, %al
; AVX512VLDQ-NEXT: jne LBB14_13
; AVX512VLDQ-NEXT: LBB14_14: ## %else12
; AVX512VLDQ-NEXT: testb $-128, %al
; AVX512VLDQ-NEXT: je LBB14_16
; AVX512VLDQ-NEXT: LBB14_15: ## %cond.store13
; AVX512VLDQ-NEXT: vpextrw $7, %xmm1, 14(%rdi)
; AVX512VLDQ-NEXT: LBB14_16: ## %else14
; AVX512VLDQ-NEXT: testl $256, %eax ## imm = 0x100
; AVX512VLDQ-NEXT: vextracti128 $1, %ymm1, %xmm0
; AVX512VLDQ-NEXT: jne LBB14_17
; AVX512VLDQ-NEXT: ## %bb.18: ## %else16
; AVX512VLDQ-NEXT: testl $512, %eax ## imm = 0x200
; AVX512VLDQ-NEXT: jne LBB14_19
; AVX512VLDQ-NEXT: LBB14_20: ## %else18
; AVX512VLDQ-NEXT: testl $1024, %eax ## imm = 0x400
; AVX512VLDQ-NEXT: jne LBB14_21
; AVX512VLDQ-NEXT: LBB14_22: ## %else20
; AVX512VLDQ-NEXT: testl $2048, %eax ## imm = 0x800
; AVX512VLDQ-NEXT: jne LBB14_23
; AVX512VLDQ-NEXT: LBB14_24: ## %else22
; AVX512VLDQ-NEXT: testl $4096, %eax ## imm = 0x1000
; AVX512VLDQ-NEXT: jne LBB14_25
; AVX512VLDQ-NEXT: LBB14_26: ## %else24
; AVX512VLDQ-NEXT: testl $8192, %eax ## imm = 0x2000
; AVX512VLDQ-NEXT: jne LBB14_27
; AVX512VLDQ-NEXT: LBB14_28: ## %else26
; AVX512VLDQ-NEXT: testl $16384, %eax ## imm = 0x4000
; AVX512VLDQ-NEXT: jne LBB14_29
; AVX512VLDQ-NEXT: LBB14_30: ## %else28
; AVX512VLDQ-NEXT: testl $32768, %eax ## imm = 0x8000
; AVX512VLDQ-NEXT: jne LBB14_31
; AVX512VLDQ-NEXT: LBB14_32: ## %else30
; AVX512VLDQ-NEXT: vzeroupper
; AVX512VLDQ-NEXT: retq
; AVX512VLDQ-NEXT: LBB14_1: ## %cond.store
[X86][AVX] Add AVX512DQ coverage for masked memory ops tests (PR34584) llvm-svn: 359395
2019-04-28 18:02:34 +08:00
; AVX512VLDQ-NEXT: vpextrw $0, %xmm1, (%rdi)
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX512VLDQ-NEXT: testb $2, %al
[X86][AVX] Add AVX512DQ coverage for masked memory ops tests (PR34584) llvm-svn: 359395
2019-04-28 18:02:34 +08:00
; AVX512VLDQ-NEXT: je LBB14_4
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX512VLDQ-NEXT: LBB14_3: ## %cond.store1
[X86][AVX] Add AVX512DQ coverage for masked memory ops tests (PR34584) llvm-svn: 359395
2019-04-28 18:02:34 +08:00
; AVX512VLDQ-NEXT: vpextrw $1, %xmm1, 2(%rdi)
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX512VLDQ-NEXT: testb $4, %al
[X86][AVX] Add AVX512DQ coverage for masked memory ops tests (PR34584) llvm-svn: 359395
2019-04-28 18:02:34 +08:00
; AVX512VLDQ-NEXT: je LBB14_6
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX512VLDQ-NEXT: LBB14_5: ## %cond.store3
[X86][AVX] Add AVX512DQ coverage for masked memory ops tests (PR34584) llvm-svn: 359395
2019-04-28 18:02:34 +08:00
; AVX512VLDQ-NEXT: vpextrw $2, %xmm1, 4(%rdi)
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX512VLDQ-NEXT: testb $8, %al
[X86][AVX] Add AVX512DQ coverage for masked memory ops tests (PR34584) llvm-svn: 359395
2019-04-28 18:02:34 +08:00
; AVX512VLDQ-NEXT: je LBB14_8
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX512VLDQ-NEXT: LBB14_7: ## %cond.store5
[X86][AVX] Add AVX512DQ coverage for masked memory ops tests (PR34584) llvm-svn: 359395
2019-04-28 18:02:34 +08:00
; AVX512VLDQ-NEXT: vpextrw $3, %xmm1, 6(%rdi)
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX512VLDQ-NEXT: testb $16, %al
[X86][AVX] Add AVX512DQ coverage for masked memory ops tests (PR34584) llvm-svn: 359395
2019-04-28 18:02:34 +08:00
; AVX512VLDQ-NEXT: je LBB14_10
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX512VLDQ-NEXT: LBB14_9: ## %cond.store7
[X86][AVX] Add AVX512DQ coverage for masked memory ops tests (PR34584) llvm-svn: 359395
2019-04-28 18:02:34 +08:00
; AVX512VLDQ-NEXT: vpextrw $4, %xmm1, 8(%rdi)
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX512VLDQ-NEXT: testb $32, %al
[X86][AVX] Add AVX512DQ coverage for masked memory ops tests (PR34584) llvm-svn: 359395
2019-04-28 18:02:34 +08:00
; AVX512VLDQ-NEXT: je LBB14_12
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX512VLDQ-NEXT: LBB14_11: ## %cond.store9
[X86][AVX] Add AVX512DQ coverage for masked memory ops tests (PR34584) llvm-svn: 359395
2019-04-28 18:02:34 +08:00
; AVX512VLDQ-NEXT: vpextrw $5, %xmm1, 10(%rdi)
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX512VLDQ-NEXT: testb $64, %al
[X86][AVX] Add AVX512DQ coverage for masked memory ops tests (PR34584) llvm-svn: 359395
2019-04-28 18:02:34 +08:00
; AVX512VLDQ-NEXT: je LBB14_14
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX512VLDQ-NEXT: LBB14_13: ## %cond.store11
[X86][AVX] Add AVX512DQ coverage for masked memory ops tests (PR34584) llvm-svn: 359395
2019-04-28 18:02:34 +08:00
; AVX512VLDQ-NEXT: vpextrw $6, %xmm1, 12(%rdi)
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX512VLDQ-NEXT: testb $-128, %al
; AVX512VLDQ-NEXT: jne LBB14_15
; AVX512VLDQ-NEXT: jmp LBB14_16
; AVX512VLDQ-NEXT: LBB14_17: ## %cond.store15
; AVX512VLDQ-NEXT: vpextrw $0, %xmm0, 16(%rdi)
; AVX512VLDQ-NEXT: testl $512, %eax ## imm = 0x200
[X86][AVX] Add AVX512DQ coverage for masked memory ops tests (PR34584) llvm-svn: 359395
2019-04-28 18:02:34 +08:00
; AVX512VLDQ-NEXT: je LBB14_20
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX512VLDQ-NEXT: LBB14_19: ## %cond.store17
; AVX512VLDQ-NEXT: vpextrw $1, %xmm0, 18(%rdi)
; AVX512VLDQ-NEXT: testl $1024, %eax ## imm = 0x400
[X86][AVX] Add AVX512DQ coverage for masked memory ops tests (PR34584) llvm-svn: 359395
2019-04-28 18:02:34 +08:00
; AVX512VLDQ-NEXT: je LBB14_22
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX512VLDQ-NEXT: LBB14_21: ## %cond.store19
; AVX512VLDQ-NEXT: vpextrw $2, %xmm0, 20(%rdi)
; AVX512VLDQ-NEXT: testl $2048, %eax ## imm = 0x800
[X86][AVX] Add AVX512DQ coverage for masked memory ops tests (PR34584) llvm-svn: 359395
2019-04-28 18:02:34 +08:00
; AVX512VLDQ-NEXT: je LBB14_24
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX512VLDQ-NEXT: LBB14_23: ## %cond.store21
; AVX512VLDQ-NEXT: vpextrw $3, %xmm0, 22(%rdi)
; AVX512VLDQ-NEXT: testl $4096, %eax ## imm = 0x1000
[X86][AVX] Add AVX512DQ coverage for masked memory ops tests (PR34584) llvm-svn: 359395
2019-04-28 18:02:34 +08:00
; AVX512VLDQ-NEXT: je LBB14_26
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX512VLDQ-NEXT: LBB14_25: ## %cond.store23
; AVX512VLDQ-NEXT: vpextrw $4, %xmm0, 24(%rdi)
; AVX512VLDQ-NEXT: testl $8192, %eax ## imm = 0x2000
[X86][AVX] Add AVX512DQ coverage for masked memory ops tests (PR34584) llvm-svn: 359395
2019-04-28 18:02:34 +08:00
; AVX512VLDQ-NEXT: je LBB14_28
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX512VLDQ-NEXT: LBB14_27: ## %cond.store25
; AVX512VLDQ-NEXT: vpextrw $5, %xmm0, 26(%rdi)
; AVX512VLDQ-NEXT: testl $16384, %eax ## imm = 0x4000
[X86][AVX] Add AVX512DQ coverage for masked memory ops tests (PR34584) llvm-svn: 359395
2019-04-28 18:02:34 +08:00
; AVX512VLDQ-NEXT: je LBB14_30
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX512VLDQ-NEXT: LBB14_29: ## %cond.store27
; AVX512VLDQ-NEXT: vpextrw $6, %xmm0, 28(%rdi)
; AVX512VLDQ-NEXT: testl $32768, %eax ## imm = 0x8000
[X86][AVX] Add AVX512DQ coverage for masked memory ops tests (PR34584) llvm-svn: 359395
2019-04-28 18:02:34 +08:00
; AVX512VLDQ-NEXT: je LBB14_32
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX512VLDQ-NEXT: LBB14_31: ## %cond.store29
; AVX512VLDQ-NEXT: vpextrw $7, %xmm0, 30(%rdi)
[X86][AVX] Add AVX512DQ coverage for masked memory ops tests (PR34584) llvm-svn: 359395
2019-04-28 18:02:34 +08:00
; AVX512VLDQ-NEXT: vzeroupper
; AVX512VLDQ-NEXT: retq
;
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; AVX512VLBW-LABEL: store_v16i16_v16i16:
; AVX512VLBW: ## %bb.0:
; AVX512VLBW-NEXT: vptestnmw %ymm0, %ymm0, %k1
; AVX512VLBW-NEXT: vmovdqu16 %ymm1, (%rdi) {%k1}
; AVX512VLBW-NEXT: vzeroupper
; AVX512VLBW-NEXT: retq
%mask = icmp eq <16 x i16> %trigger, zeroinitializer
call void @llvm.masked.store.v16i16.p0v16i16(<16 x i16> %val, <16 x i16>* %addr, i32 4, <16 x i1> %mask)
ret void
}
;
; vXi8
;
define void @store_v16i8_v16i8(<16 x i8> %trigger, <16 x i8>* %addr, <16 x i8> %val) {
; SSE2-LABEL: store_v16i8_v16i8:
; SSE2: ## %bb.0:
; SSE2-NEXT: pxor %xmm2, %xmm2
; SSE2-NEXT: pcmpeqb %xmm0, %xmm2
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE2-NEXT: pmovmskb %xmm2, %eax
; SSE2-NEXT: testb $1, %al
; SSE2-NEXT: movd %xmm1, %ecx
; SSE2-NEXT: jne LBB15_1
; SSE2-NEXT: ## %bb.2: ## %else
; SSE2-NEXT: testb $2, %al
; SSE2-NEXT: jne LBB15_3
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; SSE2-NEXT: LBB15_4: ## %else2
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE2-NEXT: testb $4, %al
; SSE2-NEXT: jne LBB15_5
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; SSE2-NEXT: LBB15_6: ## %else4
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE2-NEXT: testb $8, %al
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; SSE2-NEXT: je LBB15_8
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE2-NEXT: LBB15_7: ## %cond.store5
; SSE2-NEXT: shrl $24, %ecx
; SSE2-NEXT: movb %cl, 3(%rdi)
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; SSE2-NEXT: LBB15_8: ## %else6
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE2-NEXT: testb $16, %al
; SSE2-NEXT: pextrw $2, %xmm1, %ecx
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; SSE2-NEXT: je LBB15_10
; SSE2-NEXT: ## %bb.9: ## %cond.store7
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE2-NEXT: movb %cl, 4(%rdi)
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; SSE2-NEXT: LBB15_10: ## %else8
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE2-NEXT: testb $32, %al
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; SSE2-NEXT: je LBB15_12
; SSE2-NEXT: ## %bb.11: ## %cond.store9
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE2-NEXT: movb %ch, 5(%rdi)
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; SSE2-NEXT: LBB15_12: ## %else10
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE2-NEXT: testb $64, %al
; SSE2-NEXT: pextrw $3, %xmm1, %ecx
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; SSE2-NEXT: je LBB15_14
; SSE2-NEXT: ## %bb.13: ## %cond.store11
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE2-NEXT: movb %cl, 6(%rdi)
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; SSE2-NEXT: LBB15_14: ## %else12
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE2-NEXT: testb $-128, %al
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; SSE2-NEXT: je LBB15_16
; SSE2-NEXT: ## %bb.15: ## %cond.store13
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE2-NEXT: movb %ch, 7(%rdi)
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; SSE2-NEXT: LBB15_16: ## %else14
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE2-NEXT: testl $256, %eax ## imm = 0x100
; SSE2-NEXT: pextrw $4, %xmm1, %ecx
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; SSE2-NEXT: je LBB15_18
; SSE2-NEXT: ## %bb.17: ## %cond.store15
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE2-NEXT: movb %cl, 8(%rdi)
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; SSE2-NEXT: LBB15_18: ## %else16
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE2-NEXT: testl $512, %eax ## imm = 0x200
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; SSE2-NEXT: je LBB15_20
; SSE2-NEXT: ## %bb.19: ## %cond.store17
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE2-NEXT: movb %ch, 9(%rdi)
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; SSE2-NEXT: LBB15_20: ## %else18
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE2-NEXT: testl $1024, %eax ## imm = 0x400
; SSE2-NEXT: pextrw $5, %xmm1, %ecx
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; SSE2-NEXT: je LBB15_22
; SSE2-NEXT: ## %bb.21: ## %cond.store19
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE2-NEXT: movb %cl, 10(%rdi)
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; SSE2-NEXT: LBB15_22: ## %else20
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE2-NEXT: testl $2048, %eax ## imm = 0x800
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; SSE2-NEXT: je LBB15_24
; SSE2-NEXT: ## %bb.23: ## %cond.store21
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE2-NEXT: movb %ch, 11(%rdi)
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; SSE2-NEXT: LBB15_24: ## %else22
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE2-NEXT: testl $4096, %eax ## imm = 0x1000
; SSE2-NEXT: pextrw $6, %xmm1, %ecx
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; SSE2-NEXT: je LBB15_26
; SSE2-NEXT: ## %bb.25: ## %cond.store23
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE2-NEXT: movb %cl, 12(%rdi)
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; SSE2-NEXT: LBB15_26: ## %else24
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE2-NEXT: testl $8192, %eax ## imm = 0x2000
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; SSE2-NEXT: je LBB15_28
; SSE2-NEXT: ## %bb.27: ## %cond.store25
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE2-NEXT: movb %ch, 13(%rdi)
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; SSE2-NEXT: LBB15_28: ## %else26
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE2-NEXT: testl $16384, %eax ## imm = 0x4000
; SSE2-NEXT: pextrw $7, %xmm1, %ecx
; SSE2-NEXT: jne LBB15_29
; SSE2-NEXT: ## %bb.30: ## %else28
; SSE2-NEXT: testl $32768, %eax ## imm = 0x8000
; SSE2-NEXT: jne LBB15_31
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; SSE2-NEXT: LBB15_32: ## %else30
; SSE2-NEXT: retq
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE2-NEXT: LBB15_1: ## %cond.store
; SSE2-NEXT: movb %cl, (%rdi)
; SSE2-NEXT: testb $2, %al
; SSE2-NEXT: je LBB15_4
; SSE2-NEXT: LBB15_3: ## %cond.store1
; SSE2-NEXT: movb %ch, 1(%rdi)
; SSE2-NEXT: testb $4, %al
; SSE2-NEXT: je LBB15_6
; SSE2-NEXT: LBB15_5: ## %cond.store3
; SSE2-NEXT: movl %ecx, %edx
; SSE2-NEXT: shrl $16, %edx
; SSE2-NEXT: movb %dl, 2(%rdi)
; SSE2-NEXT: testb $8, %al
; SSE2-NEXT: jne LBB15_7
; SSE2-NEXT: jmp LBB15_8
; SSE2-NEXT: LBB15_29: ## %cond.store27
; SSE2-NEXT: movb %cl, 14(%rdi)
; SSE2-NEXT: testl $32768, %eax ## imm = 0x8000
; SSE2-NEXT: je LBB15_32
; SSE2-NEXT: LBB15_31: ## %cond.store29
; SSE2-NEXT: movb %ch, 15(%rdi)
; SSE2-NEXT: retq
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
;
; SSE4-LABEL: store_v16i8_v16i8:
; SSE4: ## %bb.0:
; SSE4-NEXT: pxor %xmm2, %xmm2
; SSE4-NEXT: pcmpeqb %xmm0, %xmm2
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE4-NEXT: pmovmskb %xmm2, %eax
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; SSE4-NEXT: testb $1, %al
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE4-NEXT: jne LBB15_1
; SSE4-NEXT: ## %bb.2: ## %else
; SSE4-NEXT: testb $2, %al
; SSE4-NEXT: jne LBB15_3
; SSE4-NEXT: LBB15_4: ## %else2
; SSE4-NEXT: testb $4, %al
; SSE4-NEXT: jne LBB15_5
; SSE4-NEXT: LBB15_6: ## %else4
; SSE4-NEXT: testb $8, %al
; SSE4-NEXT: jne LBB15_7
; SSE4-NEXT: LBB15_8: ## %else6
; SSE4-NEXT: testb $16, %al
; SSE4-NEXT: jne LBB15_9
; SSE4-NEXT: LBB15_10: ## %else8
; SSE4-NEXT: testb $32, %al
; SSE4-NEXT: jne LBB15_11
; SSE4-NEXT: LBB15_12: ## %else10
; SSE4-NEXT: testb $64, %al
; SSE4-NEXT: jne LBB15_13
; SSE4-NEXT: LBB15_14: ## %else12
; SSE4-NEXT: testb $-128, %al
; SSE4-NEXT: jne LBB15_15
; SSE4-NEXT: LBB15_16: ## %else14
; SSE4-NEXT: testl $256, %eax ## imm = 0x100
; SSE4-NEXT: jne LBB15_17
; SSE4-NEXT: LBB15_18: ## %else16
; SSE4-NEXT: testl $512, %eax ## imm = 0x200
; SSE4-NEXT: jne LBB15_19
; SSE4-NEXT: LBB15_20: ## %else18
; SSE4-NEXT: testl $1024, %eax ## imm = 0x400
; SSE4-NEXT: jne LBB15_21
; SSE4-NEXT: LBB15_22: ## %else20
; SSE4-NEXT: testl $2048, %eax ## imm = 0x800
; SSE4-NEXT: jne LBB15_23
; SSE4-NEXT: LBB15_24: ## %else22
; SSE4-NEXT: testl $4096, %eax ## imm = 0x1000
; SSE4-NEXT: jne LBB15_25
; SSE4-NEXT: LBB15_26: ## %else24
; SSE4-NEXT: testl $8192, %eax ## imm = 0x2000
; SSE4-NEXT: jne LBB15_27
; SSE4-NEXT: LBB15_28: ## %else26
; SSE4-NEXT: testl $16384, %eax ## imm = 0x4000
; SSE4-NEXT: jne LBB15_29
; SSE4-NEXT: LBB15_30: ## %else28
; SSE4-NEXT: testl $32768, %eax ## imm = 0x8000
; SSE4-NEXT: jne LBB15_31
; SSE4-NEXT: LBB15_32: ## %else30
; SSE4-NEXT: retq
; SSE4-NEXT: LBB15_1: ## %cond.store
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; SSE4-NEXT: pextrb $0, %xmm1, (%rdi)
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE4-NEXT: testb $2, %al
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; SSE4-NEXT: je LBB15_4
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE4-NEXT: LBB15_3: ## %cond.store1
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; SSE4-NEXT: pextrb $1, %xmm1, 1(%rdi)
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE4-NEXT: testb $4, %al
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; SSE4-NEXT: je LBB15_6
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE4-NEXT: LBB15_5: ## %cond.store3
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; SSE4-NEXT: pextrb $2, %xmm1, 2(%rdi)
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE4-NEXT: testb $8, %al
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; SSE4-NEXT: je LBB15_8
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE4-NEXT: LBB15_7: ## %cond.store5
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; SSE4-NEXT: pextrb $3, %xmm1, 3(%rdi)
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE4-NEXT: testb $16, %al
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; SSE4-NEXT: je LBB15_10
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE4-NEXT: LBB15_9: ## %cond.store7
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; SSE4-NEXT: pextrb $4, %xmm1, 4(%rdi)
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE4-NEXT: testb $32, %al
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; SSE4-NEXT: je LBB15_12
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE4-NEXT: LBB15_11: ## %cond.store9
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; SSE4-NEXT: pextrb $5, %xmm1, 5(%rdi)
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE4-NEXT: testb $64, %al
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; SSE4-NEXT: je LBB15_14
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE4-NEXT: LBB15_13: ## %cond.store11
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; SSE4-NEXT: pextrb $6, %xmm1, 6(%rdi)
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE4-NEXT: testb $-128, %al
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; SSE4-NEXT: je LBB15_16
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE4-NEXT: LBB15_15: ## %cond.store13
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; SSE4-NEXT: pextrb $7, %xmm1, 7(%rdi)
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE4-NEXT: testl $256, %eax ## imm = 0x100
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; SSE4-NEXT: je LBB15_18
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE4-NEXT: LBB15_17: ## %cond.store15
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; SSE4-NEXT: pextrb $8, %xmm1, 8(%rdi)
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE4-NEXT: testl $512, %eax ## imm = 0x200
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; SSE4-NEXT: je LBB15_20
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE4-NEXT: LBB15_19: ## %cond.store17
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; SSE4-NEXT: pextrb $9, %xmm1, 9(%rdi)
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE4-NEXT: testl $1024, %eax ## imm = 0x400
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; SSE4-NEXT: je LBB15_22
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE4-NEXT: LBB15_21: ## %cond.store19
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; SSE4-NEXT: pextrb $10, %xmm1, 10(%rdi)
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE4-NEXT: testl $2048, %eax ## imm = 0x800
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; SSE4-NEXT: je LBB15_24
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE4-NEXT: LBB15_23: ## %cond.store21
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; SSE4-NEXT: pextrb $11, %xmm1, 11(%rdi)
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE4-NEXT: testl $4096, %eax ## imm = 0x1000
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; SSE4-NEXT: je LBB15_26
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE4-NEXT: LBB15_25: ## %cond.store23
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; SSE4-NEXT: pextrb $12, %xmm1, 12(%rdi)
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE4-NEXT: testl $8192, %eax ## imm = 0x2000
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; SSE4-NEXT: je LBB15_28
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE4-NEXT: LBB15_27: ## %cond.store25
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; SSE4-NEXT: pextrb $13, %xmm1, 13(%rdi)
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE4-NEXT: testl $16384, %eax ## imm = 0x4000
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; SSE4-NEXT: je LBB15_30
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE4-NEXT: LBB15_29: ## %cond.store27
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; SSE4-NEXT: pextrb $14, %xmm1, 14(%rdi)
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE4-NEXT: testl $32768, %eax ## imm = 0x8000
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; SSE4-NEXT: je LBB15_32
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE4-NEXT: LBB15_31: ## %cond.store29
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; SSE4-NEXT: pextrb $15, %xmm1, 15(%rdi)
; SSE4-NEXT: retq
;
; AVX1OR2-LABEL: store_v16i8_v16i8:
; AVX1OR2: ## %bb.0:
; AVX1OR2-NEXT: vpxor %xmm2, %xmm2, %xmm2
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX1OR2-NEXT: vpcmpeqb %xmm2, %xmm0, %xmm0
; AVX1OR2-NEXT: vpmovmskb %xmm0, %eax
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; AVX1OR2-NEXT: testb $1, %al
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX1OR2-NEXT: jne LBB15_1
; AVX1OR2-NEXT: ## %bb.2: ## %else
; AVX1OR2-NEXT: testb $2, %al
; AVX1OR2-NEXT: jne LBB15_3
; AVX1OR2-NEXT: LBB15_4: ## %else2
; AVX1OR2-NEXT: testb $4, %al
; AVX1OR2-NEXT: jne LBB15_5
; AVX1OR2-NEXT: LBB15_6: ## %else4
; AVX1OR2-NEXT: testb $8, %al
; AVX1OR2-NEXT: jne LBB15_7
; AVX1OR2-NEXT: LBB15_8: ## %else6
; AVX1OR2-NEXT: testb $16, %al
; AVX1OR2-NEXT: jne LBB15_9
; AVX1OR2-NEXT: LBB15_10: ## %else8
; AVX1OR2-NEXT: testb $32, %al
; AVX1OR2-NEXT: jne LBB15_11
; AVX1OR2-NEXT: LBB15_12: ## %else10
; AVX1OR2-NEXT: testb $64, %al
; AVX1OR2-NEXT: jne LBB15_13
; AVX1OR2-NEXT: LBB15_14: ## %else12
; AVX1OR2-NEXT: testb $-128, %al
; AVX1OR2-NEXT: jne LBB15_15
; AVX1OR2-NEXT: LBB15_16: ## %else14
; AVX1OR2-NEXT: testl $256, %eax ## imm = 0x100
; AVX1OR2-NEXT: jne LBB15_17
; AVX1OR2-NEXT: LBB15_18: ## %else16
; AVX1OR2-NEXT: testl $512, %eax ## imm = 0x200
; AVX1OR2-NEXT: jne LBB15_19
; AVX1OR2-NEXT: LBB15_20: ## %else18
; AVX1OR2-NEXT: testl $1024, %eax ## imm = 0x400
; AVX1OR2-NEXT: jne LBB15_21
; AVX1OR2-NEXT: LBB15_22: ## %else20
; AVX1OR2-NEXT: testl $2048, %eax ## imm = 0x800
; AVX1OR2-NEXT: jne LBB15_23
; AVX1OR2-NEXT: LBB15_24: ## %else22
; AVX1OR2-NEXT: testl $4096, %eax ## imm = 0x1000
; AVX1OR2-NEXT: jne LBB15_25
; AVX1OR2-NEXT: LBB15_26: ## %else24
; AVX1OR2-NEXT: testl $8192, %eax ## imm = 0x2000
; AVX1OR2-NEXT: jne LBB15_27
; AVX1OR2-NEXT: LBB15_28: ## %else26
; AVX1OR2-NEXT: testl $16384, %eax ## imm = 0x4000
; AVX1OR2-NEXT: jne LBB15_29
; AVX1OR2-NEXT: LBB15_30: ## %else28
; AVX1OR2-NEXT: testl $32768, %eax ## imm = 0x8000
; AVX1OR2-NEXT: jne LBB15_31
; AVX1OR2-NEXT: LBB15_32: ## %else30
; AVX1OR2-NEXT: retq
; AVX1OR2-NEXT: LBB15_1: ## %cond.store
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; AVX1OR2-NEXT: vpextrb $0, %xmm1, (%rdi)
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX1OR2-NEXT: testb $2, %al
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; AVX1OR2-NEXT: je LBB15_4
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX1OR2-NEXT: LBB15_3: ## %cond.store1
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; AVX1OR2-NEXT: vpextrb $1, %xmm1, 1(%rdi)
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX1OR2-NEXT: testb $4, %al
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; AVX1OR2-NEXT: je LBB15_6
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX1OR2-NEXT: LBB15_5: ## %cond.store3
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; AVX1OR2-NEXT: vpextrb $2, %xmm1, 2(%rdi)
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX1OR2-NEXT: testb $8, %al
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; AVX1OR2-NEXT: je LBB15_8
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX1OR2-NEXT: LBB15_7: ## %cond.store5
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; AVX1OR2-NEXT: vpextrb $3, %xmm1, 3(%rdi)
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX1OR2-NEXT: testb $16, %al
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; AVX1OR2-NEXT: je LBB15_10
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX1OR2-NEXT: LBB15_9: ## %cond.store7
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; AVX1OR2-NEXT: vpextrb $4, %xmm1, 4(%rdi)
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX1OR2-NEXT: testb $32, %al
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; AVX1OR2-NEXT: je LBB15_12
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX1OR2-NEXT: LBB15_11: ## %cond.store9
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; AVX1OR2-NEXT: vpextrb $5, %xmm1, 5(%rdi)
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX1OR2-NEXT: testb $64, %al
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; AVX1OR2-NEXT: je LBB15_14
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX1OR2-NEXT: LBB15_13: ## %cond.store11
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; AVX1OR2-NEXT: vpextrb $6, %xmm1, 6(%rdi)
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX1OR2-NEXT: testb $-128, %al
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; AVX1OR2-NEXT: je LBB15_16
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX1OR2-NEXT: LBB15_15: ## %cond.store13
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; AVX1OR2-NEXT: vpextrb $7, %xmm1, 7(%rdi)
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX1OR2-NEXT: testl $256, %eax ## imm = 0x100
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; AVX1OR2-NEXT: je LBB15_18
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX1OR2-NEXT: LBB15_17: ## %cond.store15
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; AVX1OR2-NEXT: vpextrb $8, %xmm1, 8(%rdi)
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX1OR2-NEXT: testl $512, %eax ## imm = 0x200
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; AVX1OR2-NEXT: je LBB15_20
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX1OR2-NEXT: LBB15_19: ## %cond.store17
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; AVX1OR2-NEXT: vpextrb $9, %xmm1, 9(%rdi)
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX1OR2-NEXT: testl $1024, %eax ## imm = 0x400
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; AVX1OR2-NEXT: je LBB15_22
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX1OR2-NEXT: LBB15_21: ## %cond.store19
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; AVX1OR2-NEXT: vpextrb $10, %xmm1, 10(%rdi)
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX1OR2-NEXT: testl $2048, %eax ## imm = 0x800
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; AVX1OR2-NEXT: je LBB15_24
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX1OR2-NEXT: LBB15_23: ## %cond.store21
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; AVX1OR2-NEXT: vpextrb $11, %xmm1, 11(%rdi)
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX1OR2-NEXT: testl $4096, %eax ## imm = 0x1000
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; AVX1OR2-NEXT: je LBB15_26
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX1OR2-NEXT: LBB15_25: ## %cond.store23
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; AVX1OR2-NEXT: vpextrb $12, %xmm1, 12(%rdi)
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX1OR2-NEXT: testl $8192, %eax ## imm = 0x2000
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; AVX1OR2-NEXT: je LBB15_28
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX1OR2-NEXT: LBB15_27: ## %cond.store25
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; AVX1OR2-NEXT: vpextrb $13, %xmm1, 13(%rdi)
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX1OR2-NEXT: testl $16384, %eax ## imm = 0x4000
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; AVX1OR2-NEXT: je LBB15_30
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX1OR2-NEXT: LBB15_29: ## %cond.store27
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; AVX1OR2-NEXT: vpextrb $14, %xmm1, 14(%rdi)
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX1OR2-NEXT: testl $32768, %eax ## imm = 0x8000
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; AVX1OR2-NEXT: je LBB15_32
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX1OR2-NEXT: LBB15_31: ## %cond.store29
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; AVX1OR2-NEXT: vpextrb $15, %xmm1, 15(%rdi)
; AVX1OR2-NEXT: retq
;
; AVX512F-LABEL: store_v16i8_v16i8:
; AVX512F: ## %bb.0:
; AVX512F-NEXT: vpxor %xmm2, %xmm2, %xmm2
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX512F-NEXT: vpcmpeqb %xmm2, %xmm0, %xmm0
; AVX512F-NEXT: vpmovmskb %xmm0, %eax
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; AVX512F-NEXT: testb $1, %al
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX512F-NEXT: jne LBB15_1
; AVX512F-NEXT: ## %bb.2: ## %else
; AVX512F-NEXT: testb $2, %al
; AVX512F-NEXT: jne LBB15_3
; AVX512F-NEXT: LBB15_4: ## %else2
; AVX512F-NEXT: testb $4, %al
; AVX512F-NEXT: jne LBB15_5
; AVX512F-NEXT: LBB15_6: ## %else4
; AVX512F-NEXT: testb $8, %al
; AVX512F-NEXT: jne LBB15_7
; AVX512F-NEXT: LBB15_8: ## %else6
; AVX512F-NEXT: testb $16, %al
; AVX512F-NEXT: jne LBB15_9
; AVX512F-NEXT: LBB15_10: ## %else8
; AVX512F-NEXT: testb $32, %al
; AVX512F-NEXT: jne LBB15_11
; AVX512F-NEXT: LBB15_12: ## %else10
; AVX512F-NEXT: testb $64, %al
; AVX512F-NEXT: jne LBB15_13
; AVX512F-NEXT: LBB15_14: ## %else12
; AVX512F-NEXT: testb $-128, %al
; AVX512F-NEXT: jne LBB15_15
; AVX512F-NEXT: LBB15_16: ## %else14
; AVX512F-NEXT: testl $256, %eax ## imm = 0x100
; AVX512F-NEXT: jne LBB15_17
; AVX512F-NEXT: LBB15_18: ## %else16
; AVX512F-NEXT: testl $512, %eax ## imm = 0x200
; AVX512F-NEXT: jne LBB15_19
; AVX512F-NEXT: LBB15_20: ## %else18
; AVX512F-NEXT: testl $1024, %eax ## imm = 0x400
; AVX512F-NEXT: jne LBB15_21
; AVX512F-NEXT: LBB15_22: ## %else20
; AVX512F-NEXT: testl $2048, %eax ## imm = 0x800
; AVX512F-NEXT: jne LBB15_23
; AVX512F-NEXT: LBB15_24: ## %else22
; AVX512F-NEXT: testl $4096, %eax ## imm = 0x1000
; AVX512F-NEXT: jne LBB15_25
; AVX512F-NEXT: LBB15_26: ## %else24
; AVX512F-NEXT: testl $8192, %eax ## imm = 0x2000
; AVX512F-NEXT: jne LBB15_27
; AVX512F-NEXT: LBB15_28: ## %else26
; AVX512F-NEXT: testl $16384, %eax ## imm = 0x4000
; AVX512F-NEXT: jne LBB15_29
; AVX512F-NEXT: LBB15_30: ## %else28
; AVX512F-NEXT: testl $32768, %eax ## imm = 0x8000
; AVX512F-NEXT: jne LBB15_31
; AVX512F-NEXT: LBB15_32: ## %else30
; AVX512F-NEXT: retq
; AVX512F-NEXT: LBB15_1: ## %cond.store
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; AVX512F-NEXT: vpextrb $0, %xmm1, (%rdi)
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX512F-NEXT: testb $2, %al
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; AVX512F-NEXT: je LBB15_4
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX512F-NEXT: LBB15_3: ## %cond.store1
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; AVX512F-NEXT: vpextrb $1, %xmm1, 1(%rdi)
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX512F-NEXT: testb $4, %al
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; AVX512F-NEXT: je LBB15_6
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX512F-NEXT: LBB15_5: ## %cond.store3
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; AVX512F-NEXT: vpextrb $2, %xmm1, 2(%rdi)
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX512F-NEXT: testb $8, %al
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; AVX512F-NEXT: je LBB15_8
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX512F-NEXT: LBB15_7: ## %cond.store5
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; AVX512F-NEXT: vpextrb $3, %xmm1, 3(%rdi)
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX512F-NEXT: testb $16, %al
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; AVX512F-NEXT: je LBB15_10
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX512F-NEXT: LBB15_9: ## %cond.store7
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; AVX512F-NEXT: vpextrb $4, %xmm1, 4(%rdi)
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX512F-NEXT: testb $32, %al
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; AVX512F-NEXT: je LBB15_12
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX512F-NEXT: LBB15_11: ## %cond.store9
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; AVX512F-NEXT: vpextrb $5, %xmm1, 5(%rdi)
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX512F-NEXT: testb $64, %al
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; AVX512F-NEXT: je LBB15_14
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX512F-NEXT: LBB15_13: ## %cond.store11
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; AVX512F-NEXT: vpextrb $6, %xmm1, 6(%rdi)
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX512F-NEXT: testb $-128, %al
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; AVX512F-NEXT: je LBB15_16
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX512F-NEXT: LBB15_15: ## %cond.store13
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; AVX512F-NEXT: vpextrb $7, %xmm1, 7(%rdi)
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX512F-NEXT: testl $256, %eax ## imm = 0x100
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; AVX512F-NEXT: je LBB15_18
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX512F-NEXT: LBB15_17: ## %cond.store15
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; AVX512F-NEXT: vpextrb $8, %xmm1, 8(%rdi)
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX512F-NEXT: testl $512, %eax ## imm = 0x200
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; AVX512F-NEXT: je LBB15_20
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX512F-NEXT: LBB15_19: ## %cond.store17
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; AVX512F-NEXT: vpextrb $9, %xmm1, 9(%rdi)
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX512F-NEXT: testl $1024, %eax ## imm = 0x400
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; AVX512F-NEXT: je LBB15_22
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX512F-NEXT: LBB15_21: ## %cond.store19
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; AVX512F-NEXT: vpextrb $10, %xmm1, 10(%rdi)
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX512F-NEXT: testl $2048, %eax ## imm = 0x800
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; AVX512F-NEXT: je LBB15_24
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX512F-NEXT: LBB15_23: ## %cond.store21
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; AVX512F-NEXT: vpextrb $11, %xmm1, 11(%rdi)
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX512F-NEXT: testl $4096, %eax ## imm = 0x1000
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; AVX512F-NEXT: je LBB15_26
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX512F-NEXT: LBB15_25: ## %cond.store23
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; AVX512F-NEXT: vpextrb $12, %xmm1, 12(%rdi)
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX512F-NEXT: testl $8192, %eax ## imm = 0x2000
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; AVX512F-NEXT: je LBB15_28
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX512F-NEXT: LBB15_27: ## %cond.store25
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; AVX512F-NEXT: vpextrb $13, %xmm1, 13(%rdi)
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX512F-NEXT: testl $16384, %eax ## imm = 0x4000
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; AVX512F-NEXT: je LBB15_30
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX512F-NEXT: LBB15_29: ## %cond.store27
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; AVX512F-NEXT: vpextrb $14, %xmm1, 14(%rdi)
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX512F-NEXT: testl $32768, %eax ## imm = 0x8000
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; AVX512F-NEXT: je LBB15_32
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX512F-NEXT: LBB15_31: ## %cond.store29
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; AVX512F-NEXT: vpextrb $15, %xmm1, 15(%rdi)
; AVX512F-NEXT: retq
;
[X86][AVX] Add AVX512DQ coverage for masked memory ops tests (PR34584) llvm-svn: 359395
2019-04-28 18:02:34 +08:00
; AVX512VLDQ-LABEL: store_v16i8_v16i8:
; AVX512VLDQ: ## %bb.0:
; AVX512VLDQ-NEXT: vpxor %xmm2, %xmm2, %xmm2
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX512VLDQ-NEXT: vpcmpeqb %xmm2, %xmm0, %xmm0
; AVX512VLDQ-NEXT: vpmovmskb %xmm0, %eax
[X86][AVX] Add AVX512DQ coverage for masked memory ops tests (PR34584) llvm-svn: 359395
2019-04-28 18:02:34 +08:00
; AVX512VLDQ-NEXT: testb $1, %al
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX512VLDQ-NEXT: jne LBB15_1
; AVX512VLDQ-NEXT: ## %bb.2: ## %else
; AVX512VLDQ-NEXT: testb $2, %al
; AVX512VLDQ-NEXT: jne LBB15_3
; AVX512VLDQ-NEXT: LBB15_4: ## %else2
; AVX512VLDQ-NEXT: testb $4, %al
; AVX512VLDQ-NEXT: jne LBB15_5
; AVX512VLDQ-NEXT: LBB15_6: ## %else4
; AVX512VLDQ-NEXT: testb $8, %al
; AVX512VLDQ-NEXT: jne LBB15_7
; AVX512VLDQ-NEXT: LBB15_8: ## %else6
; AVX512VLDQ-NEXT: testb $16, %al
; AVX512VLDQ-NEXT: jne LBB15_9
; AVX512VLDQ-NEXT: LBB15_10: ## %else8
; AVX512VLDQ-NEXT: testb $32, %al
; AVX512VLDQ-NEXT: jne LBB15_11
; AVX512VLDQ-NEXT: LBB15_12: ## %else10
; AVX512VLDQ-NEXT: testb $64, %al
; AVX512VLDQ-NEXT: jne LBB15_13
; AVX512VLDQ-NEXT: LBB15_14: ## %else12
; AVX512VLDQ-NEXT: testb $-128, %al
; AVX512VLDQ-NEXT: jne LBB15_15
; AVX512VLDQ-NEXT: LBB15_16: ## %else14
; AVX512VLDQ-NEXT: testl $256, %eax ## imm = 0x100
; AVX512VLDQ-NEXT: jne LBB15_17
; AVX512VLDQ-NEXT: LBB15_18: ## %else16
; AVX512VLDQ-NEXT: testl $512, %eax ## imm = 0x200
; AVX512VLDQ-NEXT: jne LBB15_19
; AVX512VLDQ-NEXT: LBB15_20: ## %else18
; AVX512VLDQ-NEXT: testl $1024, %eax ## imm = 0x400
; AVX512VLDQ-NEXT: jne LBB15_21
; AVX512VLDQ-NEXT: LBB15_22: ## %else20
; AVX512VLDQ-NEXT: testl $2048, %eax ## imm = 0x800
; AVX512VLDQ-NEXT: jne LBB15_23
; AVX512VLDQ-NEXT: LBB15_24: ## %else22
; AVX512VLDQ-NEXT: testl $4096, %eax ## imm = 0x1000
; AVX512VLDQ-NEXT: jne LBB15_25
; AVX512VLDQ-NEXT: LBB15_26: ## %else24
; AVX512VLDQ-NEXT: testl $8192, %eax ## imm = 0x2000
; AVX512VLDQ-NEXT: jne LBB15_27
; AVX512VLDQ-NEXT: LBB15_28: ## %else26
; AVX512VLDQ-NEXT: testl $16384, %eax ## imm = 0x4000
; AVX512VLDQ-NEXT: jne LBB15_29
; AVX512VLDQ-NEXT: LBB15_30: ## %else28
; AVX512VLDQ-NEXT: testl $32768, %eax ## imm = 0x8000
; AVX512VLDQ-NEXT: jne LBB15_31
; AVX512VLDQ-NEXT: LBB15_32: ## %else30
; AVX512VLDQ-NEXT: retq
; AVX512VLDQ-NEXT: LBB15_1: ## %cond.store
[X86][AVX] Add AVX512DQ coverage for masked memory ops tests (PR34584) llvm-svn: 359395
2019-04-28 18:02:34 +08:00
; AVX512VLDQ-NEXT: vpextrb $0, %xmm1, (%rdi)
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX512VLDQ-NEXT: testb $2, %al
[X86][AVX] Add AVX512DQ coverage for masked memory ops tests (PR34584) llvm-svn: 359395
2019-04-28 18:02:34 +08:00
; AVX512VLDQ-NEXT: je LBB15_4
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX512VLDQ-NEXT: LBB15_3: ## %cond.store1
[X86][AVX] Add AVX512DQ coverage for masked memory ops tests (PR34584) llvm-svn: 359395
2019-04-28 18:02:34 +08:00
; AVX512VLDQ-NEXT: vpextrb $1, %xmm1, 1(%rdi)
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX512VLDQ-NEXT: testb $4, %al
[X86][AVX] Add AVX512DQ coverage for masked memory ops tests (PR34584) llvm-svn: 359395
2019-04-28 18:02:34 +08:00
; AVX512VLDQ-NEXT: je LBB15_6
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX512VLDQ-NEXT: LBB15_5: ## %cond.store3
[X86][AVX] Add AVX512DQ coverage for masked memory ops tests (PR34584) llvm-svn: 359395
2019-04-28 18:02:34 +08:00
; AVX512VLDQ-NEXT: vpextrb $2, %xmm1, 2(%rdi)
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX512VLDQ-NEXT: testb $8, %al
[X86][AVX] Add AVX512DQ coverage for masked memory ops tests (PR34584) llvm-svn: 359395
2019-04-28 18:02:34 +08:00
; AVX512VLDQ-NEXT: je LBB15_8
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX512VLDQ-NEXT: LBB15_7: ## %cond.store5
[X86][AVX] Add AVX512DQ coverage for masked memory ops tests (PR34584) llvm-svn: 359395
2019-04-28 18:02:34 +08:00
; AVX512VLDQ-NEXT: vpextrb $3, %xmm1, 3(%rdi)
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX512VLDQ-NEXT: testb $16, %al
[X86][AVX] Add AVX512DQ coverage for masked memory ops tests (PR34584) llvm-svn: 359395
2019-04-28 18:02:34 +08:00
; AVX512VLDQ-NEXT: je LBB15_10
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX512VLDQ-NEXT: LBB15_9: ## %cond.store7
[X86][AVX] Add AVX512DQ coverage for masked memory ops tests (PR34584) llvm-svn: 359395
2019-04-28 18:02:34 +08:00
; AVX512VLDQ-NEXT: vpextrb $4, %xmm1, 4(%rdi)
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX512VLDQ-NEXT: testb $32, %al
[X86][AVX] Add AVX512DQ coverage for masked memory ops tests (PR34584) llvm-svn: 359395
2019-04-28 18:02:34 +08:00
; AVX512VLDQ-NEXT: je LBB15_12
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX512VLDQ-NEXT: LBB15_11: ## %cond.store9
[X86][AVX] Add AVX512DQ coverage for masked memory ops tests (PR34584) llvm-svn: 359395
2019-04-28 18:02:34 +08:00
; AVX512VLDQ-NEXT: vpextrb $5, %xmm1, 5(%rdi)
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX512VLDQ-NEXT: testb $64, %al
[X86][AVX] Add AVX512DQ coverage for masked memory ops tests (PR34584) llvm-svn: 359395
2019-04-28 18:02:34 +08:00
; AVX512VLDQ-NEXT: je LBB15_14
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX512VLDQ-NEXT: LBB15_13: ## %cond.store11
[X86][AVX] Add AVX512DQ coverage for masked memory ops tests (PR34584) llvm-svn: 359395
2019-04-28 18:02:34 +08:00
; AVX512VLDQ-NEXT: vpextrb $6, %xmm1, 6(%rdi)
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX512VLDQ-NEXT: testb $-128, %al
[X86][AVX] Add AVX512DQ coverage for masked memory ops tests (PR34584) llvm-svn: 359395
2019-04-28 18:02:34 +08:00
; AVX512VLDQ-NEXT: je LBB15_16
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX512VLDQ-NEXT: LBB15_15: ## %cond.store13
; AVX512VLDQ-NEXT: vpextrb $7, %xmm1, 7(%rdi)
; AVX512VLDQ-NEXT: testl $256, %eax ## imm = 0x100
[X86][AVX] Add AVX512DQ coverage for masked memory ops tests (PR34584) llvm-svn: 359395
2019-04-28 18:02:34 +08:00
; AVX512VLDQ-NEXT: je LBB15_18
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX512VLDQ-NEXT: LBB15_17: ## %cond.store15
[X86][AVX] Add AVX512DQ coverage for masked memory ops tests (PR34584) llvm-svn: 359395
2019-04-28 18:02:34 +08:00
; AVX512VLDQ-NEXT: vpextrb $8, %xmm1, 8(%rdi)
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX512VLDQ-NEXT: testl $512, %eax ## imm = 0x200
[X86][AVX] Add AVX512DQ coverage for masked memory ops tests (PR34584) llvm-svn: 359395
2019-04-28 18:02:34 +08:00
; AVX512VLDQ-NEXT: je LBB15_20
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX512VLDQ-NEXT: LBB15_19: ## %cond.store17
[X86][AVX] Add AVX512DQ coverage for masked memory ops tests (PR34584) llvm-svn: 359395
2019-04-28 18:02:34 +08:00
; AVX512VLDQ-NEXT: vpextrb $9, %xmm1, 9(%rdi)
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX512VLDQ-NEXT: testl $1024, %eax ## imm = 0x400
[X86][AVX] Add AVX512DQ coverage for masked memory ops tests (PR34584) llvm-svn: 359395
2019-04-28 18:02:34 +08:00
; AVX512VLDQ-NEXT: je LBB15_22
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX512VLDQ-NEXT: LBB15_21: ## %cond.store19
[X86][AVX] Add AVX512DQ coverage for masked memory ops tests (PR34584) llvm-svn: 359395
2019-04-28 18:02:34 +08:00
; AVX512VLDQ-NEXT: vpextrb $10, %xmm1, 10(%rdi)
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX512VLDQ-NEXT: testl $2048, %eax ## imm = 0x800
[X86][AVX] Add AVX512DQ coverage for masked memory ops tests (PR34584) llvm-svn: 359395
2019-04-28 18:02:34 +08:00
; AVX512VLDQ-NEXT: je LBB15_24
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX512VLDQ-NEXT: LBB15_23: ## %cond.store21
[X86][AVX] Add AVX512DQ coverage for masked memory ops tests (PR34584) llvm-svn: 359395
2019-04-28 18:02:34 +08:00
; AVX512VLDQ-NEXT: vpextrb $11, %xmm1, 11(%rdi)
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX512VLDQ-NEXT: testl $4096, %eax ## imm = 0x1000
[X86][AVX] Add AVX512DQ coverage for masked memory ops tests (PR34584) llvm-svn: 359395
2019-04-28 18:02:34 +08:00
; AVX512VLDQ-NEXT: je LBB15_26
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX512VLDQ-NEXT: LBB15_25: ## %cond.store23
[X86][AVX] Add AVX512DQ coverage for masked memory ops tests (PR34584) llvm-svn: 359395
2019-04-28 18:02:34 +08:00
; AVX512VLDQ-NEXT: vpextrb $12, %xmm1, 12(%rdi)
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX512VLDQ-NEXT: testl $8192, %eax ## imm = 0x2000
[X86][AVX] Add AVX512DQ coverage for masked memory ops tests (PR34584) llvm-svn: 359395
2019-04-28 18:02:34 +08:00
; AVX512VLDQ-NEXT: je LBB15_28
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX512VLDQ-NEXT: LBB15_27: ## %cond.store25
[X86][AVX] Add AVX512DQ coverage for masked memory ops tests (PR34584) llvm-svn: 359395
2019-04-28 18:02:34 +08:00
; AVX512VLDQ-NEXT: vpextrb $13, %xmm1, 13(%rdi)
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX512VLDQ-NEXT: testl $16384, %eax ## imm = 0x4000
[X86][AVX] Add AVX512DQ coverage for masked memory ops tests (PR34584) llvm-svn: 359395
2019-04-28 18:02:34 +08:00
; AVX512VLDQ-NEXT: je LBB15_30
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX512VLDQ-NEXT: LBB15_29: ## %cond.store27
[X86][AVX] Add AVX512DQ coverage for masked memory ops tests (PR34584) llvm-svn: 359395
2019-04-28 18:02:34 +08:00
; AVX512VLDQ-NEXT: vpextrb $14, %xmm1, 14(%rdi)
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX512VLDQ-NEXT: testl $32768, %eax ## imm = 0x8000
[X86][AVX] Add AVX512DQ coverage for masked memory ops tests (PR34584) llvm-svn: 359395
2019-04-28 18:02:34 +08:00
; AVX512VLDQ-NEXT: je LBB15_32
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX512VLDQ-NEXT: LBB15_31: ## %cond.store29
[X86][AVX] Add AVX512DQ coverage for masked memory ops tests (PR34584) llvm-svn: 359395
2019-04-28 18:02:34 +08:00
; AVX512VLDQ-NEXT: vpextrb $15, %xmm1, 15(%rdi)
; AVX512VLDQ-NEXT: retq
;
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; AVX512VLBW-LABEL: store_v16i8_v16i8:
; AVX512VLBW: ## %bb.0:
; AVX512VLBW-NEXT: vptestnmb %xmm0, %xmm0, %k1
; AVX512VLBW-NEXT: vmovdqu8 %xmm1, (%rdi) {%k1}
; AVX512VLBW-NEXT: retq
%mask = icmp eq <16 x i8> %trigger, zeroinitializer
call void @llvm.masked.store.v16i8.p0v16i8(<16 x i8> %val, <16 x i8>* %addr, i32 4, <16 x i1> %mask)
ret void
}
define void @store_v32i8_v32i8(<32 x i8> %trigger, <32 x i8>* %addr, <32 x i8> %val) {
; SSE2-LABEL: store_v32i8_v32i8:
; SSE2: ## %bb.0:
; SSE2-NEXT: pxor %xmm4, %xmm4
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE2-NEXT: pcmpeqb %xmm4, %xmm0
; SSE2-NEXT: pmovmskb %xmm0, %ecx
; SSE2-NEXT: pcmpeqb %xmm4, %xmm1
; SSE2-NEXT: pmovmskb %xmm1, %eax
; SSE2-NEXT: shll $16, %eax
; SSE2-NEXT: orl %ecx, %eax
; SSE2-NEXT: testb $1, %al
; SSE2-NEXT: movd %xmm2, %ecx
; SSE2-NEXT: jne LBB16_1
; SSE2-NEXT: ## %bb.2: ## %else
; SSE2-NEXT: testb $2, %al
; SSE2-NEXT: jne LBB16_3
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; SSE2-NEXT: LBB16_4: ## %else2
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE2-NEXT: testb $4, %al
; SSE2-NEXT: jne LBB16_5
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; SSE2-NEXT: LBB16_6: ## %else4
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE2-NEXT: testb $8, %al
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; SSE2-NEXT: je LBB16_8
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE2-NEXT: LBB16_7: ## %cond.store5
; SSE2-NEXT: shrl $24, %ecx
; SSE2-NEXT: movb %cl, 3(%rdi)
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; SSE2-NEXT: LBB16_8: ## %else6
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE2-NEXT: testb $16, %al
; SSE2-NEXT: pextrw $2, %xmm2, %ecx
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; SSE2-NEXT: je LBB16_10
; SSE2-NEXT: ## %bb.9: ## %cond.store7
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE2-NEXT: movb %cl, 4(%rdi)
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; SSE2-NEXT: LBB16_10: ## %else8
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE2-NEXT: testb $32, %al
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; SSE2-NEXT: je LBB16_12
; SSE2-NEXT: ## %bb.11: ## %cond.store9
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE2-NEXT: movb %ch, 5(%rdi)
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; SSE2-NEXT: LBB16_12: ## %else10
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE2-NEXT: testb $64, %al
; SSE2-NEXT: pextrw $3, %xmm2, %ecx
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; SSE2-NEXT: je LBB16_14
; SSE2-NEXT: ## %bb.13: ## %cond.store11
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE2-NEXT: movb %cl, 6(%rdi)
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; SSE2-NEXT: LBB16_14: ## %else12
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE2-NEXT: testb $-128, %al
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; SSE2-NEXT: je LBB16_16
; SSE2-NEXT: ## %bb.15: ## %cond.store13
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE2-NEXT: movb %ch, 7(%rdi)
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; SSE2-NEXT: LBB16_16: ## %else14
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE2-NEXT: testl $256, %eax ## imm = 0x100
; SSE2-NEXT: pextrw $4, %xmm2, %ecx
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; SSE2-NEXT: je LBB16_18
; SSE2-NEXT: ## %bb.17: ## %cond.store15
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE2-NEXT: movb %cl, 8(%rdi)
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; SSE2-NEXT: LBB16_18: ## %else16
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE2-NEXT: testl $512, %eax ## imm = 0x200
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; SSE2-NEXT: je LBB16_20
; SSE2-NEXT: ## %bb.19: ## %cond.store17
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE2-NEXT: movb %ch, 9(%rdi)
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; SSE2-NEXT: LBB16_20: ## %else18
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE2-NEXT: testl $1024, %eax ## imm = 0x400
; SSE2-NEXT: pextrw $5, %xmm2, %ecx
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; SSE2-NEXT: je LBB16_22
; SSE2-NEXT: ## %bb.21: ## %cond.store19
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE2-NEXT: movb %cl, 10(%rdi)
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; SSE2-NEXT: LBB16_22: ## %else20
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE2-NEXT: testl $2048, %eax ## imm = 0x800
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; SSE2-NEXT: je LBB16_24
; SSE2-NEXT: ## %bb.23: ## %cond.store21
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE2-NEXT: movb %ch, 11(%rdi)
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; SSE2-NEXT: LBB16_24: ## %else22
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE2-NEXT: testl $4096, %eax ## imm = 0x1000
; SSE2-NEXT: pextrw $6, %xmm2, %ecx
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; SSE2-NEXT: je LBB16_26
; SSE2-NEXT: ## %bb.25: ## %cond.store23
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE2-NEXT: movb %cl, 12(%rdi)
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; SSE2-NEXT: LBB16_26: ## %else24
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE2-NEXT: testl $8192, %eax ## imm = 0x2000
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; SSE2-NEXT: je LBB16_28
; SSE2-NEXT: ## %bb.27: ## %cond.store25
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE2-NEXT: movb %ch, 13(%rdi)
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; SSE2-NEXT: LBB16_28: ## %else26
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE2-NEXT: testl $16384, %eax ## imm = 0x4000
; SSE2-NEXT: pextrw $7, %xmm2, %ecx
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; SSE2-NEXT: je LBB16_30
; SSE2-NEXT: ## %bb.29: ## %cond.store27
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE2-NEXT: movb %cl, 14(%rdi)
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; SSE2-NEXT: LBB16_30: ## %else28
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE2-NEXT: testl $32768, %eax ## imm = 0x8000
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; SSE2-NEXT: je LBB16_32
; SSE2-NEXT: ## %bb.31: ## %cond.store29
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE2-NEXT: movb %ch, 15(%rdi)
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; SSE2-NEXT: LBB16_32: ## %else30
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE2-NEXT: testl $65536, %eax ## imm = 0x10000
; SSE2-NEXT: movd %xmm3, %ecx
; SSE2-NEXT: jne LBB16_33
; SSE2-NEXT: ## %bb.34: ## %else32
; SSE2-NEXT: testl $131072, %eax ## imm = 0x20000
; SSE2-NEXT: jne LBB16_35
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; SSE2-NEXT: LBB16_36: ## %else34
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE2-NEXT: testl $262144, %eax ## imm = 0x40000
; SSE2-NEXT: jne LBB16_37
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; SSE2-NEXT: LBB16_38: ## %else36
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE2-NEXT: testl $524288, %eax ## imm = 0x80000
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; SSE2-NEXT: je LBB16_40
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE2-NEXT: LBB16_39: ## %cond.store37
; SSE2-NEXT: shrl $24, %ecx
; SSE2-NEXT: movb %cl, 19(%rdi)
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; SSE2-NEXT: LBB16_40: ## %else38
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE2-NEXT: testl $1048576, %eax ## imm = 0x100000
; SSE2-NEXT: pextrw $2, %xmm3, %ecx
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; SSE2-NEXT: je LBB16_42
; SSE2-NEXT: ## %bb.41: ## %cond.store39
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE2-NEXT: movb %cl, 20(%rdi)
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; SSE2-NEXT: LBB16_42: ## %else40
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE2-NEXT: testl $2097152, %eax ## imm = 0x200000
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; SSE2-NEXT: je LBB16_44
; SSE2-NEXT: ## %bb.43: ## %cond.store41
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE2-NEXT: movb %ch, 21(%rdi)
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; SSE2-NEXT: LBB16_44: ## %else42
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE2-NEXT: testl $4194304, %eax ## imm = 0x400000
; SSE2-NEXT: pextrw $3, %xmm3, %ecx
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; SSE2-NEXT: je LBB16_46
; SSE2-NEXT: ## %bb.45: ## %cond.store43
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE2-NEXT: movb %cl, 22(%rdi)
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; SSE2-NEXT: LBB16_46: ## %else44
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE2-NEXT: testl $8388608, %eax ## imm = 0x800000
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; SSE2-NEXT: je LBB16_48
; SSE2-NEXT: ## %bb.47: ## %cond.store45
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE2-NEXT: movb %ch, 23(%rdi)
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; SSE2-NEXT: LBB16_48: ## %else46
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE2-NEXT: testl $16777216, %eax ## imm = 0x1000000
; SSE2-NEXT: pextrw $4, %xmm3, %ecx
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; SSE2-NEXT: je LBB16_50
; SSE2-NEXT: ## %bb.49: ## %cond.store47
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE2-NEXT: movb %cl, 24(%rdi)
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; SSE2-NEXT: LBB16_50: ## %else48
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE2-NEXT: testl $33554432, %eax ## imm = 0x2000000
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; SSE2-NEXT: je LBB16_52
; SSE2-NEXT: ## %bb.51: ## %cond.store49
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE2-NEXT: movb %ch, 25(%rdi)
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; SSE2-NEXT: LBB16_52: ## %else50
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE2-NEXT: testl $67108864, %eax ## imm = 0x4000000
; SSE2-NEXT: pextrw $5, %xmm3, %ecx
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; SSE2-NEXT: je LBB16_54
; SSE2-NEXT: ## %bb.53: ## %cond.store51
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE2-NEXT: movb %cl, 26(%rdi)
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; SSE2-NEXT: LBB16_54: ## %else52
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE2-NEXT: testl $134217728, %eax ## imm = 0x8000000
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; SSE2-NEXT: je LBB16_56
; SSE2-NEXT: ## %bb.55: ## %cond.store53
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE2-NEXT: movb %ch, 27(%rdi)
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; SSE2-NEXT: LBB16_56: ## %else54
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE2-NEXT: testl $268435456, %eax ## imm = 0x10000000
; SSE2-NEXT: pextrw $6, %xmm3, %ecx
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; SSE2-NEXT: je LBB16_58
; SSE2-NEXT: ## %bb.57: ## %cond.store55
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE2-NEXT: movb %cl, 28(%rdi)
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; SSE2-NEXT: LBB16_58: ## %else56
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE2-NEXT: testl $536870912, %eax ## imm = 0x20000000
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; SSE2-NEXT: je LBB16_60
; SSE2-NEXT: ## %bb.59: ## %cond.store57
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE2-NEXT: movb %ch, 29(%rdi)
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; SSE2-NEXT: LBB16_60: ## %else58
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE2-NEXT: testl $1073741824, %eax ## imm = 0x40000000
; SSE2-NEXT: pextrw $7, %xmm3, %ecx
; SSE2-NEXT: jne LBB16_61
; SSE2-NEXT: ## %bb.62: ## %else60
; SSE2-NEXT: testl $-2147483648, %eax ## imm = 0x80000000
; SSE2-NEXT: jne LBB16_63
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; SSE2-NEXT: LBB16_64: ## %else62
; SSE2-NEXT: retq
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE2-NEXT: LBB16_1: ## %cond.store
; SSE2-NEXT: movb %cl, (%rdi)
; SSE2-NEXT: testb $2, %al
; SSE2-NEXT: je LBB16_4
; SSE2-NEXT: LBB16_3: ## %cond.store1
; SSE2-NEXT: movb %ch, 1(%rdi)
; SSE2-NEXT: testb $4, %al
; SSE2-NEXT: je LBB16_6
; SSE2-NEXT: LBB16_5: ## %cond.store3
; SSE2-NEXT: movl %ecx, %edx
; SSE2-NEXT: shrl $16, %edx
; SSE2-NEXT: movb %dl, 2(%rdi)
; SSE2-NEXT: testb $8, %al
; SSE2-NEXT: jne LBB16_7
; SSE2-NEXT: jmp LBB16_8
; SSE2-NEXT: LBB16_33: ## %cond.store31
; SSE2-NEXT: movb %cl, 16(%rdi)
; SSE2-NEXT: testl $131072, %eax ## imm = 0x20000
; SSE2-NEXT: je LBB16_36
; SSE2-NEXT: LBB16_35: ## %cond.store33
; SSE2-NEXT: movb %ch, 17(%rdi)
; SSE2-NEXT: testl $262144, %eax ## imm = 0x40000
; SSE2-NEXT: je LBB16_38
; SSE2-NEXT: LBB16_37: ## %cond.store35
; SSE2-NEXT: movl %ecx, %edx
; SSE2-NEXT: shrl $16, %edx
; SSE2-NEXT: movb %dl, 18(%rdi)
; SSE2-NEXT: testl $524288, %eax ## imm = 0x80000
; SSE2-NEXT: jne LBB16_39
; SSE2-NEXT: jmp LBB16_40
; SSE2-NEXT: LBB16_61: ## %cond.store59
; SSE2-NEXT: movb %cl, 30(%rdi)
; SSE2-NEXT: testl $-2147483648, %eax ## imm = 0x80000000
; SSE2-NEXT: je LBB16_64
; SSE2-NEXT: LBB16_63: ## %cond.store61
; SSE2-NEXT: movb %ch, 31(%rdi)
; SSE2-NEXT: retq
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
;
; SSE4-LABEL: store_v32i8_v32i8:
; SSE4: ## %bb.0:
; SSE4-NEXT: pxor %xmm4, %xmm4
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE4-NEXT: pcmpeqb %xmm4, %xmm0
; SSE4-NEXT: pmovmskb %xmm0, %ecx
; SSE4-NEXT: pcmpeqb %xmm4, %xmm1
; SSE4-NEXT: pmovmskb %xmm1, %eax
; SSE4-NEXT: shll $16, %eax
; SSE4-NEXT: orl %ecx, %eax
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; SSE4-NEXT: testb $1, %al
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE4-NEXT: jne LBB16_1
; SSE4-NEXT: ## %bb.2: ## %else
; SSE4-NEXT: testb $2, %al
; SSE4-NEXT: jne LBB16_3
; SSE4-NEXT: LBB16_4: ## %else2
; SSE4-NEXT: testb $4, %al
; SSE4-NEXT: jne LBB16_5
; SSE4-NEXT: LBB16_6: ## %else4
; SSE4-NEXT: testb $8, %al
; SSE4-NEXT: jne LBB16_7
; SSE4-NEXT: LBB16_8: ## %else6
; SSE4-NEXT: testb $16, %al
; SSE4-NEXT: jne LBB16_9
; SSE4-NEXT: LBB16_10: ## %else8
; SSE4-NEXT: testb $32, %al
; SSE4-NEXT: jne LBB16_11
; SSE4-NEXT: LBB16_12: ## %else10
; SSE4-NEXT: testb $64, %al
; SSE4-NEXT: jne LBB16_13
; SSE4-NEXT: LBB16_14: ## %else12
; SSE4-NEXT: testb $-128, %al
; SSE4-NEXT: jne LBB16_15
; SSE4-NEXT: LBB16_16: ## %else14
; SSE4-NEXT: testl $256, %eax ## imm = 0x100
; SSE4-NEXT: jne LBB16_17
; SSE4-NEXT: LBB16_18: ## %else16
; SSE4-NEXT: testl $512, %eax ## imm = 0x200
; SSE4-NEXT: jne LBB16_19
; SSE4-NEXT: LBB16_20: ## %else18
; SSE4-NEXT: testl $1024, %eax ## imm = 0x400
; SSE4-NEXT: jne LBB16_21
; SSE4-NEXT: LBB16_22: ## %else20
; SSE4-NEXT: testl $2048, %eax ## imm = 0x800
; SSE4-NEXT: jne LBB16_23
; SSE4-NEXT: LBB16_24: ## %else22
; SSE4-NEXT: testl $4096, %eax ## imm = 0x1000
; SSE4-NEXT: jne LBB16_25
; SSE4-NEXT: LBB16_26: ## %else24
; SSE4-NEXT: testl $8192, %eax ## imm = 0x2000
; SSE4-NEXT: jne LBB16_27
; SSE4-NEXT: LBB16_28: ## %else26
; SSE4-NEXT: testl $16384, %eax ## imm = 0x4000
; SSE4-NEXT: jne LBB16_29
; SSE4-NEXT: LBB16_30: ## %else28
; SSE4-NEXT: testl $32768, %eax ## imm = 0x8000
; SSE4-NEXT: jne LBB16_31
; SSE4-NEXT: LBB16_32: ## %else30
; SSE4-NEXT: testl $65536, %eax ## imm = 0x10000
; SSE4-NEXT: jne LBB16_33
; SSE4-NEXT: LBB16_34: ## %else32
; SSE4-NEXT: testl $131072, %eax ## imm = 0x20000
; SSE4-NEXT: jne LBB16_35
; SSE4-NEXT: LBB16_36: ## %else34
; SSE4-NEXT: testl $262144, %eax ## imm = 0x40000
; SSE4-NEXT: jne LBB16_37
; SSE4-NEXT: LBB16_38: ## %else36
; SSE4-NEXT: testl $524288, %eax ## imm = 0x80000
; SSE4-NEXT: jne LBB16_39
; SSE4-NEXT: LBB16_40: ## %else38
; SSE4-NEXT: testl $1048576, %eax ## imm = 0x100000
; SSE4-NEXT: jne LBB16_41
; SSE4-NEXT: LBB16_42: ## %else40
; SSE4-NEXT: testl $2097152, %eax ## imm = 0x200000
; SSE4-NEXT: jne LBB16_43
; SSE4-NEXT: LBB16_44: ## %else42
; SSE4-NEXT: testl $4194304, %eax ## imm = 0x400000
; SSE4-NEXT: jne LBB16_45
; SSE4-NEXT: LBB16_46: ## %else44
; SSE4-NEXT: testl $8388608, %eax ## imm = 0x800000
; SSE4-NEXT: jne LBB16_47
; SSE4-NEXT: LBB16_48: ## %else46
; SSE4-NEXT: testl $16777216, %eax ## imm = 0x1000000
; SSE4-NEXT: jne LBB16_49
; SSE4-NEXT: LBB16_50: ## %else48
; SSE4-NEXT: testl $33554432, %eax ## imm = 0x2000000
; SSE4-NEXT: jne LBB16_51
; SSE4-NEXT: LBB16_52: ## %else50
; SSE4-NEXT: testl $67108864, %eax ## imm = 0x4000000
; SSE4-NEXT: jne LBB16_53
; SSE4-NEXT: LBB16_54: ## %else52
; SSE4-NEXT: testl $134217728, %eax ## imm = 0x8000000
; SSE4-NEXT: jne LBB16_55
; SSE4-NEXT: LBB16_56: ## %else54
; SSE4-NEXT: testl $268435456, %eax ## imm = 0x10000000
; SSE4-NEXT: jne LBB16_57
; SSE4-NEXT: LBB16_58: ## %else56
; SSE4-NEXT: testl $536870912, %eax ## imm = 0x20000000
; SSE4-NEXT: jne LBB16_59
; SSE4-NEXT: LBB16_60: ## %else58
; SSE4-NEXT: testl $1073741824, %eax ## imm = 0x40000000
; SSE4-NEXT: jne LBB16_61
; SSE4-NEXT: LBB16_62: ## %else60
; SSE4-NEXT: testl $-2147483648, %eax ## imm = 0x80000000
; SSE4-NEXT: jne LBB16_63
; SSE4-NEXT: LBB16_64: ## %else62
; SSE4-NEXT: retq
; SSE4-NEXT: LBB16_1: ## %cond.store
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; SSE4-NEXT: pextrb $0, %xmm2, (%rdi)
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE4-NEXT: testb $2, %al
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; SSE4-NEXT: je LBB16_4
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE4-NEXT: LBB16_3: ## %cond.store1
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; SSE4-NEXT: pextrb $1, %xmm2, 1(%rdi)
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE4-NEXT: testb $4, %al
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; SSE4-NEXT: je LBB16_6
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE4-NEXT: LBB16_5: ## %cond.store3
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; SSE4-NEXT: pextrb $2, %xmm2, 2(%rdi)
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE4-NEXT: testb $8, %al
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; SSE4-NEXT: je LBB16_8
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE4-NEXT: LBB16_7: ## %cond.store5
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; SSE4-NEXT: pextrb $3, %xmm2, 3(%rdi)
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE4-NEXT: testb $16, %al
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; SSE4-NEXT: je LBB16_10
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE4-NEXT: LBB16_9: ## %cond.store7
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; SSE4-NEXT: pextrb $4, %xmm2, 4(%rdi)
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE4-NEXT: testb $32, %al
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; SSE4-NEXT: je LBB16_12
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE4-NEXT: LBB16_11: ## %cond.store9
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; SSE4-NEXT: pextrb $5, %xmm2, 5(%rdi)
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE4-NEXT: testb $64, %al
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; SSE4-NEXT: je LBB16_14
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE4-NEXT: LBB16_13: ## %cond.store11
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; SSE4-NEXT: pextrb $6, %xmm2, 6(%rdi)
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE4-NEXT: testb $-128, %al
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; SSE4-NEXT: je LBB16_16
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE4-NEXT: LBB16_15: ## %cond.store13
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; SSE4-NEXT: pextrb $7, %xmm2, 7(%rdi)
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE4-NEXT: testl $256, %eax ## imm = 0x100
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; SSE4-NEXT: je LBB16_18
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE4-NEXT: LBB16_17: ## %cond.store15
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; SSE4-NEXT: pextrb $8, %xmm2, 8(%rdi)
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE4-NEXT: testl $512, %eax ## imm = 0x200
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; SSE4-NEXT: je LBB16_20
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE4-NEXT: LBB16_19: ## %cond.store17
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; SSE4-NEXT: pextrb $9, %xmm2, 9(%rdi)
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE4-NEXT: testl $1024, %eax ## imm = 0x400
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; SSE4-NEXT: je LBB16_22
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE4-NEXT: LBB16_21: ## %cond.store19
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; SSE4-NEXT: pextrb $10, %xmm2, 10(%rdi)
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE4-NEXT: testl $2048, %eax ## imm = 0x800
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; SSE4-NEXT: je LBB16_24
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE4-NEXT: LBB16_23: ## %cond.store21
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; SSE4-NEXT: pextrb $11, %xmm2, 11(%rdi)
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE4-NEXT: testl $4096, %eax ## imm = 0x1000
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; SSE4-NEXT: je LBB16_26
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE4-NEXT: LBB16_25: ## %cond.store23
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; SSE4-NEXT: pextrb $12, %xmm2, 12(%rdi)
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE4-NEXT: testl $8192, %eax ## imm = 0x2000
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; SSE4-NEXT: je LBB16_28
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE4-NEXT: LBB16_27: ## %cond.store25
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; SSE4-NEXT: pextrb $13, %xmm2, 13(%rdi)
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE4-NEXT: testl $16384, %eax ## imm = 0x4000
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; SSE4-NEXT: je LBB16_30
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE4-NEXT: LBB16_29: ## %cond.store27
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; SSE4-NEXT: pextrb $14, %xmm2, 14(%rdi)
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE4-NEXT: testl $32768, %eax ## imm = 0x8000
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; SSE4-NEXT: je LBB16_32
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE4-NEXT: LBB16_31: ## %cond.store29
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; SSE4-NEXT: pextrb $15, %xmm2, 15(%rdi)
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE4-NEXT: testl $65536, %eax ## imm = 0x10000
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; SSE4-NEXT: je LBB16_34
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE4-NEXT: LBB16_33: ## %cond.store31
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; SSE4-NEXT: pextrb $0, %xmm3, 16(%rdi)
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE4-NEXT: testl $131072, %eax ## imm = 0x20000
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; SSE4-NEXT: je LBB16_36
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE4-NEXT: LBB16_35: ## %cond.store33
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; SSE4-NEXT: pextrb $1, %xmm3, 17(%rdi)
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE4-NEXT: testl $262144, %eax ## imm = 0x40000
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; SSE4-NEXT: je LBB16_38
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE4-NEXT: LBB16_37: ## %cond.store35
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; SSE4-NEXT: pextrb $2, %xmm3, 18(%rdi)
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE4-NEXT: testl $524288, %eax ## imm = 0x80000
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; SSE4-NEXT: je LBB16_40
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE4-NEXT: LBB16_39: ## %cond.store37
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; SSE4-NEXT: pextrb $3, %xmm3, 19(%rdi)
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE4-NEXT: testl $1048576, %eax ## imm = 0x100000
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; SSE4-NEXT: je LBB16_42
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE4-NEXT: LBB16_41: ## %cond.store39
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; SSE4-NEXT: pextrb $4, %xmm3, 20(%rdi)
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE4-NEXT: testl $2097152, %eax ## imm = 0x200000
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; SSE4-NEXT: je LBB16_44
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE4-NEXT: LBB16_43: ## %cond.store41
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; SSE4-NEXT: pextrb $5, %xmm3, 21(%rdi)
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE4-NEXT: testl $4194304, %eax ## imm = 0x400000
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; SSE4-NEXT: je LBB16_46
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE4-NEXT: LBB16_45: ## %cond.store43
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; SSE4-NEXT: pextrb $6, %xmm3, 22(%rdi)
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE4-NEXT: testl $8388608, %eax ## imm = 0x800000
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; SSE4-NEXT: je LBB16_48
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE4-NEXT: LBB16_47: ## %cond.store45
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; SSE4-NEXT: pextrb $7, %xmm3, 23(%rdi)
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE4-NEXT: testl $16777216, %eax ## imm = 0x1000000
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; SSE4-NEXT: je LBB16_50
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE4-NEXT: LBB16_49: ## %cond.store47
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; SSE4-NEXT: pextrb $8, %xmm3, 24(%rdi)
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE4-NEXT: testl $33554432, %eax ## imm = 0x2000000
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; SSE4-NEXT: je LBB16_52
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE4-NEXT: LBB16_51: ## %cond.store49
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; SSE4-NEXT: pextrb $9, %xmm3, 25(%rdi)
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE4-NEXT: testl $67108864, %eax ## imm = 0x4000000
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; SSE4-NEXT: je LBB16_54
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE4-NEXT: LBB16_53: ## %cond.store51
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; SSE4-NEXT: pextrb $10, %xmm3, 26(%rdi)
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE4-NEXT: testl $134217728, %eax ## imm = 0x8000000
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; SSE4-NEXT: je LBB16_56
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE4-NEXT: LBB16_55: ## %cond.store53
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; SSE4-NEXT: pextrb $11, %xmm3, 27(%rdi)
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE4-NEXT: testl $268435456, %eax ## imm = 0x10000000
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; SSE4-NEXT: je LBB16_58
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE4-NEXT: LBB16_57: ## %cond.store55
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; SSE4-NEXT: pextrb $12, %xmm3, 28(%rdi)
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE4-NEXT: testl $536870912, %eax ## imm = 0x20000000
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; SSE4-NEXT: je LBB16_60
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE4-NEXT: LBB16_59: ## %cond.store57
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; SSE4-NEXT: pextrb $13, %xmm3, 29(%rdi)
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE4-NEXT: testl $1073741824, %eax ## imm = 0x40000000
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; SSE4-NEXT: je LBB16_62
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE4-NEXT: LBB16_61: ## %cond.store59
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; SSE4-NEXT: pextrb $14, %xmm3, 30(%rdi)
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE4-NEXT: testl $-2147483648, %eax ## imm = 0x80000000
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; SSE4-NEXT: je LBB16_64
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE4-NEXT: LBB16_63: ## %cond.store61
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; SSE4-NEXT: pextrb $15, %xmm3, 31(%rdi)
; SSE4-NEXT: retq
;
; AVX1-LABEL: store_v32i8_v32i8:
; AVX1: ## %bb.0:
; AVX1-NEXT: vpxor %xmm2, %xmm2, %xmm2
; AVX1-NEXT: vpcmpeqb %xmm2, %xmm0, %xmm3
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX1-NEXT: vpmovmskb %xmm3, %ecx
; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm0
; AVX1-NEXT: vpcmpeqb %xmm2, %xmm0, %xmm0
; AVX1-NEXT: vpmovmskb %xmm0, %eax
; AVX1-NEXT: shll $16, %eax
; AVX1-NEXT: orl %ecx, %eax
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; AVX1-NEXT: testb $1, %al
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX1-NEXT: jne LBB16_1
; AVX1-NEXT: ## %bb.2: ## %else
; AVX1-NEXT: testb $2, %al
; AVX1-NEXT: jne LBB16_3
; AVX1-NEXT: LBB16_4: ## %else2
; AVX1-NEXT: testb $4, %al
; AVX1-NEXT: jne LBB16_5
; AVX1-NEXT: LBB16_6: ## %else4
; AVX1-NEXT: testb $8, %al
; AVX1-NEXT: jne LBB16_7
; AVX1-NEXT: LBB16_8: ## %else6
; AVX1-NEXT: testb $16, %al
; AVX1-NEXT: jne LBB16_9
; AVX1-NEXT: LBB16_10: ## %else8
; AVX1-NEXT: testb $32, %al
; AVX1-NEXT: jne LBB16_11
; AVX1-NEXT: LBB16_12: ## %else10
; AVX1-NEXT: testb $64, %al
; AVX1-NEXT: jne LBB16_13
; AVX1-NEXT: LBB16_14: ## %else12
; AVX1-NEXT: testb $-128, %al
; AVX1-NEXT: jne LBB16_15
; AVX1-NEXT: LBB16_16: ## %else14
; AVX1-NEXT: testl $256, %eax ## imm = 0x100
; AVX1-NEXT: jne LBB16_17
; AVX1-NEXT: LBB16_18: ## %else16
; AVX1-NEXT: testl $512, %eax ## imm = 0x200
; AVX1-NEXT: jne LBB16_19
; AVX1-NEXT: LBB16_20: ## %else18
; AVX1-NEXT: testl $1024, %eax ## imm = 0x400
; AVX1-NEXT: jne LBB16_21
; AVX1-NEXT: LBB16_22: ## %else20
; AVX1-NEXT: testl $2048, %eax ## imm = 0x800
; AVX1-NEXT: jne LBB16_23
; AVX1-NEXT: LBB16_24: ## %else22
; AVX1-NEXT: testl $4096, %eax ## imm = 0x1000
; AVX1-NEXT: jne LBB16_25
; AVX1-NEXT: LBB16_26: ## %else24
; AVX1-NEXT: testl $8192, %eax ## imm = 0x2000
; AVX1-NEXT: jne LBB16_27
; AVX1-NEXT: LBB16_28: ## %else26
; AVX1-NEXT: testl $16384, %eax ## imm = 0x4000
; AVX1-NEXT: jne LBB16_29
; AVX1-NEXT: LBB16_30: ## %else28
; AVX1-NEXT: testl $32768, %eax ## imm = 0x8000
; AVX1-NEXT: je LBB16_32
; AVX1-NEXT: LBB16_31: ## %cond.store29
; AVX1-NEXT: vpextrb $15, %xmm1, 15(%rdi)
; AVX1-NEXT: LBB16_32: ## %else30
; AVX1-NEXT: testl $65536, %eax ## imm = 0x10000
; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm0
; AVX1-NEXT: jne LBB16_33
; AVX1-NEXT: ## %bb.34: ## %else32
; AVX1-NEXT: testl $131072, %eax ## imm = 0x20000
; AVX1-NEXT: jne LBB16_35
; AVX1-NEXT: LBB16_36: ## %else34
; AVX1-NEXT: testl $262144, %eax ## imm = 0x40000
; AVX1-NEXT: jne LBB16_37
; AVX1-NEXT: LBB16_38: ## %else36
; AVX1-NEXT: testl $524288, %eax ## imm = 0x80000
; AVX1-NEXT: jne LBB16_39
; AVX1-NEXT: LBB16_40: ## %else38
; AVX1-NEXT: testl $1048576, %eax ## imm = 0x100000
; AVX1-NEXT: jne LBB16_41
; AVX1-NEXT: LBB16_42: ## %else40
; AVX1-NEXT: testl $2097152, %eax ## imm = 0x200000
; AVX1-NEXT: jne LBB16_43
; AVX1-NEXT: LBB16_44: ## %else42
; AVX1-NEXT: testl $4194304, %eax ## imm = 0x400000
; AVX1-NEXT: jne LBB16_45
; AVX1-NEXT: LBB16_46: ## %else44
; AVX1-NEXT: testl $8388608, %eax ## imm = 0x800000
; AVX1-NEXT: jne LBB16_47
; AVX1-NEXT: LBB16_48: ## %else46
; AVX1-NEXT: testl $16777216, %eax ## imm = 0x1000000
; AVX1-NEXT: jne LBB16_49
; AVX1-NEXT: LBB16_50: ## %else48
; AVX1-NEXT: testl $33554432, %eax ## imm = 0x2000000
; AVX1-NEXT: jne LBB16_51
; AVX1-NEXT: LBB16_52: ## %else50
; AVX1-NEXT: testl $67108864, %eax ## imm = 0x4000000
; AVX1-NEXT: jne LBB16_53
; AVX1-NEXT: LBB16_54: ## %else52
; AVX1-NEXT: testl $134217728, %eax ## imm = 0x8000000
; AVX1-NEXT: jne LBB16_55
; AVX1-NEXT: LBB16_56: ## %else54
; AVX1-NEXT: testl $268435456, %eax ## imm = 0x10000000
; AVX1-NEXT: jne LBB16_57
; AVX1-NEXT: LBB16_58: ## %else56
; AVX1-NEXT: testl $536870912, %eax ## imm = 0x20000000
; AVX1-NEXT: jne LBB16_59
; AVX1-NEXT: LBB16_60: ## %else58
; AVX1-NEXT: testl $1073741824, %eax ## imm = 0x40000000
; AVX1-NEXT: jne LBB16_61
; AVX1-NEXT: LBB16_62: ## %else60
; AVX1-NEXT: testl $-2147483648, %eax ## imm = 0x80000000
; AVX1-NEXT: jne LBB16_63
; AVX1-NEXT: LBB16_64: ## %else62
; AVX1-NEXT: vzeroupper
; AVX1-NEXT: retq
; AVX1-NEXT: LBB16_1: ## %cond.store
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; AVX1-NEXT: vpextrb $0, %xmm1, (%rdi)
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX1-NEXT: testb $2, %al
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; AVX1-NEXT: je LBB16_4
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX1-NEXT: LBB16_3: ## %cond.store1
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; AVX1-NEXT: vpextrb $1, %xmm1, 1(%rdi)
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX1-NEXT: testb $4, %al
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; AVX1-NEXT: je LBB16_6
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX1-NEXT: LBB16_5: ## %cond.store3
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; AVX1-NEXT: vpextrb $2, %xmm1, 2(%rdi)
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX1-NEXT: testb $8, %al
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; AVX1-NEXT: je LBB16_8
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX1-NEXT: LBB16_7: ## %cond.store5
; AVX1-NEXT: vpextrb $3, %xmm1, 3(%rdi)
; AVX1-NEXT: testb $16, %al
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; AVX1-NEXT: je LBB16_10
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX1-NEXT: LBB16_9: ## %cond.store7
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; AVX1-NEXT: vpextrb $4, %xmm1, 4(%rdi)
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX1-NEXT: testb $32, %al
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; AVX1-NEXT: je LBB16_12
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX1-NEXT: LBB16_11: ## %cond.store9
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; AVX1-NEXT: vpextrb $5, %xmm1, 5(%rdi)
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX1-NEXT: testb $64, %al
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; AVX1-NEXT: je LBB16_14
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX1-NEXT: LBB16_13: ## %cond.store11
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; AVX1-NEXT: vpextrb $6, %xmm1, 6(%rdi)
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX1-NEXT: testb $-128, %al
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; AVX1-NEXT: je LBB16_16
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX1-NEXT: LBB16_15: ## %cond.store13
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; AVX1-NEXT: vpextrb $7, %xmm1, 7(%rdi)
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX1-NEXT: testl $256, %eax ## imm = 0x100
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; AVX1-NEXT: je LBB16_18
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX1-NEXT: LBB16_17: ## %cond.store15
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; AVX1-NEXT: vpextrb $8, %xmm1, 8(%rdi)
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX1-NEXT: testl $512, %eax ## imm = 0x200
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; AVX1-NEXT: je LBB16_20
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX1-NEXT: LBB16_19: ## %cond.store17
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; AVX1-NEXT: vpextrb $9, %xmm1, 9(%rdi)
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX1-NEXT: testl $1024, %eax ## imm = 0x400
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; AVX1-NEXT: je LBB16_22
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX1-NEXT: LBB16_21: ## %cond.store19
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; AVX1-NEXT: vpextrb $10, %xmm1, 10(%rdi)
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX1-NEXT: testl $2048, %eax ## imm = 0x800
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; AVX1-NEXT: je LBB16_24
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX1-NEXT: LBB16_23: ## %cond.store21
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; AVX1-NEXT: vpextrb $11, %xmm1, 11(%rdi)
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX1-NEXT: testl $4096, %eax ## imm = 0x1000
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; AVX1-NEXT: je LBB16_26
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX1-NEXT: LBB16_25: ## %cond.store23
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; AVX1-NEXT: vpextrb $12, %xmm1, 12(%rdi)
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX1-NEXT: testl $8192, %eax ## imm = 0x2000
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; AVX1-NEXT: je LBB16_28
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX1-NEXT: LBB16_27: ## %cond.store25
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; AVX1-NEXT: vpextrb $13, %xmm1, 13(%rdi)
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX1-NEXT: testl $16384, %eax ## imm = 0x4000
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; AVX1-NEXT: je LBB16_30
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX1-NEXT: LBB16_29: ## %cond.store27
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; AVX1-NEXT: vpextrb $14, %xmm1, 14(%rdi)
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX1-NEXT: testl $32768, %eax ## imm = 0x8000
; AVX1-NEXT: jne LBB16_31
; AVX1-NEXT: jmp LBB16_32
; AVX1-NEXT: LBB16_33: ## %cond.store31
[MIR] Add simple PRE pass to MachineCSE This is the second part of the commit fixing PR38917 (hoisting partitially redundant machine instruction). Most of PRE (partitial redundancy elimination) and CSE work is done on LLVM IR, but some of redundancy arises during DAG legalization. Machine CSE is not enough to deal with it. This simple PRE implementation works a little bit intricately: it passes before CSE, looking for partitial redundancy and transforming it to fully redundancy, anticipating that the next CSE step will eliminate this created redundancy. If CSE doesn't eliminate this, than created instruction will remain dead and eliminated later by Remove Dead Machine Instructions pass. The third part of the commit is supposed to refactor MachineCSE, to make it more clear and to merge MachinePRE with MachineCSE, so one need no rely on further Remove Dead pass to clear instrs not eliminated by CSE. First step: https://reviews.llvm.org/D54839 Fixes llvm.org/PR38917 This is fixed recommit of r361356 after PowerPC64 multistage build failure. llvm-svn: 362901
2019-06-09 20:15:47 +08:00
; AVX1-NEXT: vpextrb $0, %xmm0, 16(%rdi)
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX1-NEXT: testl $131072, %eax ## imm = 0x20000
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; AVX1-NEXT: je LBB16_36
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX1-NEXT: LBB16_35: ## %cond.store33
[MIR] Add simple PRE pass to MachineCSE This is the second part of the commit fixing PR38917 (hoisting partitially redundant machine instruction). Most of PRE (partitial redundancy elimination) and CSE work is done on LLVM IR, but some of redundancy arises during DAG legalization. Machine CSE is not enough to deal with it. This simple PRE implementation works a little bit intricately: it passes before CSE, looking for partitial redundancy and transforming it to fully redundancy, anticipating that the next CSE step will eliminate this created redundancy. If CSE doesn't eliminate this, than created instruction will remain dead and eliminated later by Remove Dead Machine Instructions pass. The third part of the commit is supposed to refactor MachineCSE, to make it more clear and to merge MachinePRE with MachineCSE, so one need no rely on further Remove Dead pass to clear instrs not eliminated by CSE. First step: https://reviews.llvm.org/D54839 Fixes llvm.org/PR38917 This is fixed recommit of r361356 after PowerPC64 multistage build failure. llvm-svn: 362901
2019-06-09 20:15:47 +08:00
; AVX1-NEXT: vpextrb $1, %xmm0, 17(%rdi)
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX1-NEXT: testl $262144, %eax ## imm = 0x40000
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; AVX1-NEXT: je LBB16_38
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX1-NEXT: LBB16_37: ## %cond.store35
[MIR] Add simple PRE pass to MachineCSE This is the second part of the commit fixing PR38917 (hoisting partitially redundant machine instruction). Most of PRE (partitial redundancy elimination) and CSE work is done on LLVM IR, but some of redundancy arises during DAG legalization. Machine CSE is not enough to deal with it. This simple PRE implementation works a little bit intricately: it passes before CSE, looking for partitial redundancy and transforming it to fully redundancy, anticipating that the next CSE step will eliminate this created redundancy. If CSE doesn't eliminate this, than created instruction will remain dead and eliminated later by Remove Dead Machine Instructions pass. The third part of the commit is supposed to refactor MachineCSE, to make it more clear and to merge MachinePRE with MachineCSE, so one need no rely on further Remove Dead pass to clear instrs not eliminated by CSE. First step: https://reviews.llvm.org/D54839 Fixes llvm.org/PR38917 This is fixed recommit of r361356 after PowerPC64 multistage build failure. llvm-svn: 362901
2019-06-09 20:15:47 +08:00
; AVX1-NEXT: vpextrb $2, %xmm0, 18(%rdi)
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX1-NEXT: testl $524288, %eax ## imm = 0x80000
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; AVX1-NEXT: je LBB16_40
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX1-NEXT: LBB16_39: ## %cond.store37
[MIR] Add simple PRE pass to MachineCSE This is the second part of the commit fixing PR38917 (hoisting partitially redundant machine instruction). Most of PRE (partitial redundancy elimination) and CSE work is done on LLVM IR, but some of redundancy arises during DAG legalization. Machine CSE is not enough to deal with it. This simple PRE implementation works a little bit intricately: it passes before CSE, looking for partitial redundancy and transforming it to fully redundancy, anticipating that the next CSE step will eliminate this created redundancy. If CSE doesn't eliminate this, than created instruction will remain dead and eliminated later by Remove Dead Machine Instructions pass. The third part of the commit is supposed to refactor MachineCSE, to make it more clear and to merge MachinePRE with MachineCSE, so one need no rely on further Remove Dead pass to clear instrs not eliminated by CSE. First step: https://reviews.llvm.org/D54839 Fixes llvm.org/PR38917 This is fixed recommit of r361356 after PowerPC64 multistage build failure. llvm-svn: 362901
2019-06-09 20:15:47 +08:00
; AVX1-NEXT: vpextrb $3, %xmm0, 19(%rdi)
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX1-NEXT: testl $1048576, %eax ## imm = 0x100000
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; AVX1-NEXT: je LBB16_42
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX1-NEXT: LBB16_41: ## %cond.store39
[MIR] Add simple PRE pass to MachineCSE This is the second part of the commit fixing PR38917 (hoisting partitially redundant machine instruction). Most of PRE (partitial redundancy elimination) and CSE work is done on LLVM IR, but some of redundancy arises during DAG legalization. Machine CSE is not enough to deal with it. This simple PRE implementation works a little bit intricately: it passes before CSE, looking for partitial redundancy and transforming it to fully redundancy, anticipating that the next CSE step will eliminate this created redundancy. If CSE doesn't eliminate this, than created instruction will remain dead and eliminated later by Remove Dead Machine Instructions pass. The third part of the commit is supposed to refactor MachineCSE, to make it more clear and to merge MachinePRE with MachineCSE, so one need no rely on further Remove Dead pass to clear instrs not eliminated by CSE. First step: https://reviews.llvm.org/D54839 Fixes llvm.org/PR38917 This is fixed recommit of r361356 after PowerPC64 multistage build failure. llvm-svn: 362901
2019-06-09 20:15:47 +08:00
; AVX1-NEXT: vpextrb $4, %xmm0, 20(%rdi)
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX1-NEXT: testl $2097152, %eax ## imm = 0x200000
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; AVX1-NEXT: je LBB16_44
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX1-NEXT: LBB16_43: ## %cond.store41
[MIR] Add simple PRE pass to MachineCSE This is the second part of the commit fixing PR38917 (hoisting partitially redundant machine instruction). Most of PRE (partitial redundancy elimination) and CSE work is done on LLVM IR, but some of redundancy arises during DAG legalization. Machine CSE is not enough to deal with it. This simple PRE implementation works a little bit intricately: it passes before CSE, looking for partitial redundancy and transforming it to fully redundancy, anticipating that the next CSE step will eliminate this created redundancy. If CSE doesn't eliminate this, than created instruction will remain dead and eliminated later by Remove Dead Machine Instructions pass. The third part of the commit is supposed to refactor MachineCSE, to make it more clear and to merge MachinePRE with MachineCSE, so one need no rely on further Remove Dead pass to clear instrs not eliminated by CSE. First step: https://reviews.llvm.org/D54839 Fixes llvm.org/PR38917 This is fixed recommit of r361356 after PowerPC64 multistage build failure. llvm-svn: 362901
2019-06-09 20:15:47 +08:00
; AVX1-NEXT: vpextrb $5, %xmm0, 21(%rdi)
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX1-NEXT: testl $4194304, %eax ## imm = 0x400000
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; AVX1-NEXT: je LBB16_46
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX1-NEXT: LBB16_45: ## %cond.store43
[MIR] Add simple PRE pass to MachineCSE This is the second part of the commit fixing PR38917 (hoisting partitially redundant machine instruction). Most of PRE (partitial redundancy elimination) and CSE work is done on LLVM IR, but some of redundancy arises during DAG legalization. Machine CSE is not enough to deal with it. This simple PRE implementation works a little bit intricately: it passes before CSE, looking for partitial redundancy and transforming it to fully redundancy, anticipating that the next CSE step will eliminate this created redundancy. If CSE doesn't eliminate this, than created instruction will remain dead and eliminated later by Remove Dead Machine Instructions pass. The third part of the commit is supposed to refactor MachineCSE, to make it more clear and to merge MachinePRE with MachineCSE, so one need no rely on further Remove Dead pass to clear instrs not eliminated by CSE. First step: https://reviews.llvm.org/D54839 Fixes llvm.org/PR38917 This is fixed recommit of r361356 after PowerPC64 multistage build failure. llvm-svn: 362901
2019-06-09 20:15:47 +08:00
; AVX1-NEXT: vpextrb $6, %xmm0, 22(%rdi)
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX1-NEXT: testl $8388608, %eax ## imm = 0x800000
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; AVX1-NEXT: je LBB16_48
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX1-NEXT: LBB16_47: ## %cond.store45
[MIR] Add simple PRE pass to MachineCSE This is the second part of the commit fixing PR38917 (hoisting partitially redundant machine instruction). Most of PRE (partitial redundancy elimination) and CSE work is done on LLVM IR, but some of redundancy arises during DAG legalization. Machine CSE is not enough to deal with it. This simple PRE implementation works a little bit intricately: it passes before CSE, looking for partitial redundancy and transforming it to fully redundancy, anticipating that the next CSE step will eliminate this created redundancy. If CSE doesn't eliminate this, than created instruction will remain dead and eliminated later by Remove Dead Machine Instructions pass. The third part of the commit is supposed to refactor MachineCSE, to make it more clear and to merge MachinePRE with MachineCSE, so one need no rely on further Remove Dead pass to clear instrs not eliminated by CSE. First step: https://reviews.llvm.org/D54839 Fixes llvm.org/PR38917 This is fixed recommit of r361356 after PowerPC64 multistage build failure. llvm-svn: 362901
2019-06-09 20:15:47 +08:00
; AVX1-NEXT: vpextrb $7, %xmm0, 23(%rdi)
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX1-NEXT: testl $16777216, %eax ## imm = 0x1000000
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; AVX1-NEXT: je LBB16_50
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX1-NEXT: LBB16_49: ## %cond.store47
[MIR] Add simple PRE pass to MachineCSE This is the second part of the commit fixing PR38917 (hoisting partitially redundant machine instruction). Most of PRE (partitial redundancy elimination) and CSE work is done on LLVM IR, but some of redundancy arises during DAG legalization. Machine CSE is not enough to deal with it. This simple PRE implementation works a little bit intricately: it passes before CSE, looking for partitial redundancy and transforming it to fully redundancy, anticipating that the next CSE step will eliminate this created redundancy. If CSE doesn't eliminate this, than created instruction will remain dead and eliminated later by Remove Dead Machine Instructions pass. The third part of the commit is supposed to refactor MachineCSE, to make it more clear and to merge MachinePRE with MachineCSE, so one need no rely on further Remove Dead pass to clear instrs not eliminated by CSE. First step: https://reviews.llvm.org/D54839 Fixes llvm.org/PR38917 This is fixed recommit of r361356 after PowerPC64 multistage build failure. llvm-svn: 362901
2019-06-09 20:15:47 +08:00
; AVX1-NEXT: vpextrb $8, %xmm0, 24(%rdi)
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX1-NEXT: testl $33554432, %eax ## imm = 0x2000000
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; AVX1-NEXT: je LBB16_52
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX1-NEXT: LBB16_51: ## %cond.store49
[MIR] Add simple PRE pass to MachineCSE This is the second part of the commit fixing PR38917 (hoisting partitially redundant machine instruction). Most of PRE (partitial redundancy elimination) and CSE work is done on LLVM IR, but some of redundancy arises during DAG legalization. Machine CSE is not enough to deal with it. This simple PRE implementation works a little bit intricately: it passes before CSE, looking for partitial redundancy and transforming it to fully redundancy, anticipating that the next CSE step will eliminate this created redundancy. If CSE doesn't eliminate this, than created instruction will remain dead and eliminated later by Remove Dead Machine Instructions pass. The third part of the commit is supposed to refactor MachineCSE, to make it more clear and to merge MachinePRE with MachineCSE, so one need no rely on further Remove Dead pass to clear instrs not eliminated by CSE. First step: https://reviews.llvm.org/D54839 Fixes llvm.org/PR38917 This is fixed recommit of r361356 after PowerPC64 multistage build failure. llvm-svn: 362901
2019-06-09 20:15:47 +08:00
; AVX1-NEXT: vpextrb $9, %xmm0, 25(%rdi)
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX1-NEXT: testl $67108864, %eax ## imm = 0x4000000
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; AVX1-NEXT: je LBB16_54
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX1-NEXT: LBB16_53: ## %cond.store51
[MIR] Add simple PRE pass to MachineCSE This is the second part of the commit fixing PR38917 (hoisting partitially redundant machine instruction). Most of PRE (partitial redundancy elimination) and CSE work is done on LLVM IR, but some of redundancy arises during DAG legalization. Machine CSE is not enough to deal with it. This simple PRE implementation works a little bit intricately: it passes before CSE, looking for partitial redundancy and transforming it to fully redundancy, anticipating that the next CSE step will eliminate this created redundancy. If CSE doesn't eliminate this, than created instruction will remain dead and eliminated later by Remove Dead Machine Instructions pass. The third part of the commit is supposed to refactor MachineCSE, to make it more clear and to merge MachinePRE with MachineCSE, so one need no rely on further Remove Dead pass to clear instrs not eliminated by CSE. First step: https://reviews.llvm.org/D54839 Fixes llvm.org/PR38917 This is fixed recommit of r361356 after PowerPC64 multistage build failure. llvm-svn: 362901
2019-06-09 20:15:47 +08:00
; AVX1-NEXT: vpextrb $10, %xmm0, 26(%rdi)
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX1-NEXT: testl $134217728, %eax ## imm = 0x8000000
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; AVX1-NEXT: je LBB16_56
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX1-NEXT: LBB16_55: ## %cond.store53
[MIR] Add simple PRE pass to MachineCSE This is the second part of the commit fixing PR38917 (hoisting partitially redundant machine instruction). Most of PRE (partitial redundancy elimination) and CSE work is done on LLVM IR, but some of redundancy arises during DAG legalization. Machine CSE is not enough to deal with it. This simple PRE implementation works a little bit intricately: it passes before CSE, looking for partitial redundancy and transforming it to fully redundancy, anticipating that the next CSE step will eliminate this created redundancy. If CSE doesn't eliminate this, than created instruction will remain dead and eliminated later by Remove Dead Machine Instructions pass. The third part of the commit is supposed to refactor MachineCSE, to make it more clear and to merge MachinePRE with MachineCSE, so one need no rely on further Remove Dead pass to clear instrs not eliminated by CSE. First step: https://reviews.llvm.org/D54839 Fixes llvm.org/PR38917 This is fixed recommit of r361356 after PowerPC64 multistage build failure. llvm-svn: 362901
2019-06-09 20:15:47 +08:00
; AVX1-NEXT: vpextrb $11, %xmm0, 27(%rdi)
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX1-NEXT: testl $268435456, %eax ## imm = 0x10000000
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; AVX1-NEXT: je LBB16_58
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX1-NEXT: LBB16_57: ## %cond.store55
[MIR] Add simple PRE pass to MachineCSE This is the second part of the commit fixing PR38917 (hoisting partitially redundant machine instruction). Most of PRE (partitial redundancy elimination) and CSE work is done on LLVM IR, but some of redundancy arises during DAG legalization. Machine CSE is not enough to deal with it. This simple PRE implementation works a little bit intricately: it passes before CSE, looking for partitial redundancy and transforming it to fully redundancy, anticipating that the next CSE step will eliminate this created redundancy. If CSE doesn't eliminate this, than created instruction will remain dead and eliminated later by Remove Dead Machine Instructions pass. The third part of the commit is supposed to refactor MachineCSE, to make it more clear and to merge MachinePRE with MachineCSE, so one need no rely on further Remove Dead pass to clear instrs not eliminated by CSE. First step: https://reviews.llvm.org/D54839 Fixes llvm.org/PR38917 This is fixed recommit of r361356 after PowerPC64 multistage build failure. llvm-svn: 362901
2019-06-09 20:15:47 +08:00
; AVX1-NEXT: vpextrb $12, %xmm0, 28(%rdi)
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX1-NEXT: testl $536870912, %eax ## imm = 0x20000000
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; AVX1-NEXT: je LBB16_60
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX1-NEXT: LBB16_59: ## %cond.store57
[MIR] Add simple PRE pass to MachineCSE This is the second part of the commit fixing PR38917 (hoisting partitially redundant machine instruction). Most of PRE (partitial redundancy elimination) and CSE work is done on LLVM IR, but some of redundancy arises during DAG legalization. Machine CSE is not enough to deal with it. This simple PRE implementation works a little bit intricately: it passes before CSE, looking for partitial redundancy and transforming it to fully redundancy, anticipating that the next CSE step will eliminate this created redundancy. If CSE doesn't eliminate this, than created instruction will remain dead and eliminated later by Remove Dead Machine Instructions pass. The third part of the commit is supposed to refactor MachineCSE, to make it more clear and to merge MachinePRE with MachineCSE, so one need no rely on further Remove Dead pass to clear instrs not eliminated by CSE. First step: https://reviews.llvm.org/D54839 Fixes llvm.org/PR38917 This is fixed recommit of r361356 after PowerPC64 multistage build failure. llvm-svn: 362901
2019-06-09 20:15:47 +08:00
; AVX1-NEXT: vpextrb $13, %xmm0, 29(%rdi)
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX1-NEXT: testl $1073741824, %eax ## imm = 0x40000000
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; AVX1-NEXT: je LBB16_62
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX1-NEXT: LBB16_61: ## %cond.store59
[MIR] Add simple PRE pass to MachineCSE This is the second part of the commit fixing PR38917 (hoisting partitially redundant machine instruction). Most of PRE (partitial redundancy elimination) and CSE work is done on LLVM IR, but some of redundancy arises during DAG legalization. Machine CSE is not enough to deal with it. This simple PRE implementation works a little bit intricately: it passes before CSE, looking for partitial redundancy and transforming it to fully redundancy, anticipating that the next CSE step will eliminate this created redundancy. If CSE doesn't eliminate this, than created instruction will remain dead and eliminated later by Remove Dead Machine Instructions pass. The third part of the commit is supposed to refactor MachineCSE, to make it more clear and to merge MachinePRE with MachineCSE, so one need no rely on further Remove Dead pass to clear instrs not eliminated by CSE. First step: https://reviews.llvm.org/D54839 Fixes llvm.org/PR38917 This is fixed recommit of r361356 after PowerPC64 multistage build failure. llvm-svn: 362901
2019-06-09 20:15:47 +08:00
; AVX1-NEXT: vpextrb $14, %xmm0, 30(%rdi)
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX1-NEXT: testl $-2147483648, %eax ## imm = 0x80000000
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; AVX1-NEXT: je LBB16_64
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX1-NEXT: LBB16_63: ## %cond.store61
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; AVX1-NEXT: vpextrb $15, %xmm0, 31(%rdi)
; AVX1-NEXT: vzeroupper
; AVX1-NEXT: retq
;
; AVX2-LABEL: store_v32i8_v32i8:
; AVX2: ## %bb.0:
; AVX2-NEXT: vpxor %xmm2, %xmm2, %xmm2
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX2-NEXT: vpcmpeqb %ymm2, %ymm0, %ymm0
; AVX2-NEXT: vpmovmskb %ymm0, %eax
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; AVX2-NEXT: testb $1, %al
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX2-NEXT: jne LBB16_1
; AVX2-NEXT: ## %bb.2: ## %else
; AVX2-NEXT: testb $2, %al
; AVX2-NEXT: jne LBB16_3
; AVX2-NEXT: LBB16_4: ## %else2
; AVX2-NEXT: testb $4, %al
; AVX2-NEXT: jne LBB16_5
; AVX2-NEXT: LBB16_6: ## %else4
; AVX2-NEXT: testb $8, %al
; AVX2-NEXT: jne LBB16_7
; AVX2-NEXT: LBB16_8: ## %else6
; AVX2-NEXT: testb $16, %al
; AVX2-NEXT: jne LBB16_9
; AVX2-NEXT: LBB16_10: ## %else8
; AVX2-NEXT: testb $32, %al
; AVX2-NEXT: jne LBB16_11
; AVX2-NEXT: LBB16_12: ## %else10
; AVX2-NEXT: testb $64, %al
; AVX2-NEXT: jne LBB16_13
; AVX2-NEXT: LBB16_14: ## %else12
; AVX2-NEXT: testb $-128, %al
; AVX2-NEXT: jne LBB16_15
; AVX2-NEXT: LBB16_16: ## %else14
; AVX2-NEXT: testl $256, %eax ## imm = 0x100
; AVX2-NEXT: jne LBB16_17
; AVX2-NEXT: LBB16_18: ## %else16
; AVX2-NEXT: testl $512, %eax ## imm = 0x200
; AVX2-NEXT: jne LBB16_19
; AVX2-NEXT: LBB16_20: ## %else18
; AVX2-NEXT: testl $1024, %eax ## imm = 0x400
; AVX2-NEXT: jne LBB16_21
; AVX2-NEXT: LBB16_22: ## %else20
; AVX2-NEXT: testl $2048, %eax ## imm = 0x800
; AVX2-NEXT: jne LBB16_23
; AVX2-NEXT: LBB16_24: ## %else22
; AVX2-NEXT: testl $4096, %eax ## imm = 0x1000
; AVX2-NEXT: jne LBB16_25
; AVX2-NEXT: LBB16_26: ## %else24
; AVX2-NEXT: testl $8192, %eax ## imm = 0x2000
; AVX2-NEXT: jne LBB16_27
; AVX2-NEXT: LBB16_28: ## %else26
; AVX2-NEXT: testl $16384, %eax ## imm = 0x4000
; AVX2-NEXT: jne LBB16_29
; AVX2-NEXT: LBB16_30: ## %else28
; AVX2-NEXT: testl $32768, %eax ## imm = 0x8000
; AVX2-NEXT: je LBB16_32
; AVX2-NEXT: LBB16_31: ## %cond.store29
; AVX2-NEXT: vpextrb $15, %xmm1, 15(%rdi)
; AVX2-NEXT: LBB16_32: ## %else30
; AVX2-NEXT: testl $65536, %eax ## imm = 0x10000
; AVX2-NEXT: vextracti128 $1, %ymm1, %xmm0
; AVX2-NEXT: jne LBB16_33
; AVX2-NEXT: ## %bb.34: ## %else32
; AVX2-NEXT: testl $131072, %eax ## imm = 0x20000
; AVX2-NEXT: jne LBB16_35
; AVX2-NEXT: LBB16_36: ## %else34
; AVX2-NEXT: testl $262144, %eax ## imm = 0x40000
; AVX2-NEXT: jne LBB16_37
; AVX2-NEXT: LBB16_38: ## %else36
; AVX2-NEXT: testl $524288, %eax ## imm = 0x80000
; AVX2-NEXT: jne LBB16_39
; AVX2-NEXT: LBB16_40: ## %else38
; AVX2-NEXT: testl $1048576, %eax ## imm = 0x100000
; AVX2-NEXT: jne LBB16_41
; AVX2-NEXT: LBB16_42: ## %else40
; AVX2-NEXT: testl $2097152, %eax ## imm = 0x200000
; AVX2-NEXT: jne LBB16_43
; AVX2-NEXT: LBB16_44: ## %else42
; AVX2-NEXT: testl $4194304, %eax ## imm = 0x400000
; AVX2-NEXT: jne LBB16_45
; AVX2-NEXT: LBB16_46: ## %else44
; AVX2-NEXT: testl $8388608, %eax ## imm = 0x800000
; AVX2-NEXT: jne LBB16_47
; AVX2-NEXT: LBB16_48: ## %else46
; AVX2-NEXT: testl $16777216, %eax ## imm = 0x1000000
; AVX2-NEXT: jne LBB16_49
; AVX2-NEXT: LBB16_50: ## %else48
; AVX2-NEXT: testl $33554432, %eax ## imm = 0x2000000
; AVX2-NEXT: jne LBB16_51
; AVX2-NEXT: LBB16_52: ## %else50
; AVX2-NEXT: testl $67108864, %eax ## imm = 0x4000000
; AVX2-NEXT: jne LBB16_53
; AVX2-NEXT: LBB16_54: ## %else52
; AVX2-NEXT: testl $134217728, %eax ## imm = 0x8000000
; AVX2-NEXT: jne LBB16_55
; AVX2-NEXT: LBB16_56: ## %else54
; AVX2-NEXT: testl $268435456, %eax ## imm = 0x10000000
; AVX2-NEXT: jne LBB16_57
; AVX2-NEXT: LBB16_58: ## %else56
; AVX2-NEXT: testl $536870912, %eax ## imm = 0x20000000
; AVX2-NEXT: jne LBB16_59
; AVX2-NEXT: LBB16_60: ## %else58
; AVX2-NEXT: testl $1073741824, %eax ## imm = 0x40000000
; AVX2-NEXT: jne LBB16_61
; AVX2-NEXT: LBB16_62: ## %else60
; AVX2-NEXT: testl $-2147483648, %eax ## imm = 0x80000000
; AVX2-NEXT: jne LBB16_63
; AVX2-NEXT: LBB16_64: ## %else62
; AVX2-NEXT: vzeroupper
; AVX2-NEXT: retq
; AVX2-NEXT: LBB16_1: ## %cond.store
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; AVX2-NEXT: vpextrb $0, %xmm1, (%rdi)
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX2-NEXT: testb $2, %al
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; AVX2-NEXT: je LBB16_4
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX2-NEXT: LBB16_3: ## %cond.store1
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; AVX2-NEXT: vpextrb $1, %xmm1, 1(%rdi)
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX2-NEXT: testb $4, %al
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; AVX2-NEXT: je LBB16_6
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX2-NEXT: LBB16_5: ## %cond.store3
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; AVX2-NEXT: vpextrb $2, %xmm1, 2(%rdi)
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX2-NEXT: testb $8, %al
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; AVX2-NEXT: je LBB16_8
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX2-NEXT: LBB16_7: ## %cond.store5
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; AVX2-NEXT: vpextrb $3, %xmm1, 3(%rdi)
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX2-NEXT: testb $16, %al
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; AVX2-NEXT: je LBB16_10
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX2-NEXT: LBB16_9: ## %cond.store7
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; AVX2-NEXT: vpextrb $4, %xmm1, 4(%rdi)
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX2-NEXT: testb $32, %al
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; AVX2-NEXT: je LBB16_12
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX2-NEXT: LBB16_11: ## %cond.store9
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; AVX2-NEXT: vpextrb $5, %xmm1, 5(%rdi)
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX2-NEXT: testb $64, %al
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; AVX2-NEXT: je LBB16_14
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX2-NEXT: LBB16_13: ## %cond.store11
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; AVX2-NEXT: vpextrb $6, %xmm1, 6(%rdi)
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX2-NEXT: testb $-128, %al
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; AVX2-NEXT: je LBB16_16
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX2-NEXT: LBB16_15: ## %cond.store13
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; AVX2-NEXT: vpextrb $7, %xmm1, 7(%rdi)
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX2-NEXT: testl $256, %eax ## imm = 0x100
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; AVX2-NEXT: je LBB16_18
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX2-NEXT: LBB16_17: ## %cond.store15
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; AVX2-NEXT: vpextrb $8, %xmm1, 8(%rdi)
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX2-NEXT: testl $512, %eax ## imm = 0x200
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; AVX2-NEXT: je LBB16_20
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX2-NEXT: LBB16_19: ## %cond.store17
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; AVX2-NEXT: vpextrb $9, %xmm1, 9(%rdi)
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX2-NEXT: testl $1024, %eax ## imm = 0x400
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; AVX2-NEXT: je LBB16_22
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX2-NEXT: LBB16_21: ## %cond.store19
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; AVX2-NEXT: vpextrb $10, %xmm1, 10(%rdi)
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX2-NEXT: testl $2048, %eax ## imm = 0x800
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; AVX2-NEXT: je LBB16_24
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX2-NEXT: LBB16_23: ## %cond.store21
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; AVX2-NEXT: vpextrb $11, %xmm1, 11(%rdi)
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX2-NEXT: testl $4096, %eax ## imm = 0x1000
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; AVX2-NEXT: je LBB16_26
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX2-NEXT: LBB16_25: ## %cond.store23
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; AVX2-NEXT: vpextrb $12, %xmm1, 12(%rdi)
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX2-NEXT: testl $8192, %eax ## imm = 0x2000
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; AVX2-NEXT: je LBB16_28
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX2-NEXT: LBB16_27: ## %cond.store25
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; AVX2-NEXT: vpextrb $13, %xmm1, 13(%rdi)
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX2-NEXT: testl $16384, %eax ## imm = 0x4000
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; AVX2-NEXT: je LBB16_30
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX2-NEXT: LBB16_29: ## %cond.store27
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; AVX2-NEXT: vpextrb $14, %xmm1, 14(%rdi)
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX2-NEXT: testl $32768, %eax ## imm = 0x8000
; AVX2-NEXT: jne LBB16_31
; AVX2-NEXT: jmp LBB16_32
; AVX2-NEXT: LBB16_33: ## %cond.store31
[X86][SSE] X86TargetLowering::isCommutativeBinOp - add PCMPEQ Allows narrowInsertExtractVectorBinOp to reduce vector size llvm-svn: 364432
2019-06-26 22:40:49 +08:00
; AVX2-NEXT: vpextrb $0, %xmm0, 16(%rdi)
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX2-NEXT: testl $131072, %eax ## imm = 0x20000
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; AVX2-NEXT: je LBB16_36
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX2-NEXT: LBB16_35: ## %cond.store33
[X86][SSE] X86TargetLowering::isCommutativeBinOp - add PCMPEQ Allows narrowInsertExtractVectorBinOp to reduce vector size llvm-svn: 364432
2019-06-26 22:40:49 +08:00
; AVX2-NEXT: vpextrb $1, %xmm0, 17(%rdi)
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX2-NEXT: testl $262144, %eax ## imm = 0x40000
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; AVX2-NEXT: je LBB16_38
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX2-NEXT: LBB16_37: ## %cond.store35
[X86][SSE] X86TargetLowering::isCommutativeBinOp - add PCMPEQ Allows narrowInsertExtractVectorBinOp to reduce vector size llvm-svn: 364432
2019-06-26 22:40:49 +08:00
; AVX2-NEXT: vpextrb $2, %xmm0, 18(%rdi)
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX2-NEXT: testl $524288, %eax ## imm = 0x80000
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; AVX2-NEXT: je LBB16_40
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX2-NEXT: LBB16_39: ## %cond.store37
[X86][SSE] X86TargetLowering::isCommutativeBinOp - add PCMPEQ Allows narrowInsertExtractVectorBinOp to reduce vector size llvm-svn: 364432
2019-06-26 22:40:49 +08:00
; AVX2-NEXT: vpextrb $3, %xmm0, 19(%rdi)
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX2-NEXT: testl $1048576, %eax ## imm = 0x100000
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; AVX2-NEXT: je LBB16_42
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX2-NEXT: LBB16_41: ## %cond.store39
[X86][SSE] X86TargetLowering::isCommutativeBinOp - add PCMPEQ Allows narrowInsertExtractVectorBinOp to reduce vector size llvm-svn: 364432
2019-06-26 22:40:49 +08:00
; AVX2-NEXT: vpextrb $4, %xmm0, 20(%rdi)
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX2-NEXT: testl $2097152, %eax ## imm = 0x200000
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; AVX2-NEXT: je LBB16_44
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX2-NEXT: LBB16_43: ## %cond.store41
[X86][SSE] X86TargetLowering::isCommutativeBinOp - add PCMPEQ Allows narrowInsertExtractVectorBinOp to reduce vector size llvm-svn: 364432
2019-06-26 22:40:49 +08:00
; AVX2-NEXT: vpextrb $5, %xmm0, 21(%rdi)
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX2-NEXT: testl $4194304, %eax ## imm = 0x400000
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; AVX2-NEXT: je LBB16_46
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX2-NEXT: LBB16_45: ## %cond.store43
[X86][SSE] X86TargetLowering::isCommutativeBinOp - add PCMPEQ Allows narrowInsertExtractVectorBinOp to reduce vector size llvm-svn: 364432
2019-06-26 22:40:49 +08:00
; AVX2-NEXT: vpextrb $6, %xmm0, 22(%rdi)
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX2-NEXT: testl $8388608, %eax ## imm = 0x800000
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; AVX2-NEXT: je LBB16_48
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX2-NEXT: LBB16_47: ## %cond.store45
[X86][SSE] X86TargetLowering::isCommutativeBinOp - add PCMPEQ Allows narrowInsertExtractVectorBinOp to reduce vector size llvm-svn: 364432
2019-06-26 22:40:49 +08:00
; AVX2-NEXT: vpextrb $7, %xmm0, 23(%rdi)
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX2-NEXT: testl $16777216, %eax ## imm = 0x1000000
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; AVX2-NEXT: je LBB16_50
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX2-NEXT: LBB16_49: ## %cond.store47
[X86][SSE] X86TargetLowering::isCommutativeBinOp - add PCMPEQ Allows narrowInsertExtractVectorBinOp to reduce vector size llvm-svn: 364432
2019-06-26 22:40:49 +08:00
; AVX2-NEXT: vpextrb $8, %xmm0, 24(%rdi)
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX2-NEXT: testl $33554432, %eax ## imm = 0x2000000
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; AVX2-NEXT: je LBB16_52
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX2-NEXT: LBB16_51: ## %cond.store49
[X86][SSE] X86TargetLowering::isCommutativeBinOp - add PCMPEQ Allows narrowInsertExtractVectorBinOp to reduce vector size llvm-svn: 364432
2019-06-26 22:40:49 +08:00
; AVX2-NEXT: vpextrb $9, %xmm0, 25(%rdi)
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX2-NEXT: testl $67108864, %eax ## imm = 0x4000000
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; AVX2-NEXT: je LBB16_54
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX2-NEXT: LBB16_53: ## %cond.store51
[X86][SSE] X86TargetLowering::isCommutativeBinOp - add PCMPEQ Allows narrowInsertExtractVectorBinOp to reduce vector size llvm-svn: 364432
2019-06-26 22:40:49 +08:00
; AVX2-NEXT: vpextrb $10, %xmm0, 26(%rdi)
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX2-NEXT: testl $134217728, %eax ## imm = 0x8000000
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; AVX2-NEXT: je LBB16_56
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX2-NEXT: LBB16_55: ## %cond.store53
[X86][SSE] X86TargetLowering::isCommutativeBinOp - add PCMPEQ Allows narrowInsertExtractVectorBinOp to reduce vector size llvm-svn: 364432
2019-06-26 22:40:49 +08:00
; AVX2-NEXT: vpextrb $11, %xmm0, 27(%rdi)
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX2-NEXT: testl $268435456, %eax ## imm = 0x10000000
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; AVX2-NEXT: je LBB16_58
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX2-NEXT: LBB16_57: ## %cond.store55
[X86][SSE] X86TargetLowering::isCommutativeBinOp - add PCMPEQ Allows narrowInsertExtractVectorBinOp to reduce vector size llvm-svn: 364432
2019-06-26 22:40:49 +08:00
; AVX2-NEXT: vpextrb $12, %xmm0, 28(%rdi)
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX2-NEXT: testl $536870912, %eax ## imm = 0x20000000
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; AVX2-NEXT: je LBB16_60
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX2-NEXT: LBB16_59: ## %cond.store57
[X86][SSE] X86TargetLowering::isCommutativeBinOp - add PCMPEQ Allows narrowInsertExtractVectorBinOp to reduce vector size llvm-svn: 364432
2019-06-26 22:40:49 +08:00
; AVX2-NEXT: vpextrb $13, %xmm0, 29(%rdi)
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX2-NEXT: testl $1073741824, %eax ## imm = 0x40000000
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; AVX2-NEXT: je LBB16_62
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX2-NEXT: LBB16_61: ## %cond.store59
[X86][SSE] X86TargetLowering::isCommutativeBinOp - add PCMPEQ Allows narrowInsertExtractVectorBinOp to reduce vector size llvm-svn: 364432
2019-06-26 22:40:49 +08:00
; AVX2-NEXT: vpextrb $14, %xmm0, 30(%rdi)
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX2-NEXT: testl $-2147483648, %eax ## imm = 0x80000000
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; AVX2-NEXT: je LBB16_64
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX2-NEXT: LBB16_63: ## %cond.store61
[X86][SSE] X86TargetLowering::isCommutativeBinOp - add PCMPEQ Allows narrowInsertExtractVectorBinOp to reduce vector size llvm-svn: 364432
2019-06-26 22:40:49 +08:00
; AVX2-NEXT: vpextrb $15, %xmm0, 31(%rdi)
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; AVX2-NEXT: vzeroupper
; AVX2-NEXT: retq
;
; AVX512F-LABEL: store_v32i8_v32i8:
; AVX512F: ## %bb.0:
; AVX512F-NEXT: vpxor %xmm2, %xmm2, %xmm2
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX512F-NEXT: vpcmpeqb %ymm2, %ymm0, %ymm0
; AVX512F-NEXT: vpmovmskb %ymm0, %eax
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; AVX512F-NEXT: testb $1, %al
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX512F-NEXT: jne LBB16_1
; AVX512F-NEXT: ## %bb.2: ## %else
; AVX512F-NEXT: testb $2, %al
; AVX512F-NEXT: jne LBB16_3
; AVX512F-NEXT: LBB16_4: ## %else2
; AVX512F-NEXT: testb $4, %al
; AVX512F-NEXT: jne LBB16_5
; AVX512F-NEXT: LBB16_6: ## %else4
; AVX512F-NEXT: testb $8, %al
; AVX512F-NEXT: jne LBB16_7
; AVX512F-NEXT: LBB16_8: ## %else6
; AVX512F-NEXT: testb $16, %al
; AVX512F-NEXT: jne LBB16_9
; AVX512F-NEXT: LBB16_10: ## %else8
; AVX512F-NEXT: testb $32, %al
; AVX512F-NEXT: jne LBB16_11
; AVX512F-NEXT: LBB16_12: ## %else10
; AVX512F-NEXT: testb $64, %al
; AVX512F-NEXT: jne LBB16_13
; AVX512F-NEXT: LBB16_14: ## %else12
; AVX512F-NEXT: testb $-128, %al
; AVX512F-NEXT: jne LBB16_15
; AVX512F-NEXT: LBB16_16: ## %else14
; AVX512F-NEXT: testl $256, %eax ## imm = 0x100
; AVX512F-NEXT: jne LBB16_17
; AVX512F-NEXT: LBB16_18: ## %else16
; AVX512F-NEXT: testl $512, %eax ## imm = 0x200
; AVX512F-NEXT: jne LBB16_19
; AVX512F-NEXT: LBB16_20: ## %else18
; AVX512F-NEXT: testl $1024, %eax ## imm = 0x400
; AVX512F-NEXT: jne LBB16_21
; AVX512F-NEXT: LBB16_22: ## %else20
; AVX512F-NEXT: testl $2048, %eax ## imm = 0x800
; AVX512F-NEXT: jne LBB16_23
; AVX512F-NEXT: LBB16_24: ## %else22
; AVX512F-NEXT: testl $4096, %eax ## imm = 0x1000
; AVX512F-NEXT: jne LBB16_25
; AVX512F-NEXT: LBB16_26: ## %else24
; AVX512F-NEXT: testl $8192, %eax ## imm = 0x2000
; AVX512F-NEXT: jne LBB16_27
; AVX512F-NEXT: LBB16_28: ## %else26
; AVX512F-NEXT: testl $16384, %eax ## imm = 0x4000
; AVX512F-NEXT: jne LBB16_29
; AVX512F-NEXT: LBB16_30: ## %else28
; AVX512F-NEXT: testl $32768, %eax ## imm = 0x8000
; AVX512F-NEXT: je LBB16_32
; AVX512F-NEXT: LBB16_31: ## %cond.store29
; AVX512F-NEXT: vpextrb $15, %xmm1, 15(%rdi)
; AVX512F-NEXT: LBB16_32: ## %else30
; AVX512F-NEXT: testl $65536, %eax ## imm = 0x10000
; AVX512F-NEXT: vextracti128 $1, %ymm1, %xmm0
; AVX512F-NEXT: jne LBB16_33
; AVX512F-NEXT: ## %bb.34: ## %else32
; AVX512F-NEXT: testl $131072, %eax ## imm = 0x20000
; AVX512F-NEXT: jne LBB16_35
; AVX512F-NEXT: LBB16_36: ## %else34
; AVX512F-NEXT: testl $262144, %eax ## imm = 0x40000
; AVX512F-NEXT: jne LBB16_37
; AVX512F-NEXT: LBB16_38: ## %else36
; AVX512F-NEXT: testl $524288, %eax ## imm = 0x80000
; AVX512F-NEXT: jne LBB16_39
; AVX512F-NEXT: LBB16_40: ## %else38
; AVX512F-NEXT: testl $1048576, %eax ## imm = 0x100000
; AVX512F-NEXT: jne LBB16_41
; AVX512F-NEXT: LBB16_42: ## %else40
; AVX512F-NEXT: testl $2097152, %eax ## imm = 0x200000
; AVX512F-NEXT: jne LBB16_43
; AVX512F-NEXT: LBB16_44: ## %else42
; AVX512F-NEXT: testl $4194304, %eax ## imm = 0x400000
; AVX512F-NEXT: jne LBB16_45
; AVX512F-NEXT: LBB16_46: ## %else44
; AVX512F-NEXT: testl $8388608, %eax ## imm = 0x800000
; AVX512F-NEXT: jne LBB16_47
; AVX512F-NEXT: LBB16_48: ## %else46
; AVX512F-NEXT: testl $16777216, %eax ## imm = 0x1000000
; AVX512F-NEXT: jne LBB16_49
; AVX512F-NEXT: LBB16_50: ## %else48
; AVX512F-NEXT: testl $33554432, %eax ## imm = 0x2000000
; AVX512F-NEXT: jne LBB16_51
; AVX512F-NEXT: LBB16_52: ## %else50
; AVX512F-NEXT: testl $67108864, %eax ## imm = 0x4000000
; AVX512F-NEXT: jne LBB16_53
; AVX512F-NEXT: LBB16_54: ## %else52
; AVX512F-NEXT: testl $134217728, %eax ## imm = 0x8000000
; AVX512F-NEXT: jne LBB16_55
; AVX512F-NEXT: LBB16_56: ## %else54
; AVX512F-NEXT: testl $268435456, %eax ## imm = 0x10000000
; AVX512F-NEXT: jne LBB16_57
; AVX512F-NEXT: LBB16_58: ## %else56
; AVX512F-NEXT: testl $536870912, %eax ## imm = 0x20000000
; AVX512F-NEXT: jne LBB16_59
; AVX512F-NEXT: LBB16_60: ## %else58
; AVX512F-NEXT: testl $1073741824, %eax ## imm = 0x40000000
; AVX512F-NEXT: jne LBB16_61
; AVX512F-NEXT: LBB16_62: ## %else60
; AVX512F-NEXT: testl $-2147483648, %eax ## imm = 0x80000000
; AVX512F-NEXT: jne LBB16_63
; AVX512F-NEXT: LBB16_64: ## %else62
; AVX512F-NEXT: vzeroupper
; AVX512F-NEXT: retq
; AVX512F-NEXT: LBB16_1: ## %cond.store
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; AVX512F-NEXT: vpextrb $0, %xmm1, (%rdi)
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX512F-NEXT: testb $2, %al
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; AVX512F-NEXT: je LBB16_4
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX512F-NEXT: LBB16_3: ## %cond.store1
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; AVX512F-NEXT: vpextrb $1, %xmm1, 1(%rdi)
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX512F-NEXT: testb $4, %al
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; AVX512F-NEXT: je LBB16_6
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX512F-NEXT: LBB16_5: ## %cond.store3
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; AVX512F-NEXT: vpextrb $2, %xmm1, 2(%rdi)
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX512F-NEXT: testb $8, %al
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; AVX512F-NEXT: je LBB16_8
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX512F-NEXT: LBB16_7: ## %cond.store5
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; AVX512F-NEXT: vpextrb $3, %xmm1, 3(%rdi)
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX512F-NEXT: testb $16, %al
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; AVX512F-NEXT: je LBB16_10
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX512F-NEXT: LBB16_9: ## %cond.store7
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; AVX512F-NEXT: vpextrb $4, %xmm1, 4(%rdi)
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX512F-NEXT: testb $32, %al
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; AVX512F-NEXT: je LBB16_12
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX512F-NEXT: LBB16_11: ## %cond.store9
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; AVX512F-NEXT: vpextrb $5, %xmm1, 5(%rdi)
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX512F-NEXT: testb $64, %al
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; AVX512F-NEXT: je LBB16_14
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX512F-NEXT: LBB16_13: ## %cond.store11
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; AVX512F-NEXT: vpextrb $6, %xmm1, 6(%rdi)
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX512F-NEXT: testb $-128, %al
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; AVX512F-NEXT: je LBB16_16
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX512F-NEXT: LBB16_15: ## %cond.store13
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; AVX512F-NEXT: vpextrb $7, %xmm1, 7(%rdi)
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX512F-NEXT: testl $256, %eax ## imm = 0x100
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; AVX512F-NEXT: je LBB16_18
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX512F-NEXT: LBB16_17: ## %cond.store15
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; AVX512F-NEXT: vpextrb $8, %xmm1, 8(%rdi)
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX512F-NEXT: testl $512, %eax ## imm = 0x200
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; AVX512F-NEXT: je LBB16_20
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX512F-NEXT: LBB16_19: ## %cond.store17
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; AVX512F-NEXT: vpextrb $9, %xmm1, 9(%rdi)
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX512F-NEXT: testl $1024, %eax ## imm = 0x400
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; AVX512F-NEXT: je LBB16_22
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX512F-NEXT: LBB16_21: ## %cond.store19
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; AVX512F-NEXT: vpextrb $10, %xmm1, 10(%rdi)
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX512F-NEXT: testl $2048, %eax ## imm = 0x800
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; AVX512F-NEXT: je LBB16_24
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX512F-NEXT: LBB16_23: ## %cond.store21
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; AVX512F-NEXT: vpextrb $11, %xmm1, 11(%rdi)
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX512F-NEXT: testl $4096, %eax ## imm = 0x1000
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; AVX512F-NEXT: je LBB16_26
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX512F-NEXT: LBB16_25: ## %cond.store23
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; AVX512F-NEXT: vpextrb $12, %xmm1, 12(%rdi)
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX512F-NEXT: testl $8192, %eax ## imm = 0x2000
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; AVX512F-NEXT: je LBB16_28
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX512F-NEXT: LBB16_27: ## %cond.store25
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; AVX512F-NEXT: vpextrb $13, %xmm1, 13(%rdi)
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX512F-NEXT: testl $16384, %eax ## imm = 0x4000
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; AVX512F-NEXT: je LBB16_30
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX512F-NEXT: LBB16_29: ## %cond.store27
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; AVX512F-NEXT: vpextrb $14, %xmm1, 14(%rdi)
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX512F-NEXT: testl $32768, %eax ## imm = 0x8000
; AVX512F-NEXT: jne LBB16_31
; AVX512F-NEXT: jmp LBB16_32
; AVX512F-NEXT: LBB16_33: ## %cond.store31
[X86][SSE] X86TargetLowering::isCommutativeBinOp - add PCMPEQ Allows narrowInsertExtractVectorBinOp to reduce vector size llvm-svn: 364432
2019-06-26 22:40:49 +08:00
; AVX512F-NEXT: vpextrb $0, %xmm0, 16(%rdi)
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX512F-NEXT: testl $131072, %eax ## imm = 0x20000
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; AVX512F-NEXT: je LBB16_36
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX512F-NEXT: LBB16_35: ## %cond.store33
[X86][SSE] X86TargetLowering::isCommutativeBinOp - add PCMPEQ Allows narrowInsertExtractVectorBinOp to reduce vector size llvm-svn: 364432
2019-06-26 22:40:49 +08:00
; AVX512F-NEXT: vpextrb $1, %xmm0, 17(%rdi)
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX512F-NEXT: testl $262144, %eax ## imm = 0x40000
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; AVX512F-NEXT: je LBB16_38
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX512F-NEXT: LBB16_37: ## %cond.store35
[X86][SSE] X86TargetLowering::isCommutativeBinOp - add PCMPEQ Allows narrowInsertExtractVectorBinOp to reduce vector size llvm-svn: 364432
2019-06-26 22:40:49 +08:00
; AVX512F-NEXT: vpextrb $2, %xmm0, 18(%rdi)
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX512F-NEXT: testl $524288, %eax ## imm = 0x80000
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; AVX512F-NEXT: je LBB16_40
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX512F-NEXT: LBB16_39: ## %cond.store37
[X86][SSE] X86TargetLowering::isCommutativeBinOp - add PCMPEQ Allows narrowInsertExtractVectorBinOp to reduce vector size llvm-svn: 364432
2019-06-26 22:40:49 +08:00
; AVX512F-NEXT: vpextrb $3, %xmm0, 19(%rdi)
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX512F-NEXT: testl $1048576, %eax ## imm = 0x100000
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; AVX512F-NEXT: je LBB16_42
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX512F-NEXT: LBB16_41: ## %cond.store39
[X86][SSE] X86TargetLowering::isCommutativeBinOp - add PCMPEQ Allows narrowInsertExtractVectorBinOp to reduce vector size llvm-svn: 364432
2019-06-26 22:40:49 +08:00
; AVX512F-NEXT: vpextrb $4, %xmm0, 20(%rdi)
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX512F-NEXT: testl $2097152, %eax ## imm = 0x200000
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; AVX512F-NEXT: je LBB16_44
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX512F-NEXT: LBB16_43: ## %cond.store41
[X86][SSE] X86TargetLowering::isCommutativeBinOp - add PCMPEQ Allows narrowInsertExtractVectorBinOp to reduce vector size llvm-svn: 364432
2019-06-26 22:40:49 +08:00
; AVX512F-NEXT: vpextrb $5, %xmm0, 21(%rdi)
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX512F-NEXT: testl $4194304, %eax ## imm = 0x400000
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; AVX512F-NEXT: je LBB16_46
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX512F-NEXT: LBB16_45: ## %cond.store43
[X86][SSE] X86TargetLowering::isCommutativeBinOp - add PCMPEQ Allows narrowInsertExtractVectorBinOp to reduce vector size llvm-svn: 364432
2019-06-26 22:40:49 +08:00
; AVX512F-NEXT: vpextrb $6, %xmm0, 22(%rdi)
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX512F-NEXT: testl $8388608, %eax ## imm = 0x800000
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; AVX512F-NEXT: je LBB16_48
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX512F-NEXT: LBB16_47: ## %cond.store45
[X86][SSE] X86TargetLowering::isCommutativeBinOp - add PCMPEQ Allows narrowInsertExtractVectorBinOp to reduce vector size llvm-svn: 364432
2019-06-26 22:40:49 +08:00
; AVX512F-NEXT: vpextrb $7, %xmm0, 23(%rdi)
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX512F-NEXT: testl $16777216, %eax ## imm = 0x1000000
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; AVX512F-NEXT: je LBB16_50
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX512F-NEXT: LBB16_49: ## %cond.store47
[X86][SSE] X86TargetLowering::isCommutativeBinOp - add PCMPEQ Allows narrowInsertExtractVectorBinOp to reduce vector size llvm-svn: 364432
2019-06-26 22:40:49 +08:00
; AVX512F-NEXT: vpextrb $8, %xmm0, 24(%rdi)
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX512F-NEXT: testl $33554432, %eax ## imm = 0x2000000
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; AVX512F-NEXT: je LBB16_52
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX512F-NEXT: LBB16_51: ## %cond.store49
[X86][SSE] X86TargetLowering::isCommutativeBinOp - add PCMPEQ Allows narrowInsertExtractVectorBinOp to reduce vector size llvm-svn: 364432
2019-06-26 22:40:49 +08:00
; AVX512F-NEXT: vpextrb $9, %xmm0, 25(%rdi)
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX512F-NEXT: testl $67108864, %eax ## imm = 0x4000000
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; AVX512F-NEXT: je LBB16_54
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX512F-NEXT: LBB16_53: ## %cond.store51
[X86][SSE] X86TargetLowering::isCommutativeBinOp - add PCMPEQ Allows narrowInsertExtractVectorBinOp to reduce vector size llvm-svn: 364432
2019-06-26 22:40:49 +08:00
; AVX512F-NEXT: vpextrb $10, %xmm0, 26(%rdi)
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX512F-NEXT: testl $134217728, %eax ## imm = 0x8000000
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; AVX512F-NEXT: je LBB16_56
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX512F-NEXT: LBB16_55: ## %cond.store53
[X86][SSE] X86TargetLowering::isCommutativeBinOp - add PCMPEQ Allows narrowInsertExtractVectorBinOp to reduce vector size llvm-svn: 364432
2019-06-26 22:40:49 +08:00
; AVX512F-NEXT: vpextrb $11, %xmm0, 27(%rdi)
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX512F-NEXT: testl $268435456, %eax ## imm = 0x10000000
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; AVX512F-NEXT: je LBB16_58
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX512F-NEXT: LBB16_57: ## %cond.store55
[X86][SSE] X86TargetLowering::isCommutativeBinOp - add PCMPEQ Allows narrowInsertExtractVectorBinOp to reduce vector size llvm-svn: 364432
2019-06-26 22:40:49 +08:00
; AVX512F-NEXT: vpextrb $12, %xmm0, 28(%rdi)
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX512F-NEXT: testl $536870912, %eax ## imm = 0x20000000
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; AVX512F-NEXT: je LBB16_60
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX512F-NEXT: LBB16_59: ## %cond.store57
[X86][SSE] X86TargetLowering::isCommutativeBinOp - add PCMPEQ Allows narrowInsertExtractVectorBinOp to reduce vector size llvm-svn: 364432
2019-06-26 22:40:49 +08:00
; AVX512F-NEXT: vpextrb $13, %xmm0, 29(%rdi)
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX512F-NEXT: testl $1073741824, %eax ## imm = 0x40000000
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; AVX512F-NEXT: je LBB16_62
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX512F-NEXT: LBB16_61: ## %cond.store59
[X86][SSE] X86TargetLowering::isCommutativeBinOp - add PCMPEQ Allows narrowInsertExtractVectorBinOp to reduce vector size llvm-svn: 364432
2019-06-26 22:40:49 +08:00
; AVX512F-NEXT: vpextrb $14, %xmm0, 30(%rdi)
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX512F-NEXT: testl $-2147483648, %eax ## imm = 0x80000000
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; AVX512F-NEXT: je LBB16_64
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX512F-NEXT: LBB16_63: ## %cond.store61
[X86][SSE] X86TargetLowering::isCommutativeBinOp - add PCMPEQ Allows narrowInsertExtractVectorBinOp to reduce vector size llvm-svn: 364432
2019-06-26 22:40:49 +08:00
; AVX512F-NEXT: vpextrb $15, %xmm0, 31(%rdi)
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; AVX512F-NEXT: vzeroupper
; AVX512F-NEXT: retq
;
[X86][AVX] Add AVX512DQ coverage for masked memory ops tests (PR34584) llvm-svn: 359395
2019-04-28 18:02:34 +08:00
; AVX512VLDQ-LABEL: store_v32i8_v32i8:
; AVX512VLDQ: ## %bb.0:
; AVX512VLDQ-NEXT: vpxor %xmm2, %xmm2, %xmm2
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX512VLDQ-NEXT: vpcmpeqb %ymm2, %ymm0, %ymm0
; AVX512VLDQ-NEXT: vpmovmskb %ymm0, %eax
[X86][AVX] Add AVX512DQ coverage for masked memory ops tests (PR34584) llvm-svn: 359395
2019-04-28 18:02:34 +08:00
; AVX512VLDQ-NEXT: testb $1, %al
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX512VLDQ-NEXT: jne LBB16_1
; AVX512VLDQ-NEXT: ## %bb.2: ## %else
; AVX512VLDQ-NEXT: testb $2, %al
; AVX512VLDQ-NEXT: jne LBB16_3
; AVX512VLDQ-NEXT: LBB16_4: ## %else2
; AVX512VLDQ-NEXT: testb $4, %al
; AVX512VLDQ-NEXT: jne LBB16_5
; AVX512VLDQ-NEXT: LBB16_6: ## %else4
; AVX512VLDQ-NEXT: testb $8, %al
; AVX512VLDQ-NEXT: jne LBB16_7
; AVX512VLDQ-NEXT: LBB16_8: ## %else6
; AVX512VLDQ-NEXT: testb $16, %al
; AVX512VLDQ-NEXT: jne LBB16_9
; AVX512VLDQ-NEXT: LBB16_10: ## %else8
; AVX512VLDQ-NEXT: testb $32, %al
; AVX512VLDQ-NEXT: jne LBB16_11
; AVX512VLDQ-NEXT: LBB16_12: ## %else10
; AVX512VLDQ-NEXT: testb $64, %al
; AVX512VLDQ-NEXT: jne LBB16_13
; AVX512VLDQ-NEXT: LBB16_14: ## %else12
; AVX512VLDQ-NEXT: testb $-128, %al
; AVX512VLDQ-NEXT: jne LBB16_15
; AVX512VLDQ-NEXT: LBB16_16: ## %else14
; AVX512VLDQ-NEXT: testl $256, %eax ## imm = 0x100
; AVX512VLDQ-NEXT: jne LBB16_17
; AVX512VLDQ-NEXT: LBB16_18: ## %else16
; AVX512VLDQ-NEXT: testl $512, %eax ## imm = 0x200
; AVX512VLDQ-NEXT: jne LBB16_19
; AVX512VLDQ-NEXT: LBB16_20: ## %else18
; AVX512VLDQ-NEXT: testl $1024, %eax ## imm = 0x400
; AVX512VLDQ-NEXT: jne LBB16_21
; AVX512VLDQ-NEXT: LBB16_22: ## %else20
; AVX512VLDQ-NEXT: testl $2048, %eax ## imm = 0x800
; AVX512VLDQ-NEXT: jne LBB16_23
; AVX512VLDQ-NEXT: LBB16_24: ## %else22
; AVX512VLDQ-NEXT: testl $4096, %eax ## imm = 0x1000
; AVX512VLDQ-NEXT: jne LBB16_25
; AVX512VLDQ-NEXT: LBB16_26: ## %else24
; AVX512VLDQ-NEXT: testl $8192, %eax ## imm = 0x2000
; AVX512VLDQ-NEXT: jne LBB16_27
; AVX512VLDQ-NEXT: LBB16_28: ## %else26
; AVX512VLDQ-NEXT: testl $16384, %eax ## imm = 0x4000
; AVX512VLDQ-NEXT: jne LBB16_29
; AVX512VLDQ-NEXT: LBB16_30: ## %else28
; AVX512VLDQ-NEXT: testl $32768, %eax ## imm = 0x8000
; AVX512VLDQ-NEXT: je LBB16_32
; AVX512VLDQ-NEXT: LBB16_31: ## %cond.store29
; AVX512VLDQ-NEXT: vpextrb $15, %xmm1, 15(%rdi)
; AVX512VLDQ-NEXT: LBB16_32: ## %else30
; AVX512VLDQ-NEXT: testl $65536, %eax ## imm = 0x10000
; AVX512VLDQ-NEXT: vextracti128 $1, %ymm1, %xmm0
; AVX512VLDQ-NEXT: jne LBB16_33
; AVX512VLDQ-NEXT: ## %bb.34: ## %else32
; AVX512VLDQ-NEXT: testl $131072, %eax ## imm = 0x20000
; AVX512VLDQ-NEXT: jne LBB16_35
; AVX512VLDQ-NEXT: LBB16_36: ## %else34
; AVX512VLDQ-NEXT: testl $262144, %eax ## imm = 0x40000
; AVX512VLDQ-NEXT: jne LBB16_37
; AVX512VLDQ-NEXT: LBB16_38: ## %else36
; AVX512VLDQ-NEXT: testl $524288, %eax ## imm = 0x80000
; AVX512VLDQ-NEXT: jne LBB16_39
; AVX512VLDQ-NEXT: LBB16_40: ## %else38
; AVX512VLDQ-NEXT: testl $1048576, %eax ## imm = 0x100000
; AVX512VLDQ-NEXT: jne LBB16_41
; AVX512VLDQ-NEXT: LBB16_42: ## %else40
; AVX512VLDQ-NEXT: testl $2097152, %eax ## imm = 0x200000
; AVX512VLDQ-NEXT: jne LBB16_43
; AVX512VLDQ-NEXT: LBB16_44: ## %else42
; AVX512VLDQ-NEXT: testl $4194304, %eax ## imm = 0x400000
; AVX512VLDQ-NEXT: jne LBB16_45
; AVX512VLDQ-NEXT: LBB16_46: ## %else44
; AVX512VLDQ-NEXT: testl $8388608, %eax ## imm = 0x800000
; AVX512VLDQ-NEXT: jne LBB16_47
; AVX512VLDQ-NEXT: LBB16_48: ## %else46
; AVX512VLDQ-NEXT: testl $16777216, %eax ## imm = 0x1000000
; AVX512VLDQ-NEXT: jne LBB16_49
; AVX512VLDQ-NEXT: LBB16_50: ## %else48
; AVX512VLDQ-NEXT: testl $33554432, %eax ## imm = 0x2000000
; AVX512VLDQ-NEXT: jne LBB16_51
; AVX512VLDQ-NEXT: LBB16_52: ## %else50
; AVX512VLDQ-NEXT: testl $67108864, %eax ## imm = 0x4000000
; AVX512VLDQ-NEXT: jne LBB16_53
; AVX512VLDQ-NEXT: LBB16_54: ## %else52
; AVX512VLDQ-NEXT: testl $134217728, %eax ## imm = 0x8000000
; AVX512VLDQ-NEXT: jne LBB16_55
; AVX512VLDQ-NEXT: LBB16_56: ## %else54
; AVX512VLDQ-NEXT: testl $268435456, %eax ## imm = 0x10000000
; AVX512VLDQ-NEXT: jne LBB16_57
; AVX512VLDQ-NEXT: LBB16_58: ## %else56
; AVX512VLDQ-NEXT: testl $536870912, %eax ## imm = 0x20000000
; AVX512VLDQ-NEXT: jne LBB16_59
; AVX512VLDQ-NEXT: LBB16_60: ## %else58
; AVX512VLDQ-NEXT: testl $1073741824, %eax ## imm = 0x40000000
; AVX512VLDQ-NEXT: jne LBB16_61
; AVX512VLDQ-NEXT: LBB16_62: ## %else60
; AVX512VLDQ-NEXT: testl $-2147483648, %eax ## imm = 0x80000000
; AVX512VLDQ-NEXT: jne LBB16_63
; AVX512VLDQ-NEXT: LBB16_64: ## %else62
; AVX512VLDQ-NEXT: vzeroupper
; AVX512VLDQ-NEXT: retq
; AVX512VLDQ-NEXT: LBB16_1: ## %cond.store
[X86][AVX] Add AVX512DQ coverage for masked memory ops tests (PR34584) llvm-svn: 359395
2019-04-28 18:02:34 +08:00
; AVX512VLDQ-NEXT: vpextrb $0, %xmm1, (%rdi)
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX512VLDQ-NEXT: testb $2, %al
[X86][AVX] Add AVX512DQ coverage for masked memory ops tests (PR34584) llvm-svn: 359395
2019-04-28 18:02:34 +08:00
; AVX512VLDQ-NEXT: je LBB16_4
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX512VLDQ-NEXT: LBB16_3: ## %cond.store1
[X86][AVX] Add AVX512DQ coverage for masked memory ops tests (PR34584) llvm-svn: 359395
2019-04-28 18:02:34 +08:00
; AVX512VLDQ-NEXT: vpextrb $1, %xmm1, 1(%rdi)
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX512VLDQ-NEXT: testb $4, %al
[X86][AVX] Add AVX512DQ coverage for masked memory ops tests (PR34584) llvm-svn: 359395
2019-04-28 18:02:34 +08:00
; AVX512VLDQ-NEXT: je LBB16_6
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX512VLDQ-NEXT: LBB16_5: ## %cond.store3
[X86][AVX] Add AVX512DQ coverage for masked memory ops tests (PR34584) llvm-svn: 359395
2019-04-28 18:02:34 +08:00
; AVX512VLDQ-NEXT: vpextrb $2, %xmm1, 2(%rdi)
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX512VLDQ-NEXT: testb $8, %al
[X86][AVX] Add AVX512DQ coverage for masked memory ops tests (PR34584) llvm-svn: 359395
2019-04-28 18:02:34 +08:00
; AVX512VLDQ-NEXT: je LBB16_8
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX512VLDQ-NEXT: LBB16_7: ## %cond.store5
[X86][AVX] Add AVX512DQ coverage for masked memory ops tests (PR34584) llvm-svn: 359395
2019-04-28 18:02:34 +08:00
; AVX512VLDQ-NEXT: vpextrb $3, %xmm1, 3(%rdi)
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX512VLDQ-NEXT: testb $16, %al
[X86][AVX] Add AVX512DQ coverage for masked memory ops tests (PR34584) llvm-svn: 359395
2019-04-28 18:02:34 +08:00
; AVX512VLDQ-NEXT: je LBB16_10
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX512VLDQ-NEXT: LBB16_9: ## %cond.store7
[X86][AVX] Add AVX512DQ coverage for masked memory ops tests (PR34584) llvm-svn: 359395
2019-04-28 18:02:34 +08:00
; AVX512VLDQ-NEXT: vpextrb $4, %xmm1, 4(%rdi)
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX512VLDQ-NEXT: testb $32, %al
[X86][AVX] Add AVX512DQ coverage for masked memory ops tests (PR34584) llvm-svn: 359395
2019-04-28 18:02:34 +08:00
; AVX512VLDQ-NEXT: je LBB16_12
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX512VLDQ-NEXT: LBB16_11: ## %cond.store9
[X86][AVX] Add AVX512DQ coverage for masked memory ops tests (PR34584) llvm-svn: 359395
2019-04-28 18:02:34 +08:00
; AVX512VLDQ-NEXT: vpextrb $5, %xmm1, 5(%rdi)
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX512VLDQ-NEXT: testb $64, %al
[X86][AVX] Add AVX512DQ coverage for masked memory ops tests (PR34584) llvm-svn: 359395
2019-04-28 18:02:34 +08:00
; AVX512VLDQ-NEXT: je LBB16_14
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX512VLDQ-NEXT: LBB16_13: ## %cond.store11
[X86][AVX] Add AVX512DQ coverage for masked memory ops tests (PR34584) llvm-svn: 359395
2019-04-28 18:02:34 +08:00
; AVX512VLDQ-NEXT: vpextrb $6, %xmm1, 6(%rdi)
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX512VLDQ-NEXT: testb $-128, %al
[X86][AVX] Add AVX512DQ coverage for masked memory ops tests (PR34584) llvm-svn: 359395
2019-04-28 18:02:34 +08:00
; AVX512VLDQ-NEXT: je LBB16_16
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX512VLDQ-NEXT: LBB16_15: ## %cond.store13
[X86][AVX] Add AVX512DQ coverage for masked memory ops tests (PR34584) llvm-svn: 359395
2019-04-28 18:02:34 +08:00
; AVX512VLDQ-NEXT: vpextrb $7, %xmm1, 7(%rdi)
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX512VLDQ-NEXT: testl $256, %eax ## imm = 0x100
[X86][AVX] Add AVX512DQ coverage for masked memory ops tests (PR34584) llvm-svn: 359395
2019-04-28 18:02:34 +08:00
; AVX512VLDQ-NEXT: je LBB16_18
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX512VLDQ-NEXT: LBB16_17: ## %cond.store15
[X86][AVX] Add AVX512DQ coverage for masked memory ops tests (PR34584) llvm-svn: 359395
2019-04-28 18:02:34 +08:00
; AVX512VLDQ-NEXT: vpextrb $8, %xmm1, 8(%rdi)
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX512VLDQ-NEXT: testl $512, %eax ## imm = 0x200
[X86][AVX] Add AVX512DQ coverage for masked memory ops tests (PR34584) llvm-svn: 359395
2019-04-28 18:02:34 +08:00
; AVX512VLDQ-NEXT: je LBB16_20
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX512VLDQ-NEXT: LBB16_19: ## %cond.store17
[X86][AVX] Add AVX512DQ coverage for masked memory ops tests (PR34584) llvm-svn: 359395
2019-04-28 18:02:34 +08:00
; AVX512VLDQ-NEXT: vpextrb $9, %xmm1, 9(%rdi)
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX512VLDQ-NEXT: testl $1024, %eax ## imm = 0x400
[X86][AVX] Add AVX512DQ coverage for masked memory ops tests (PR34584) llvm-svn: 359395
2019-04-28 18:02:34 +08:00
; AVX512VLDQ-NEXT: je LBB16_22
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX512VLDQ-NEXT: LBB16_21: ## %cond.store19
[X86][AVX] Add AVX512DQ coverage for masked memory ops tests (PR34584) llvm-svn: 359395
2019-04-28 18:02:34 +08:00
; AVX512VLDQ-NEXT: vpextrb $10, %xmm1, 10(%rdi)
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX512VLDQ-NEXT: testl $2048, %eax ## imm = 0x800
[X86][AVX] Add AVX512DQ coverage for masked memory ops tests (PR34584) llvm-svn: 359395
2019-04-28 18:02:34 +08:00
; AVX512VLDQ-NEXT: je LBB16_24
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX512VLDQ-NEXT: LBB16_23: ## %cond.store21
[X86][AVX] Add AVX512DQ coverage for masked memory ops tests (PR34584) llvm-svn: 359395
2019-04-28 18:02:34 +08:00
; AVX512VLDQ-NEXT: vpextrb $11, %xmm1, 11(%rdi)
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX512VLDQ-NEXT: testl $4096, %eax ## imm = 0x1000
[X86][AVX] Add AVX512DQ coverage for masked memory ops tests (PR34584) llvm-svn: 359395
2019-04-28 18:02:34 +08:00
; AVX512VLDQ-NEXT: je LBB16_26
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX512VLDQ-NEXT: LBB16_25: ## %cond.store23
[X86][AVX] Add AVX512DQ coverage for masked memory ops tests (PR34584) llvm-svn: 359395
2019-04-28 18:02:34 +08:00
; AVX512VLDQ-NEXT: vpextrb $12, %xmm1, 12(%rdi)
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX512VLDQ-NEXT: testl $8192, %eax ## imm = 0x2000
[X86][AVX] Add AVX512DQ coverage for masked memory ops tests (PR34584) llvm-svn: 359395
2019-04-28 18:02:34 +08:00
; AVX512VLDQ-NEXT: je LBB16_28
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX512VLDQ-NEXT: LBB16_27: ## %cond.store25
[X86][AVX] Add AVX512DQ coverage for masked memory ops tests (PR34584) llvm-svn: 359395
2019-04-28 18:02:34 +08:00
; AVX512VLDQ-NEXT: vpextrb $13, %xmm1, 13(%rdi)
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX512VLDQ-NEXT: testl $16384, %eax ## imm = 0x4000
[X86][AVX] Add AVX512DQ coverage for masked memory ops tests (PR34584) llvm-svn: 359395
2019-04-28 18:02:34 +08:00
; AVX512VLDQ-NEXT: je LBB16_30
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX512VLDQ-NEXT: LBB16_29: ## %cond.store27
[X86][AVX] Add AVX512DQ coverage for masked memory ops tests (PR34584) llvm-svn: 359395
2019-04-28 18:02:34 +08:00
; AVX512VLDQ-NEXT: vpextrb $14, %xmm1, 14(%rdi)
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX512VLDQ-NEXT: testl $32768, %eax ## imm = 0x8000
; AVX512VLDQ-NEXT: jne LBB16_31
; AVX512VLDQ-NEXT: jmp LBB16_32
; AVX512VLDQ-NEXT: LBB16_33: ## %cond.store31
[X86][SSE] X86TargetLowering::isCommutativeBinOp - add PCMPEQ Allows narrowInsertExtractVectorBinOp to reduce vector size llvm-svn: 364432
2019-06-26 22:40:49 +08:00
; AVX512VLDQ-NEXT: vpextrb $0, %xmm0, 16(%rdi)
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX512VLDQ-NEXT: testl $131072, %eax ## imm = 0x20000
[X86][AVX] Add AVX512DQ coverage for masked memory ops tests (PR34584) llvm-svn: 359395
2019-04-28 18:02:34 +08:00
; AVX512VLDQ-NEXT: je LBB16_36
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX512VLDQ-NEXT: LBB16_35: ## %cond.store33
[X86][SSE] X86TargetLowering::isCommutativeBinOp - add PCMPEQ Allows narrowInsertExtractVectorBinOp to reduce vector size llvm-svn: 364432
2019-06-26 22:40:49 +08:00
; AVX512VLDQ-NEXT: vpextrb $1, %xmm0, 17(%rdi)
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX512VLDQ-NEXT: testl $262144, %eax ## imm = 0x40000
[X86][AVX] Add AVX512DQ coverage for masked memory ops tests (PR34584) llvm-svn: 359395
2019-04-28 18:02:34 +08:00
; AVX512VLDQ-NEXT: je LBB16_38
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX512VLDQ-NEXT: LBB16_37: ## %cond.store35
[X86][SSE] X86TargetLowering::isCommutativeBinOp - add PCMPEQ Allows narrowInsertExtractVectorBinOp to reduce vector size llvm-svn: 364432
2019-06-26 22:40:49 +08:00
; AVX512VLDQ-NEXT: vpextrb $2, %xmm0, 18(%rdi)
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX512VLDQ-NEXT: testl $524288, %eax ## imm = 0x80000
[X86][AVX] Add AVX512DQ coverage for masked memory ops tests (PR34584) llvm-svn: 359395
2019-04-28 18:02:34 +08:00
; AVX512VLDQ-NEXT: je LBB16_40
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX512VLDQ-NEXT: LBB16_39: ## %cond.store37
[X86][SSE] X86TargetLowering::isCommutativeBinOp - add PCMPEQ Allows narrowInsertExtractVectorBinOp to reduce vector size llvm-svn: 364432
2019-06-26 22:40:49 +08:00
; AVX512VLDQ-NEXT: vpextrb $3, %xmm0, 19(%rdi)
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX512VLDQ-NEXT: testl $1048576, %eax ## imm = 0x100000
[X86][AVX] Add AVX512DQ coverage for masked memory ops tests (PR34584) llvm-svn: 359395
2019-04-28 18:02:34 +08:00
; AVX512VLDQ-NEXT: je LBB16_42
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX512VLDQ-NEXT: LBB16_41: ## %cond.store39
[X86][SSE] X86TargetLowering::isCommutativeBinOp - add PCMPEQ Allows narrowInsertExtractVectorBinOp to reduce vector size llvm-svn: 364432
2019-06-26 22:40:49 +08:00
; AVX512VLDQ-NEXT: vpextrb $4, %xmm0, 20(%rdi)
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX512VLDQ-NEXT: testl $2097152, %eax ## imm = 0x200000
[X86][AVX] Add AVX512DQ coverage for masked memory ops tests (PR34584) llvm-svn: 359395
2019-04-28 18:02:34 +08:00
; AVX512VLDQ-NEXT: je LBB16_44
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX512VLDQ-NEXT: LBB16_43: ## %cond.store41
[X86][SSE] X86TargetLowering::isCommutativeBinOp - add PCMPEQ Allows narrowInsertExtractVectorBinOp to reduce vector size llvm-svn: 364432
2019-06-26 22:40:49 +08:00
; AVX512VLDQ-NEXT: vpextrb $5, %xmm0, 21(%rdi)
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX512VLDQ-NEXT: testl $4194304, %eax ## imm = 0x400000
[X86][AVX] Add AVX512DQ coverage for masked memory ops tests (PR34584) llvm-svn: 359395
2019-04-28 18:02:34 +08:00
; AVX512VLDQ-NEXT: je LBB16_46
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX512VLDQ-NEXT: LBB16_45: ## %cond.store43
[X86][SSE] X86TargetLowering::isCommutativeBinOp - add PCMPEQ Allows narrowInsertExtractVectorBinOp to reduce vector size llvm-svn: 364432
2019-06-26 22:40:49 +08:00
; AVX512VLDQ-NEXT: vpextrb $6, %xmm0, 22(%rdi)
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX512VLDQ-NEXT: testl $8388608, %eax ## imm = 0x800000
[X86][AVX] Add AVX512DQ coverage for masked memory ops tests (PR34584) llvm-svn: 359395
2019-04-28 18:02:34 +08:00
; AVX512VLDQ-NEXT: je LBB16_48
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX512VLDQ-NEXT: LBB16_47: ## %cond.store45
[X86][SSE] X86TargetLowering::isCommutativeBinOp - add PCMPEQ Allows narrowInsertExtractVectorBinOp to reduce vector size llvm-svn: 364432
2019-06-26 22:40:49 +08:00
; AVX512VLDQ-NEXT: vpextrb $7, %xmm0, 23(%rdi)
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX512VLDQ-NEXT: testl $16777216, %eax ## imm = 0x1000000
[X86][AVX] Add AVX512DQ coverage for masked memory ops tests (PR34584) llvm-svn: 359395
2019-04-28 18:02:34 +08:00
; AVX512VLDQ-NEXT: je LBB16_50
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX512VLDQ-NEXT: LBB16_49: ## %cond.store47
[X86][SSE] X86TargetLowering::isCommutativeBinOp - add PCMPEQ Allows narrowInsertExtractVectorBinOp to reduce vector size llvm-svn: 364432
2019-06-26 22:40:49 +08:00
; AVX512VLDQ-NEXT: vpextrb $8, %xmm0, 24(%rdi)
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX512VLDQ-NEXT: testl $33554432, %eax ## imm = 0x2000000
[X86][AVX] Add AVX512DQ coverage for masked memory ops tests (PR34584) llvm-svn: 359395
2019-04-28 18:02:34 +08:00
; AVX512VLDQ-NEXT: je LBB16_52
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX512VLDQ-NEXT: LBB16_51: ## %cond.store49
[X86][SSE] X86TargetLowering::isCommutativeBinOp - add PCMPEQ Allows narrowInsertExtractVectorBinOp to reduce vector size llvm-svn: 364432
2019-06-26 22:40:49 +08:00
; AVX512VLDQ-NEXT: vpextrb $9, %xmm0, 25(%rdi)
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX512VLDQ-NEXT: testl $67108864, %eax ## imm = 0x4000000
[X86][AVX] Add AVX512DQ coverage for masked memory ops tests (PR34584) llvm-svn: 359395
2019-04-28 18:02:34 +08:00
; AVX512VLDQ-NEXT: je LBB16_54
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX512VLDQ-NEXT: LBB16_53: ## %cond.store51
[X86][SSE] X86TargetLowering::isCommutativeBinOp - add PCMPEQ Allows narrowInsertExtractVectorBinOp to reduce vector size llvm-svn: 364432
2019-06-26 22:40:49 +08:00
; AVX512VLDQ-NEXT: vpextrb $10, %xmm0, 26(%rdi)
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX512VLDQ-NEXT: testl $134217728, %eax ## imm = 0x8000000
[X86][AVX] Add AVX512DQ coverage for masked memory ops tests (PR34584) llvm-svn: 359395
2019-04-28 18:02:34 +08:00
; AVX512VLDQ-NEXT: je LBB16_56
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX512VLDQ-NEXT: LBB16_55: ## %cond.store53
[X86][SSE] X86TargetLowering::isCommutativeBinOp - add PCMPEQ Allows narrowInsertExtractVectorBinOp to reduce vector size llvm-svn: 364432
2019-06-26 22:40:49 +08:00
; AVX512VLDQ-NEXT: vpextrb $11, %xmm0, 27(%rdi)
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX512VLDQ-NEXT: testl $268435456, %eax ## imm = 0x10000000
[X86][AVX] Add AVX512DQ coverage for masked memory ops tests (PR34584) llvm-svn: 359395
2019-04-28 18:02:34 +08:00
; AVX512VLDQ-NEXT: je LBB16_58
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX512VLDQ-NEXT: LBB16_57: ## %cond.store55
[X86][SSE] X86TargetLowering::isCommutativeBinOp - add PCMPEQ Allows narrowInsertExtractVectorBinOp to reduce vector size llvm-svn: 364432
2019-06-26 22:40:49 +08:00
; AVX512VLDQ-NEXT: vpextrb $12, %xmm0, 28(%rdi)
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX512VLDQ-NEXT: testl $536870912, %eax ## imm = 0x20000000
[X86][AVX] Add AVX512DQ coverage for masked memory ops tests (PR34584) llvm-svn: 359395
2019-04-28 18:02:34 +08:00
; AVX512VLDQ-NEXT: je LBB16_60
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX512VLDQ-NEXT: LBB16_59: ## %cond.store57
[X86][SSE] X86TargetLowering::isCommutativeBinOp - add PCMPEQ Allows narrowInsertExtractVectorBinOp to reduce vector size llvm-svn: 364432
2019-06-26 22:40:49 +08:00
; AVX512VLDQ-NEXT: vpextrb $13, %xmm0, 29(%rdi)
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX512VLDQ-NEXT: testl $1073741824, %eax ## imm = 0x40000000
[X86][AVX] Add AVX512DQ coverage for masked memory ops tests (PR34584) llvm-svn: 359395
2019-04-28 18:02:34 +08:00
; AVX512VLDQ-NEXT: je LBB16_62
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX512VLDQ-NEXT: LBB16_61: ## %cond.store59
[X86][SSE] X86TargetLowering::isCommutativeBinOp - add PCMPEQ Allows narrowInsertExtractVectorBinOp to reduce vector size llvm-svn: 364432
2019-06-26 22:40:49 +08:00
; AVX512VLDQ-NEXT: vpextrb $14, %xmm0, 30(%rdi)
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX512VLDQ-NEXT: testl $-2147483648, %eax ## imm = 0x80000000
[X86][AVX] Add AVX512DQ coverage for masked memory ops tests (PR34584) llvm-svn: 359395
2019-04-28 18:02:34 +08:00
; AVX512VLDQ-NEXT: je LBB16_64
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; AVX512VLDQ-NEXT: LBB16_63: ## %cond.store61
[X86][SSE] X86TargetLowering::isCommutativeBinOp - add PCMPEQ Allows narrowInsertExtractVectorBinOp to reduce vector size llvm-svn: 364432
2019-06-26 22:40:49 +08:00
; AVX512VLDQ-NEXT: vpextrb $15, %xmm0, 31(%rdi)
[X86][AVX] Add AVX512DQ coverage for masked memory ops tests (PR34584) llvm-svn: 359395
2019-04-28 18:02:34 +08:00
; AVX512VLDQ-NEXT: vzeroupper
; AVX512VLDQ-NEXT: retq
;
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; AVX512VLBW-LABEL: store_v32i8_v32i8:
; AVX512VLBW: ## %bb.0:
; AVX512VLBW-NEXT: vptestnmb %ymm0, %ymm0, %k1
; AVX512VLBW-NEXT: vmovdqu8 %ymm1, (%rdi) {%k1}
; AVX512VLBW-NEXT: vzeroupper
; AVX512VLBW-NEXT: retq
%mask = icmp eq <32 x i8> %trigger, zeroinitializer
call void @llvm.masked.store.v32i8.p0v32i8(<32 x i8> %val, <32 x i8>* %addr, i32 4, <32 x i1> %mask)
ret void
}
;;; Stores with Constant Masks
define void @mstore_constmask_v4i32_v4i32(<4 x i32> %trigger, <4 x i32>* %addr, <4 x i32> %val) {
; SSE-LABEL: mstore_constmask_v4i32_v4i32:
; SSE: ## %bb.0:
; SSE-NEXT: movups %xmm1, (%rdi)
; SSE-NEXT: retq
;
; AVX1-LABEL: mstore_constmask_v4i32_v4i32:
; AVX1: ## %bb.0:
; AVX1-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; AVX1-NEXT: vmaskmovps %xmm1, %xmm0, (%rdi)
; AVX1-NEXT: retq
;
; AVX2-LABEL: mstore_constmask_v4i32_v4i32:
; AVX2: ## %bb.0:
; AVX2-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; AVX2-NEXT: vpmaskmovd %xmm1, %xmm0, (%rdi)
; AVX2-NEXT: retq
;
; AVX512F-LABEL: mstore_constmask_v4i32_v4i32:
; AVX512F: ## %bb.0:
; AVX512F-NEXT: ## kill: def $xmm1 killed $xmm1 def $zmm1
; AVX512F-NEXT: movw $15, %ax
; AVX512F-NEXT: kmovw %eax, %k1
; AVX512F-NEXT: vmovdqu32 %zmm1, (%rdi) {%k1}
; AVX512F-NEXT: vzeroupper
; AVX512F-NEXT: retq
;
[X86][AVX] Add AVX512DQ coverage for masked memory ops tests (PR34584) llvm-svn: 359395
2019-04-28 18:02:34 +08:00
; AVX512VL-LABEL: mstore_constmask_v4i32_v4i32:
; AVX512VL: ## %bb.0:
; AVX512VL-NEXT: kxnorw %k0, %k0, %k1
; AVX512VL-NEXT: vmovdqu32 %xmm1, (%rdi) {%k1}
; AVX512VL-NEXT: retq
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
%mask = icmp eq <4 x i32> %trigger, zeroinitializer
call void @llvm.masked.store.v4i32.p0v4i32(<4 x i32> %val, <4 x i32>* %addr, i32 4, <4 x i1><i1 true, i1 true, i1 true, i1 true>)
ret void
}
; When only one element of the mask is set, reduce to a scalar store.
define void @one_mask_bit_set1(<4 x i32>* %addr, <4 x i32> %val) {
; SSE-LABEL: one_mask_bit_set1:
; SSE: ## %bb.0:
; SSE-NEXT: movss %xmm0, (%rdi)
; SSE-NEXT: retq
;
; AVX-LABEL: one_mask_bit_set1:
; AVX: ## %bb.0:
; AVX-NEXT: vmovss %xmm0, (%rdi)
; AVX-NEXT: retq
call void @llvm.masked.store.v4i32.p0v4i32(<4 x i32> %val, <4 x i32>* %addr, i32 4, <4 x i1><i1 true, i1 false, i1 false, i1 false>)
ret void
}
; Choose a different element to show that the correct address offset is produced.
define void @one_mask_bit_set2(<4 x float>* %addr, <4 x float> %val) {
; SSE2-LABEL: one_mask_bit_set2:
; SSE2: ## %bb.0:
; SSE2-NEXT: movhlps {{.*#+}} xmm0 = xmm0[1,1]
; SSE2-NEXT: movss %xmm0, 8(%rdi)
; SSE2-NEXT: retq
;
; SSE4-LABEL: one_mask_bit_set2:
; SSE4: ## %bb.0:
; SSE4-NEXT: extractps $2, %xmm0, 8(%rdi)
[X86][AVX] Add PR34584 masked store test cases llvm-svn: 357757
2019-04-05 19:34:30 +08:00
; SSE4-NEXT: retq
;
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; AVX-LABEL: one_mask_bit_set2:
; AVX: ## %bb.0:
; AVX-NEXT: vextractps $2, %xmm0, 8(%rdi)
; AVX-NEXT: retq
call void @llvm.masked.store.v4f32.p0v4f32(<4 x float> %val, <4 x float>* %addr, i32 4, <4 x i1><i1 false, i1 false, i1 true, i1 false>)
ret void
}
; Choose a different scalar type and a high element of a 256-bit vector because AVX doesn't support those evenly.
define void @one_mask_bit_set3(<4 x i64>* %addr, <4 x i64> %val) {
; SSE-LABEL: one_mask_bit_set3:
; SSE: ## %bb.0:
; SSE-NEXT: movlps %xmm1, 16(%rdi)
; SSE-NEXT: retq
;
; AVX-LABEL: one_mask_bit_set3:
; AVX: ## %bb.0:
; AVX-NEXT: vextractf128 $1, %ymm0, %xmm0
; AVX-NEXT: vmovlps %xmm0, 16(%rdi)
; AVX-NEXT: vzeroupper
; AVX-NEXT: retq
call void @llvm.masked.store.v4i64.p0v4i64(<4 x i64> %val, <4 x i64>* %addr, i32 4, <4 x i1><i1 false, i1 false, i1 true, i1 false>)
ret void
}
; Choose a different scalar type and a high element of a 256-bit vector because AVX doesn't support those evenly.
define void @one_mask_bit_set4(<4 x double>* %addr, <4 x double> %val) {
; SSE-LABEL: one_mask_bit_set4:
; SSE: ## %bb.0:
[X86] Remove patterns from MOVLPSmr and MOVHPSmr instructions. These patterns are the same as the MOVLPDmr and MOVHPDmr patterns, but with a bitcast at the end. We can just select the PD instruction and let execution domain fixing switch to PS. llvm-svn: 365267
2019-07-07 01:59:51 +08:00
; SSE-NEXT: movhps %xmm1, 24(%rdi)
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; SSE-NEXT: retq
;
; AVX-LABEL: one_mask_bit_set4:
; AVX: ## %bb.0:
; AVX-NEXT: vextractf128 $1, %ymm0, %xmm0
[X86] Remove patterns from MOVLPSmr and MOVHPSmr instructions. These patterns are the same as the MOVLPDmr and MOVHPDmr patterns, but with a bitcast at the end. We can just select the PD instruction and let execution domain fixing switch to PS. llvm-svn: 365267
2019-07-07 01:59:51 +08:00
; AVX-NEXT: vmovhps %xmm0, 24(%rdi)
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; AVX-NEXT: vzeroupper
; AVX-NEXT: retq
call void @llvm.masked.store.v4f64.p0v4f64(<4 x double> %val, <4 x double>* %addr, i32 4, <4 x i1><i1 false, i1 false, i1 false, i1 true>)
ret void
}
; Try a 512-bit vector to make sure AVX doesn't die and AVX512 works as expected.
define void @one_mask_bit_set5(<8 x double>* %addr, <8 x double> %val) {
; SSE-LABEL: one_mask_bit_set5:
; SSE: ## %bb.0:
; SSE-NEXT: movlps %xmm3, 48(%rdi)
; SSE-NEXT: retq
;
; AVX1OR2-LABEL: one_mask_bit_set5:
[X86][AVX] Add PR34584 masked store test cases llvm-svn: 357757
2019-04-05 19:34:30 +08:00
; AVX1OR2: ## %bb.0:
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; AVX1OR2-NEXT: vextractf128 $1, %ymm1, %xmm0
; AVX1OR2-NEXT: vmovlps %xmm0, 48(%rdi)
[X86][AVX] Add PR34584 masked store test cases llvm-svn: 357757
2019-04-05 19:34:30 +08:00
; AVX1OR2-NEXT: vzeroupper
; AVX1OR2-NEXT: retq
;
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; AVX512-LABEL: one_mask_bit_set5:
[X86][AVX] Add PR34584 masked store test cases llvm-svn: 357757
2019-04-05 19:34:30 +08:00
; AVX512: ## %bb.0:
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
; AVX512-NEXT: vextractf32x4 $3, %zmm0, %xmm0
; AVX512-NEXT: vmovlps %xmm0, 48(%rdi)
[X86][AVX] Add PR34584 masked store test cases llvm-svn: 357757
2019-04-05 19:34:30 +08:00
; AVX512-NEXT: vzeroupper
; AVX512-NEXT: retq
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
call void @llvm.masked.store.v8f64.p0v8f64(<8 x double> %val, <8 x double>* %addr, i32 4, <8 x i1><i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 true, i1 false>)
[X86][AVX] Add PR34584 masked store test cases llvm-svn: 357757
2019-04-05 19:34:30 +08:00
ret void
}
; SimplifyDemandedBits eliminates an ashr here.
define void @masked_store_bool_mask_demand_trunc_sext(<4 x double> %x, <4 x double>* %p, <4 x i32> %masksrc) {
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE-LABEL: masked_store_bool_mask_demand_trunc_sext:
; SSE: ## %bb.0:
; SSE-NEXT: pslld $31, %xmm2
; SSE-NEXT: movmskps %xmm2, %eax
; SSE-NEXT: testb $1, %al
; SSE-NEXT: jne LBB23_1
; SSE-NEXT: ## %bb.2: ## %else
; SSE-NEXT: testb $2, %al
; SSE-NEXT: jne LBB23_3
; SSE-NEXT: LBB23_4: ## %else2
; SSE-NEXT: testb $4, %al
; SSE-NEXT: jne LBB23_5
; SSE-NEXT: LBB23_6: ## %else4
; SSE-NEXT: testb $8, %al
; SSE-NEXT: jne LBB23_7
; SSE-NEXT: LBB23_8: ## %else6
; SSE-NEXT: retq
; SSE-NEXT: LBB23_1: ## %cond.store
; SSE-NEXT: movlps %xmm0, (%rdi)
; SSE-NEXT: testb $2, %al
; SSE-NEXT: je LBB23_4
; SSE-NEXT: LBB23_3: ## %cond.store1
; SSE-NEXT: movhps %xmm0, 8(%rdi)
; SSE-NEXT: testb $4, %al
; SSE-NEXT: je LBB23_6
; SSE-NEXT: LBB23_5: ## %cond.store3
; SSE-NEXT: movlps %xmm1, 16(%rdi)
; SSE-NEXT: testb $8, %al
; SSE-NEXT: je LBB23_8
; SSE-NEXT: LBB23_7: ## %cond.store5
; SSE-NEXT: movhps %xmm1, 24(%rdi)
; SSE-NEXT: retq
[X86][SSE] Add SSE2/SSE42 masked load/store tests Now that the load/store tests are split the impact of running the tests on multiple (illegal) targets is a lot less impactful llvm-svn: 346896
2018-11-15 05:31:50 +08:00
;
[X86] Split masked load/store test files llvm-svn: 346889
2018-11-15 04:44:59 +08:00
; AVX1-LABEL: masked_store_bool_mask_demand_trunc_sext:
; AVX1: ## %bb.0:
; AVX1-NEXT: vpslld $31, %xmm1, %xmm1
; AVX1-NEXT: vpmovsxdq %xmm1, %xmm2
; AVX1-NEXT: vpshufd {{.*#+}} xmm1 = xmm1[2,3,0,1]
; AVX1-NEXT: vpmovsxdq %xmm1, %xmm1
; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm2, %ymm1
; AVX1-NEXT: vmaskmovpd %ymm0, %ymm1, (%rdi)
; AVX1-NEXT: vzeroupper
; AVX1-NEXT: retq
;
; AVX2-LABEL: masked_store_bool_mask_demand_trunc_sext:
; AVX2: ## %bb.0:
; AVX2-NEXT: vpslld $31, %xmm1, %xmm1
; AVX2-NEXT: vpmovsxdq %xmm1, %ymm1
; AVX2-NEXT: vmaskmovpd %ymm0, %ymm1, (%rdi)
; AVX2-NEXT: vzeroupper
; AVX2-NEXT: retq
;
; AVX512F-LABEL: masked_store_bool_mask_demand_trunc_sext:
; AVX512F: ## %bb.0:
; AVX512F-NEXT: ## kill: def $ymm0 killed $ymm0 def $zmm0
; AVX512F-NEXT: vpslld $31, %xmm1, %xmm1
; AVX512F-NEXT: vptestmd %zmm1, %zmm1, %k0
; AVX512F-NEXT: kshiftlw $12, %k0, %k0
; AVX512F-NEXT: kshiftrw $12, %k0, %k1
; AVX512F-NEXT: vmovupd %zmm0, (%rdi) {%k1}
; AVX512F-NEXT: vzeroupper
; AVX512F-NEXT: retq
;
[X86][AVX] Add AVX512DQ coverage for masked memory ops tests (PR34584) llvm-svn: 359395
2019-04-28 18:02:34 +08:00
; AVX512VLDQ-LABEL: masked_store_bool_mask_demand_trunc_sext:
; AVX512VLDQ: ## %bb.0:
; AVX512VLDQ-NEXT: vpslld $31, %xmm1, %xmm1
; AVX512VLDQ-NEXT: vpmovd2m %xmm1, %k1
; AVX512VLDQ-NEXT: vmovupd %ymm0, (%rdi) {%k1}
; AVX512VLDQ-NEXT: vzeroupper
; AVX512VLDQ-NEXT: retq
;
[X86][SSE] Add SSE2/SSE42 masked load/store tests Now that the load/store tests are split the impact of running the tests on multiple (illegal) targets is a lot less impactful llvm-svn: 346896
2018-11-15 05:31:50 +08:00
; AVX512VLBW-LABEL: masked_store_bool_mask_demand_trunc_sext:
; AVX512VLBW: ## %bb.0:
; AVX512VLBW-NEXT: vpslld $31, %xmm1, %xmm1
; AVX512VLBW-NEXT: vptestmd %xmm1, %xmm1, %k1
; AVX512VLBW-NEXT: vmovupd %ymm0, (%rdi) {%k1}
; AVX512VLBW-NEXT: vzeroupper
; AVX512VLBW-NEXT: retq
[X86] Split masked load/store test files llvm-svn: 346889
2018-11-15 04:44:59 +08:00
%sext = sext <4 x i32> %masksrc to <4 x i64>
%boolmask = trunc <4 x i64> %sext to <4 x i1>
call void @llvm.masked.store.v4f64.p0v4f64(<4 x double> %x, <4 x double>* %p, i32 4, <4 x i1> %boolmask)
ret void
}
[X86][SSE] Add masked bit test cases for PR26697 llvm-svn: 359082
2019-04-24 18:34:15 +08:00
; PR26697
define void @one_mask_bit_set1_variable(<4 x float>* %addr, <4 x float> %val, <4 x i32> %mask) {
; SSE2-LABEL: one_mask_bit_set1_variable:
; SSE2: ## %bb.0:
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE2-NEXT: movmskps %xmm1, %eax
[X86][SSE] Add masked bit test cases for PR26697 llvm-svn: 359082
2019-04-24 18:34:15 +08:00
; SSE2-NEXT: testb $1, %al
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE2-NEXT: jne LBB24_1
; SSE2-NEXT: ## %bb.2: ## %else
; SSE2-NEXT: testb $2, %al
; SSE2-NEXT: jne LBB24_3
; SSE2-NEXT: LBB24_4: ## %else2
; SSE2-NEXT: testb $4, %al
; SSE2-NEXT: jne LBB24_5
; SSE2-NEXT: LBB24_6: ## %else4
; SSE2-NEXT: testb $8, %al
; SSE2-NEXT: jne LBB24_7
; SSE2-NEXT: LBB24_8: ## %else6
; SSE2-NEXT: retq
; SSE2-NEXT: LBB24_1: ## %cond.store
[X86][SSE] Add masked bit test cases for PR26697 llvm-svn: 359082
2019-04-24 18:34:15 +08:00
; SSE2-NEXT: movss %xmm0, (%rdi)
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE2-NEXT: testb $2, %al
[X86][SSE] Add masked bit test cases for PR26697 llvm-svn: 359082
2019-04-24 18:34:15 +08:00
; SSE2-NEXT: je LBB24_4
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE2-NEXT: LBB24_3: ## %cond.store1
; SSE2-NEXT: movaps %xmm0, %xmm1
; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[1,1],xmm0[2,3]
; SSE2-NEXT: movss %xmm1, 4(%rdi)
; SSE2-NEXT: testb $4, %al
[X86][SSE] Add masked bit test cases for PR26697 llvm-svn: 359082
2019-04-24 18:34:15 +08:00
; SSE2-NEXT: je LBB24_6
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE2-NEXT: LBB24_5: ## %cond.store3
; SSE2-NEXT: movaps %xmm0, %xmm1
; SSE2-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm0[1]
; SSE2-NEXT: movss %xmm1, 8(%rdi)
; SSE2-NEXT: testb $8, %al
[X86][SSE] Add masked bit test cases for PR26697 llvm-svn: 359082
2019-04-24 18:34:15 +08:00
; SSE2-NEXT: je LBB24_8
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE2-NEXT: LBB24_7: ## %cond.store5
[X86][SSE] Add masked bit test cases for PR26697 llvm-svn: 359082
2019-04-24 18:34:15 +08:00
; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[3,1,2,3]
; SSE2-NEXT: movss %xmm0, 12(%rdi)
; SSE2-NEXT: retq
;
; SSE4-LABEL: one_mask_bit_set1_variable:
; SSE4: ## %bb.0:
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE4-NEXT: movmskps %xmm1, %eax
[X86][SSE] Add masked bit test cases for PR26697 llvm-svn: 359082
2019-04-24 18:34:15 +08:00
; SSE4-NEXT: testb $1, %al
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE4-NEXT: jne LBB24_1
; SSE4-NEXT: ## %bb.2: ## %else
; SSE4-NEXT: testb $2, %al
; SSE4-NEXT: jne LBB24_3
; SSE4-NEXT: LBB24_4: ## %else2
; SSE4-NEXT: testb $4, %al
; SSE4-NEXT: jne LBB24_5
; SSE4-NEXT: LBB24_6: ## %else4
; SSE4-NEXT: testb $8, %al
; SSE4-NEXT: jne LBB24_7
; SSE4-NEXT: LBB24_8: ## %else6
; SSE4-NEXT: retq
; SSE4-NEXT: LBB24_1: ## %cond.store
[X86][SSE] Add masked bit test cases for PR26697 llvm-svn: 359082
2019-04-24 18:34:15 +08:00
; SSE4-NEXT: movss %xmm0, (%rdi)
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE4-NEXT: testb $2, %al
[X86][SSE] Add masked bit test cases for PR26697 llvm-svn: 359082
2019-04-24 18:34:15 +08:00
; SSE4-NEXT: je LBB24_4
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE4-NEXT: LBB24_3: ## %cond.store1
[X86][SSE] Add masked bit test cases for PR26697 llvm-svn: 359082
2019-04-24 18:34:15 +08:00
; SSE4-NEXT: extractps $1, %xmm0, 4(%rdi)
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE4-NEXT: testb $4, %al
[X86][SSE] Add masked bit test cases for PR26697 llvm-svn: 359082
2019-04-24 18:34:15 +08:00
; SSE4-NEXT: je LBB24_6
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE4-NEXT: LBB24_5: ## %cond.store3
[X86][SSE] Add masked bit test cases for PR26697 llvm-svn: 359082
2019-04-24 18:34:15 +08:00
; SSE4-NEXT: extractps $2, %xmm0, 8(%rdi)
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE4-NEXT: testb $8, %al
[X86][SSE] Add masked bit test cases for PR26697 llvm-svn: 359082
2019-04-24 18:34:15 +08:00
; SSE4-NEXT: je LBB24_8
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE4-NEXT: LBB24_7: ## %cond.store5
[X86][SSE] Add masked bit test cases for PR26697 llvm-svn: 359082
2019-04-24 18:34:15 +08:00
; SSE4-NEXT: extractps $3, %xmm0, 12(%rdi)
; SSE4-NEXT: retq
;
; AVX1OR2-LABEL: one_mask_bit_set1_variable:
; AVX1OR2: ## %bb.0:
; AVX1OR2-NEXT: vmaskmovps %xmm0, %xmm1, (%rdi)
; AVX1OR2-NEXT: retq
;
; AVX512F-LABEL: one_mask_bit_set1_variable:
; AVX512F: ## %bb.0:
; AVX512F-NEXT: ## kill: def $xmm1 killed $xmm1 def $zmm1
; AVX512F-NEXT: ## kill: def $xmm0 killed $xmm0 def $zmm0
; AVX512F-NEXT: vptestmd {{.*}}(%rip){1to16}, %zmm1, %k0
; AVX512F-NEXT: kshiftlw $12, %k0, %k0
; AVX512F-NEXT: kshiftrw $12, %k0, %k1
; AVX512F-NEXT: vmovups %zmm0, (%rdi) {%k1}
; AVX512F-NEXT: vzeroupper
; AVX512F-NEXT: retq
;
[X86][AVX] Add AVX512DQ coverage for masked memory ops tests (PR34584) llvm-svn: 359395
2019-04-28 18:02:34 +08:00
; AVX512VL-LABEL: one_mask_bit_set1_variable:
; AVX512VL: ## %bb.0:
; AVX512VL-NEXT: vptestmd {{.*}}(%rip){1to4}, %xmm1, %k1
; AVX512VL-NEXT: vmovups %xmm0, (%rdi) {%k1}
; AVX512VL-NEXT: retq
[X86][SSE] Add masked bit test cases for PR26697 llvm-svn: 359082
2019-04-24 18:34:15 +08:00
%mask_signbit = and <4 x i32> %mask, <i32 2147483648, i32 2147483648, i32 2147483648, i32 2147483648>
%mask_bool = icmp ne <4 x i32> %mask_signbit, zeroinitializer
call void @llvm.masked.store.v4f32.p0v4f32(<4 x float> %val, <4 x float>* %addr, i32 1, <4 x i1> %mask_bool)
ret void
}
[X86] Split masked load/store test files llvm-svn: 346889
2018-11-15 04:44:59 +08:00
; This needs to be widened to v4i32.
; This used to assert in type legalization. PR38436
; FIXME: The codegen for AVX512 should use KSHIFT to zero the upper bits of the mask.
define void @widen_masked_store(<3 x i32> %v, <3 x i32>* %p, <3 x i1> %mask) {
[X86][SSE] Add SSE2/SSE42 masked load/store tests Now that the load/store tests are split the impact of running the tests on multiple (illegal) targets is a lot less impactful llvm-svn: 346896
2018-11-15 05:31:50 +08:00
; SSE2-LABEL: widen_masked_store:
; SSE2: ## %bb.0:
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE2-NEXT: andb $1, %sil
; SSE2-NEXT: andb $1, %dl
; SSE2-NEXT: addb %dl, %dl
; SSE2-NEXT: orb %sil, %dl
; SSE2-NEXT: andb $1, %cl
; SSE2-NEXT: shlb $2, %cl
; SSE2-NEXT: orb %dl, %cl
; SSE2-NEXT: testb $1, %cl
[X86][SSE] Add masked bit test cases for PR26697 llvm-svn: 359082
2019-04-24 18:34:15 +08:00
; SSE2-NEXT: jne LBB25_1
[X86][SSE] Add SSE2/SSE42 masked load/store tests Now that the load/store tests are split the impact of running the tests on multiple (illegal) targets is a lot less impactful llvm-svn: 346896
2018-11-15 05:31:50 +08:00
; SSE2-NEXT: ## %bb.2: ## %else
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE2-NEXT: testb $2, %cl
[X86][SSE] Add masked bit test cases for PR26697 llvm-svn: 359082
2019-04-24 18:34:15 +08:00
; SSE2-NEXT: jne LBB25_3
; SSE2-NEXT: LBB25_4: ## %else2
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE2-NEXT: testb $4, %cl
[X86][SSE] Add masked bit test cases for PR26697 llvm-svn: 359082
2019-04-24 18:34:15 +08:00
; SSE2-NEXT: jne LBB25_5
; SSE2-NEXT: LBB25_6: ## %else4
[X86][SSE] Add SSE2/SSE42 masked load/store tests Now that the load/store tests are split the impact of running the tests on multiple (illegal) targets is a lot less impactful llvm-svn: 346896
2018-11-15 05:31:50 +08:00
; SSE2-NEXT: retq
[X86][SSE] Add masked bit test cases for PR26697 llvm-svn: 359082
2019-04-24 18:34:15 +08:00
; SSE2-NEXT: LBB25_1: ## %cond.store
[X86][SSE] Add SSE2/SSE42 masked load/store tests Now that the load/store tests are split the impact of running the tests on multiple (illegal) targets is a lot less impactful llvm-svn: 346896
2018-11-15 05:31:50 +08:00
; SSE2-NEXT: movd %xmm0, (%rdi)
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE2-NEXT: testb $2, %cl
[X86][SSE] Add masked bit test cases for PR26697 llvm-svn: 359082
2019-04-24 18:34:15 +08:00
; SSE2-NEXT: je LBB25_4
; SSE2-NEXT: LBB25_3: ## %cond.store1
[X86][SSE] Add SSE2/SSE42 masked load/store tests Now that the load/store tests are split the impact of running the tests on multiple (illegal) targets is a lot less impactful llvm-svn: 346896
2018-11-15 05:31:50 +08:00
; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm0[1,1,2,3]
; SSE2-NEXT: movd %xmm1, 4(%rdi)
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE2-NEXT: testb $4, %cl
[X86][SSE] Add masked bit test cases for PR26697 llvm-svn: 359082
2019-04-24 18:34:15 +08:00
; SSE2-NEXT: je LBB25_6
; SSE2-NEXT: LBB25_5: ## %cond.store3
[X86][SSE] Add SSE2/SSE42 masked load/store tests Now that the load/store tests are split the impact of running the tests on multiple (illegal) targets is a lot less impactful llvm-svn: 346896
2018-11-15 05:31:50 +08:00
; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[2,3,0,1]
; SSE2-NEXT: movd %xmm0, 8(%rdi)
; SSE2-NEXT: retq
;
; SSE4-LABEL: widen_masked_store:
; SSE4: ## %bb.0:
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE4-NEXT: andb $1, %sil
; SSE4-NEXT: andb $1, %dl
; SSE4-NEXT: addb %dl, %dl
; SSE4-NEXT: orb %sil, %dl
; SSE4-NEXT: andb $1, %cl
; SSE4-NEXT: shlb $2, %cl
; SSE4-NEXT: orb %dl, %cl
; SSE4-NEXT: testb $1, %cl
[X86][SSE] Add masked bit test cases for PR26697 llvm-svn: 359082
2019-04-24 18:34:15 +08:00
; SSE4-NEXT: jne LBB25_1
[X86][SSE] Add SSE2/SSE42 masked load/store tests Now that the load/store tests are split the impact of running the tests on multiple (illegal) targets is a lot less impactful llvm-svn: 346896
2018-11-15 05:31:50 +08:00
; SSE4-NEXT: ## %bb.2: ## %else
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE4-NEXT: testb $2, %cl
[X86][SSE] Add masked bit test cases for PR26697 llvm-svn: 359082
2019-04-24 18:34:15 +08:00
; SSE4-NEXT: jne LBB25_3
; SSE4-NEXT: LBB25_4: ## %else2
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE4-NEXT: testb $4, %cl
[X86][SSE] Add masked bit test cases for PR26697 llvm-svn: 359082
2019-04-24 18:34:15 +08:00
; SSE4-NEXT: jne LBB25_5
; SSE4-NEXT: LBB25_6: ## %else4
[X86][SSE] Add SSE2/SSE42 masked load/store tests Now that the load/store tests are split the impact of running the tests on multiple (illegal) targets is a lot less impactful llvm-svn: 346896
2018-11-15 05:31:50 +08:00
; SSE4-NEXT: retq
[X86][SSE] Add masked bit test cases for PR26697 llvm-svn: 359082
2019-04-24 18:34:15 +08:00
; SSE4-NEXT: LBB25_1: ## %cond.store
[X86][SSE] Add SSE2/SSE42 masked load/store tests Now that the load/store tests are split the impact of running the tests on multiple (illegal) targets is a lot less impactful llvm-svn: 346896
2018-11-15 05:31:50 +08:00
; SSE4-NEXT: movss %xmm0, (%rdi)
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE4-NEXT: testb $2, %cl
[X86][SSE] Add masked bit test cases for PR26697 llvm-svn: 359082
2019-04-24 18:34:15 +08:00
; SSE4-NEXT: je LBB25_4
; SSE4-NEXT: LBB25_3: ## %cond.store1
[X86][SSE] Add SSE2/SSE42 masked load/store tests Now that the load/store tests are split the impact of running the tests on multiple (illegal) targets is a lot less impactful llvm-svn: 346896
2018-11-15 05:31:50 +08:00
; SSE4-NEXT: extractps $1, %xmm0, 4(%rdi)
[ScalarizeMaskedMemIntrin] Bitcast the mask to the scalar domain and use scalar bit tests for the branches. X86 at least is able to use movmsk or kmov to move the mask to the scalar domain. Then we can just use test instructions to test individual bits. This is more efficient than extracting each mask element individually. I special cased v1i1 to use the previous behavior. This avoids poor type legalization of bitcast of v1i1 to i1. I've skipped expandload/compressstore as I think we need to handle constant masks for those better first. Many tests end up with duplicate test instructions due to tail duplication in the branch folding pass. But the same thing happens when constructing similar code in C. So its not unique to the scalarization. Not sure if this lowering code will also be good for other targets, but we're only testing X86 today. Differential Revision: https://reviews.llvm.org/D65319 llvm-svn: 367489
2019-08-01 06:58:15 +08:00
; SSE4-NEXT: testb $4, %cl
[X86][SSE] Add masked bit test cases for PR26697 llvm-svn: 359082
2019-04-24 18:34:15 +08:00
; SSE4-NEXT: je LBB25_6
; SSE4-NEXT: LBB25_5: ## %cond.store3
[X86][SSE] Add SSE2/SSE42 masked load/store tests Now that the load/store tests are split the impact of running the tests on multiple (illegal) targets is a lot less impactful llvm-svn: 346896
2018-11-15 05:31:50 +08:00
; SSE4-NEXT: extractps $2, %xmm0, 8(%rdi)
; SSE4-NEXT: retq
;
[X86] Split masked load/store test files llvm-svn: 346889
2018-11-15 04:44:59 +08:00
; AVX1-LABEL: widen_masked_store:
; AVX1: ## %bb.0:
; AVX1-NEXT: vmovd %edx, %xmm1
; AVX1-NEXT: vmovd %esi, %xmm2
; AVX1-NEXT: vpunpckldq {{.*#+}} xmm1 = xmm2[0],xmm1[0],xmm2[1],xmm1[1]
; AVX1-NEXT: vmovd %ecx, %xmm2
; AVX1-NEXT: vpunpcklqdq {{.*#+}} xmm1 = xmm1[0],xmm2[0]
; AVX1-NEXT: vpslld $31, %xmm1, %xmm1
; AVX1-NEXT: vmaskmovps %xmm0, %xmm1, (%rdi)
; AVX1-NEXT: retq
;
; AVX2-LABEL: widen_masked_store:
; AVX2: ## %bb.0:
; AVX2-NEXT: vmovd %edx, %xmm1
; AVX2-NEXT: vmovd %esi, %xmm2
; AVX2-NEXT: vpunpckldq {{.*#+}} xmm1 = xmm2[0],xmm1[0],xmm2[1],xmm1[1]
; AVX2-NEXT: vmovd %ecx, %xmm2
; AVX2-NEXT: vpunpcklqdq {{.*#+}} xmm1 = xmm1[0],xmm2[0]
; AVX2-NEXT: vpslld $31, %xmm1, %xmm1
; AVX2-NEXT: vpmaskmovd %xmm0, %xmm1, (%rdi)
; AVX2-NEXT: retq
;
; AVX512F-LABEL: widen_masked_store:
; AVX512F: ## %bb.0:
; AVX512F-NEXT: ## kill: def $xmm0 killed $xmm0 def $zmm0
; AVX512F-NEXT: vpslld $31, %xmm1, %xmm1
; AVX512F-NEXT: vptestmd %zmm1, %zmm1, %k1
; AVX512F-NEXT: vpternlogd $255, %zmm1, %zmm1, %zmm1 {%k1} {z}
; AVX512F-NEXT: vpxor %xmm2, %xmm2, %xmm2
; AVX512F-NEXT: vpblendd {{.*#+}} xmm1 = xmm1[0,1,2],xmm2[3]
; AVX512F-NEXT: vptestmd %zmm1, %zmm1, %k0
; AVX512F-NEXT: kshiftlw $12, %k0, %k0
; AVX512F-NEXT: kshiftrw $12, %k0, %k1
; AVX512F-NEXT: vmovdqu32 %zmm0, (%rdi) {%k1}
; AVX512F-NEXT: vzeroupper
; AVX512F-NEXT: retq
;
[X86][AVX] Add AVX512DQ coverage for masked memory ops tests (PR34584) llvm-svn: 359395
2019-04-28 18:02:34 +08:00
; AVX512VLDQ-LABEL: widen_masked_store:
; AVX512VLDQ: ## %bb.0:
; AVX512VLDQ-NEXT: vpslld $31, %xmm1, %xmm1
; AVX512VLDQ-NEXT: vpmovd2m %xmm1, %k0
; AVX512VLDQ-NEXT: vpmovm2d %k0, %xmm1
; AVX512VLDQ-NEXT: vpxor %xmm2, %xmm2, %xmm2
; AVX512VLDQ-NEXT: vpblendd {{.*#+}} xmm1 = xmm1[0,1,2],xmm2[3]
; AVX512VLDQ-NEXT: vpmovd2m %xmm1, %k1
; AVX512VLDQ-NEXT: vmovdqa32 %xmm0, (%rdi) {%k1}
; AVX512VLDQ-NEXT: retq
;
[X86][SSE] Add SSE2/SSE42 masked load/store tests Now that the load/store tests are split the impact of running the tests on multiple (illegal) targets is a lot less impactful llvm-svn: 346896
2018-11-15 05:31:50 +08:00
; AVX512VLBW-LABEL: widen_masked_store:
; AVX512VLBW: ## %bb.0:
; AVX512VLBW-NEXT: vpslld $31, %xmm1, %xmm1
; AVX512VLBW-NEXT: vptestmd %xmm1, %xmm1, %k1
; AVX512VLBW-NEXT: vpcmpeqd %xmm1, %xmm1, %xmm1
; AVX512VLBW-NEXT: vmovdqa32 %xmm1, %xmm1 {%k1} {z}
; AVX512VLBW-NEXT: vpxor %xmm2, %xmm2, %xmm2
; AVX512VLBW-NEXT: vpblendd {{.*#+}} xmm1 = xmm1[0,1,2],xmm2[3]
; AVX512VLBW-NEXT: vptestmd %xmm1, %xmm1, %k1
; AVX512VLBW-NEXT: vmovdqa32 %xmm0, (%rdi) {%k1}
; AVX512VLBW-NEXT: retq
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
call void @llvm.masked.store.v3i32.p0v3i32(<3 x i32> %v, <3 x i32>* %p, i32 16, <3 x i1> %mask)
[X86] Split masked load/store test files llvm-svn: 346889
2018-11-15 04:44:59 +08:00
ret void
}
[X86] Add test cases for masked store and masked scatter with an all zeroes mask. Fix bug in ScalarizeMaskedMemIntrin Need to cast only to Constant instead of ConstantVector to allow ConstantAggregateZero. llvm-svn: 362341
2019-06-03 06:52:34 +08:00
define void @zero_mask(<2 x double>* %addr, <2 x double> %val) {
; SSE-LABEL: zero_mask:
; SSE: ## %bb.0:
; SSE-NEXT: retq
;
[DAGCombiner][X86] Fold away masked store and scatter with all zeroes mask. Similar to what was done for masked load and gather. llvm-svn: 362342
2019-06-03 06:52:38 +08:00
; AVX-LABEL: zero_mask:
; AVX: ## %bb.0:
; AVX-NEXT: retq
[X86] Add test cases for masked store and masked scatter with an all zeroes mask. Fix bug in ScalarizeMaskedMemIntrin Need to cast only to Constant instead of ConstantVector to allow ConstantAggregateZero. llvm-svn: 362341
2019-06-03 06:52:34 +08:00
call void @llvm.masked.store.v2f64.p0v2f64(<2 x double> %val, <2 x double>* %addr, i32 4, <2 x i1> zeroinitializer)
ret void
}
[X86] Split masked load/store test files llvm-svn: 346889
2018-11-15 04:44:59 +08:00
declare void @llvm.masked.store.v8f64.p0v8f64(<8 x double>, <8 x double>*, i32, <8 x i1>)
declare void @llvm.masked.store.v4f64.p0v4f64(<4 x double>, <4 x double>*, i32, <4 x i1>)
declare void @llvm.masked.store.v2f64.p0v2f64(<2 x double>, <2 x double>*, i32, <2 x i1>)
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
declare void @llvm.masked.store.v1f64.p0v1f64(<1 x double>, <1 x double>*, i32, <1 x i1>)
declare void @llvm.masked.store.v16f32.p0v16f32(<16 x float>, <16 x float>*, i32, <16 x i1>)
declare void @llvm.masked.store.v8f32.p0v8f32(<8 x float>, <8 x float>*, i32, <8 x i1>)
declare void @llvm.masked.store.v4f32.p0v4f32(<4 x float>, <4 x float>*, i32, <4 x i1>)
declare void @llvm.masked.store.v2f32.p0v2f32(<2 x float>, <2 x float>*, i32, <2 x i1>)
declare void @llvm.masked.store.v8i64.p0v8i64(<8 x i64>, <8 x i64>*, i32, <8 x i1>)
declare void @llvm.masked.store.v4i64.p0v4i64(<4 x i64>, <4 x i64>*, i32, <4 x i1>)
[X86] Split masked load/store test files llvm-svn: 346889
2018-11-15 04:44:59 +08:00
declare void @llvm.masked.store.v2i64.p0v2i64(<2 x i64>, <2 x i64>*, i32, <2 x i1>)
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
declare void @llvm.masked.store.v1i64.p0v1i64(<1 x i64>, <1 x i64>*, i32, <1 x i1>)
declare void @llvm.masked.store.v16i32.p0v16i32(<16 x i32>, <16 x i32>*, i32, <16 x i1>)
declare void @llvm.masked.store.v8i32.p0v8i32(<8 x i32>, <8 x i32>*, i32, <8 x i1>)
declare void @llvm.masked.store.v4i32.p0v4i32(<4 x i32>, <4 x i32>*, i32, <4 x i1>)
declare void @llvm.masked.store.v3i32.p0v3i32(<3 x i32>, <3 x i32>*, i32, <3 x i1>)
declare void @llvm.masked.store.v2i32.p0v2i32(<2 x i32>, <2 x i32>*, i32, <2 x i1>)
declare void @llvm.masked.store.v1i32.p0v1i32(<1 x i32>, <1 x i32>*, i32, <1 x i1>)
declare void @llvm.masked.store.v32i16.p0v32i16(<32 x i16>, <32 x i16>*, i32, <32 x i1>)
declare void @llvm.masked.store.v16i16.p0v16i16(<16 x i16>, <16 x i16>*, i32, <16 x i1>)
declare void @llvm.masked.store.v8i16.p0v8i16(<8 x i16>, <8 x i16>*, i32, <8 x i1>)
declare void @llvm.masked.store.v4i16.p0v4i16(<4 x i16>, <4 x i16>*, i32, <4 x i1>)
[X86] Split masked load/store test files llvm-svn: 346889
2018-11-15 04:44:59 +08:00
[X86][SSE] Add more exhaustive masked load/store tests Reordered/renamed some existing tests to match the cleaned up order llvm-svn: 357839
2019-04-06 22:01:37 +08:00
declare void @llvm.masked.store.v64i8.p0v64i8(<64 x i8>, <64 x i8>*, i32, <64 x i1>)
declare void @llvm.masked.store.v32i8.p0v32i8(<32 x i8>, <32 x i8>*, i32, <32 x i1>)
declare void @llvm.masked.store.v16i8.p0v16i8(<16 x i8>, <16 x i8>*, i32, <16 x i1>)
declare void @llvm.masked.store.v8i8.p0v8i8(<8 x i8>, <8 x i8>*, i32, <8 x i1>)