2005-10-16 13:39:50 +08:00
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//===-- PPCISelLowering.h - PPC32 DAG Lowering Interface --------*- C++ -*-===//
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2005-08-17 01:14:42 +08:00
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//
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// The LLVM Compiler Infrastructure
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//
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2007-12-30 04:36:04 +08:00
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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2005-08-17 01:14:42 +08:00
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defines the interfaces that PPC uses to lower LLVM code into a
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// selection DAG.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_TARGET_POWERPC_PPC32ISELLOWERING_H
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#define LLVM_TARGET_POWERPC_PPC32ISELLOWERING_H
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2005-10-15 07:51:18 +08:00
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#include "PPC.h"
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2006-11-02 09:44:04 +08:00
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#include "PPCSubtarget.h"
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2012-03-18 02:46:09 +08:00
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#include "llvm/CodeGen/SelectionDAG.h"
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2012-12-04 15:12:27 +08:00
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#include "llvm/Target/TargetLowering.h"
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2005-08-17 01:14:42 +08:00
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namespace llvm {
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2005-08-27 04:25:03 +08:00
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namespace PPCISD {
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enum NodeType {
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2007-01-27 06:40:50 +08:00
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// Start the numbering where the builtin ops and target ops leave off.
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2008-09-24 02:42:32 +08:00
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FIRST_NUMBER = ISD::BUILTIN_OP_END,
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2005-08-27 04:25:03 +08:00
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/// FSEL - Traditional three-operand fsel node.
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///
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FSEL,
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2011-02-26 05:41:48 +08:00
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2005-09-07 06:03:27 +08:00
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/// FCFID - The FCFID instruction, taking an f64 operand and producing
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/// and f64 value containing the FP representation of the integer that
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/// was temporarily in the f64 operand.
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FCFID,
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2011-02-26 05:41:48 +08:00
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/// FCTI[D,W]Z - The FCTIDZ and FCTIWZ instructions, taking an f32 or f64
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2005-09-07 06:03:27 +08:00
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/// operand, producing an f64 value containing the integer representation
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/// of that FP value.
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FCTIDZ, FCTIWZ,
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2011-02-26 05:41:48 +08:00
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2006-03-01 13:50:56 +08:00
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/// STFIWX - The STFIWX instruction. The first operand is an input token
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2009-09-26 04:36:54 +08:00
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/// chain, then an f64 value to store, then an address to store it to.
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2006-03-01 13:50:56 +08:00
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STFIWX,
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2011-02-26 05:41:48 +08:00
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2005-12-14 06:55:22 +08:00
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// VMADDFP, VNMSUBFP - The VMADDFP and VNMSUBFP instructions, taking
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// three v4f32 operands and producing a v4f32 result.
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VMADDFP, VNMSUBFP,
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2011-02-26 05:41:48 +08:00
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2006-03-20 09:53:53 +08:00
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/// VPERM - The PPC VPERM Instruction.
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///
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VPERM,
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2011-02-26 05:41:48 +08:00
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2005-11-17 15:30:41 +08:00
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/// Hi/Lo - These represent the high and low 16-bit parts of a global
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/// address respectively. These nodes have two operands, the first of
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/// which must be a TargetGlobalAddress, and the second of which must be a
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/// Constant. Selected naively, these turn into 'lis G+C' and 'li G+C',
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/// though these are usually folded into other nodes.
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Hi, Lo,
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2011-02-26 05:41:48 +08:00
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2009-08-15 19:54:46 +08:00
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TOC_ENTRY,
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2009-12-18 21:00:15 +08:00
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/// The following three target-specific nodes are used for calls through
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/// function pointers in the 64-bit SVR4 ABI.
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/// Restore the TOC from the TOC save area of the current stack frame.
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/// This is basically a hard coded load instruction which additionally
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/// takes/produces a flag.
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TOC_RESTORE,
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/// Like a regular LOAD but additionally taking/producing a flag.
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LOAD,
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/// LOAD into r2 (also taking/producing a flag). Like TOC_RESTORE, this is
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/// a hard coded load instruction.
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LOAD_TOC,
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2006-11-17 06:43:37 +08:00
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/// OPRC, CHAIN = DYNALLOC(CHAIN, NEGSIZE, FRAME_INDEX)
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/// This instruction is lowered in PPCRegisterInfo::eliminateFrameIndex to
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/// compute an allocation on the stack.
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DYNALLOC,
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2011-02-26 05:41:48 +08:00
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2005-11-17 15:30:41 +08:00
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/// GlobalBaseReg - On Darwin, this node represents the result of the mflr
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/// at function entry, used for PIC code.
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GlobalBaseReg,
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2011-02-26 05:41:48 +08:00
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2005-12-06 10:10:38 +08:00
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/// These nodes represent the 32-bit PPC shifts that operate on 6-bit
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/// shift amounts. These nodes are generated by the multi-precision shift
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/// code.
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SRL, SRA, SHL,
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2011-02-26 05:41:48 +08:00
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When possible, custom lower 32-bit SINT_TO_FP to this:
_foo2:
extsw r2, r3
std r2, -8(r1)
lfd f0, -8(r1)
fcfid f0, f0
frsp f1, f0
blr
instead of this:
_foo2:
lis r2, ha16(LCPI2_0)
lis r4, 17200
xoris r3, r3, 32768
stw r3, -4(r1)
stw r4, -8(r1)
lfs f0, lo16(LCPI2_0)(r2)
lfd f1, -8(r1)
fsub f0, f1, f0
frsp f1, f0
blr
This speeds up Misc/pi from 2.44s->2.09s with LLC and from 3.01->2.18s
with llcbeta (16.7% and 38.1% respectively).
llvm-svn: 26943
2006-03-22 13:30:33 +08:00
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/// EXTSW_32 - This is the EXTSW instruction for use with "32-bit"
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/// registers.
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EXTSW_32,
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2005-12-20 08:26:01 +08:00
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2006-05-18 03:00:46 +08:00
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/// CALL - A direct function call.
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2012-03-31 22:45:15 +08:00
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/// CALL_NOP_SVR4 is a call with the special NOP which follows 64-bit
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/// SVR4 calls.
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CALL_Darwin, CALL_SVR4, CALL_NOP_SVR4,
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2011-02-26 05:41:48 +08:00
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2009-08-15 19:54:46 +08:00
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/// NOP - Special NOP which follows 64-bit SVR4 calls.
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NOP,
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2006-05-18 03:00:46 +08:00
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/// CHAIN,FLAG = MTCTR(VAL, CHAIN[, INFLAG]) - Directly corresponds to a
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/// MTCTR instruction.
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MTCTR,
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2011-02-26 05:41:48 +08:00
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2006-05-18 03:00:46 +08:00
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/// CHAIN,FLAG = BCTRL(CHAIN, INFLAG) - Directly corresponds to a
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/// BCTRL instruction.
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2009-07-03 14:47:08 +08:00
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BCTRL_Darwin, BCTRL_SVR4,
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2011-02-26 05:41:48 +08:00
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2005-12-20 08:26:01 +08:00
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/// Return with a flag operand, matched by 'blr'
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RET_FLAG,
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2011-02-26 05:41:48 +08:00
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2010-05-21 01:48:26 +08:00
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/// R32 = MFCR(CRREG, INFLAG) - Represents the MFCRpseud/MFOCRF
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/// instructions. This copies the bits corresponding to the specified
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/// CRREG into the resultant GPR. Bits corresponding to other CR regs
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/// are undefined.
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2006-03-26 18:06:40 +08:00
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MFCR,
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2006-03-31 13:13:27 +08:00
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/// RESVEC = VCMP(LHS, RHS, OPC) - Represents one of the altivec VCMP*
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/// instructions. For lack of better number, we use the opcode number
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/// encoding for the OPC field to identify the compare. For example, 838
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/// is VCMPGTSH.
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VCMP,
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2011-02-26 05:41:48 +08:00
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2006-03-26 18:06:40 +08:00
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/// RESVEC, OUTFLAG = VCMPo(LHS, RHS, OPC) - Represents one of the
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2011-02-26 05:41:48 +08:00
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/// altivec VCMP*o instructions. For lack of better number, we use the
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2006-03-26 18:06:40 +08:00
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/// opcode number encoding for the OPC field to identify the compare. For
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/// example, 838 is VCMPGTSH.
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Implement an important entry from README_ALTIVEC:
If an altivec predicate compare is used immediately by a branch, don't
use a (serializing) MFCR instruction to read the CR6 register, which requires
a compare to get it back to CR's. Instead, just branch on CR6 directly. :)
For example, for:
void foo2(vector float *A, vector float *B) {
if (!vec_any_eq(*A, *B))
*B = (vector float){0,0,0,0};
}
We now generate:
_foo2:
mfspr r2, 256
oris r5, r2, 12288
mtspr 256, r5
lvx v2, 0, r4
lvx v3, 0, r3
vcmpeqfp. v2, v3, v2
bne cr6, LBB1_2 ; UnifiedReturnBlock
LBB1_1: ; cond_true
vxor v2, v2, v2
stvx v2, 0, r4
mtspr 256, r2
blr
LBB1_2: ; UnifiedReturnBlock
mtspr 256, r2
blr
instead of:
_foo2:
mfspr r2, 256
oris r5, r2, 12288
mtspr 256, r5
lvx v2, 0, r4
lvx v3, 0, r3
vcmpeqfp. v2, v3, v2
mfcr r3, 2
rlwinm r3, r3, 27, 31, 31
cmpwi cr0, r3, 0
beq cr0, LBB1_2 ; UnifiedReturnBlock
LBB1_1: ; cond_true
vxor v2, v2, v2
stvx v2, 0, r4
mtspr 256, r2
blr
LBB1_2: ; UnifiedReturnBlock
mtspr 256, r2
blr
This implements CodeGen/PowerPC/vec_br_cmp.ll.
llvm-svn: 27804
2006-04-19 01:59:36 +08:00
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VCMPo,
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2011-02-26 05:41:48 +08:00
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Implement an important entry from README_ALTIVEC:
If an altivec predicate compare is used immediately by a branch, don't
use a (serializing) MFCR instruction to read the CR6 register, which requires
a compare to get it back to CR's. Instead, just branch on CR6 directly. :)
For example, for:
void foo2(vector float *A, vector float *B) {
if (!vec_any_eq(*A, *B))
*B = (vector float){0,0,0,0};
}
We now generate:
_foo2:
mfspr r2, 256
oris r5, r2, 12288
mtspr 256, r5
lvx v2, 0, r4
lvx v3, 0, r3
vcmpeqfp. v2, v3, v2
bne cr6, LBB1_2 ; UnifiedReturnBlock
LBB1_1: ; cond_true
vxor v2, v2, v2
stvx v2, 0, r4
mtspr 256, r2
blr
LBB1_2: ; UnifiedReturnBlock
mtspr 256, r2
blr
instead of:
_foo2:
mfspr r2, 256
oris r5, r2, 12288
mtspr 256, r5
lvx v2, 0, r4
lvx v3, 0, r3
vcmpeqfp. v2, v3, v2
mfcr r3, 2
rlwinm r3, r3, 27, 31, 31
cmpwi cr0, r3, 0
beq cr0, LBB1_2 ; UnifiedReturnBlock
LBB1_1: ; cond_true
vxor v2, v2, v2
stvx v2, 0, r4
mtspr 256, r2
blr
LBB1_2: ; UnifiedReturnBlock
mtspr 256, r2
blr
This implements CodeGen/PowerPC/vec_br_cmp.ll.
llvm-svn: 27804
2006-04-19 01:59:36 +08:00
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/// CHAIN = COND_BRANCH CHAIN, CRRC, OPC, DESTBB [, INFLAG] - This
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/// corresponds to the COND_BRANCH pseudo instruction. CRRC is the
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/// condition register to branch on, OPC is the branch opcode to use (e.g.
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/// PPC::BLE), DESTBB is the destination block to branch to, and INFLAG is
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/// an optional input flag argument.
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2006-07-11 04:56:58 +08:00
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COND_BRANCH,
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2011-02-26 05:41:48 +08:00
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2007-10-10 09:01:31 +08:00
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// The following 5 instructions are used only as part of the
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// long double-to-int conversion sequence.
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/// OUTFLAG = MFFS F8RC - This moves the FPSCR (not modelled) into the
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/// register.
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MFFS,
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/// OUTFLAG = MTFSB0 INFLAG - This clears a bit in the FPSCR.
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MTFSB0,
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/// OUTFLAG = MTFSB1 INFLAG - This sets a bit in the FPSCR.
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MTFSB1,
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/// F8RC, OUTFLAG = FADDRTZ F8RC, F8RC, INFLAG - This is an FADD done with
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2011-02-26 05:41:48 +08:00
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/// rounding towards zero. It has flags added so it won't move past the
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2007-10-10 09:01:31 +08:00
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/// FPSCR-setting instructions.
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FADDRTZ,
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/// MTFSF = F8RC, INFLAG - This moves the register into the FPSCR.
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2008-04-19 09:30:48 +08:00
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MTFSF,
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2008-04-19 10:30:38 +08:00
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/// LARX = This corresponds to PPC l{w|d}arx instrcution: load and
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2008-04-19 09:30:48 +08:00
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/// reserve indexed. This is used to implement atomic operations.
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2008-04-19 10:30:38 +08:00
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LARX,
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2008-04-19 09:30:48 +08:00
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2008-04-19 10:30:38 +08:00
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/// STCX = This corresponds to PPC stcx. instrcution: store conditional
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/// indexed. This is used to implement atomic operations.
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STCX,
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2008-04-19 09:30:48 +08:00
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2008-04-30 17:16:33 +08:00
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/// TC_RETURN - A tail call return.
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/// operand #0 chain
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/// operand #1 callee (register or absolute)
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/// operand #2 stack adjustment
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/// operand #3 optional in flag
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2009-09-26 04:36:54 +08:00
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TC_RETURN,
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2012-08-28 10:10:27 +08:00
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/// ch, gl = CR6[UN]SET ch, inglue - Toggle CR bit 6 for SVR4 vararg calls
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CR6SET,
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CR6UNSET,
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This patch improves the 64-bit PowerPC InitialExec TLS support by providing
for a wider range of GOT entries that can hold thread-relative offsets.
This matches the behavior of GCC, which was not documented in the PPC64 TLS
ABI. The ABI will be updated with the new code sequence.
Former sequence:
ld 9,x@got@tprel(2)
add 9,9,x@tls
New sequence:
addis 9,2,x@got@tprel@ha
ld 9,x@got@tprel@l(9)
add 9,9,x@tls
Note that a linker optimization exists to transform the new sequence into
the shorter sequence when appropriate, by replacing the addis with a nop
and modifying the base register and relocation type of the ld.
llvm-svn: 170209
2012-12-15 01:02:38 +08:00
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/// G8RC = ADDIS_GOT_TPREL_HA %X2, Symbol - Used by the initial-exec
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/// TLS model, produces an ADDIS8 instruction that adds the GOT
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/// base to sym@got@tprel@ha.
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ADDIS_GOT_TPREL_HA,
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/// G8RC = LD_GOT_TPREL_L Symbol, G8RReg - Used by the initial-exec
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2012-12-05 00:18:08 +08:00
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/// TLS model, produces a LD instruction with base register G8RReg
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This patch improves the 64-bit PowerPC InitialExec TLS support by providing
for a wider range of GOT entries that can hold thread-relative offsets.
This matches the behavior of GCC, which was not documented in the PPC64 TLS
ABI. The ABI will be updated with the new code sequence.
Former sequence:
ld 9,x@got@tprel(2)
add 9,9,x@tls
New sequence:
addis 9,2,x@got@tprel@ha
ld 9,x@got@tprel@l(9)
add 9,9,x@tls
Note that a linker optimization exists to transform the new sequence into
the shorter sequence when appropriate, by replacing the addis with a nop
and modifying the base register and relocation type of the ld.
llvm-svn: 170209
2012-12-15 01:02:38 +08:00
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/// and offset sym@got@tprel@l. This completes the addition that
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/// finds the offset of "sym" relative to the thread pointer.
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LD_GOT_TPREL_L,
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2012-12-05 00:18:08 +08:00
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/// G8RC = ADD_TLS G8RReg, Symbol - Used by the initial-exec TLS
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/// model, produces an ADD instruction that adds the contents of
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/// G8RReg to the thread pointer. Symbol contains a relocation
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/// sym@tls which is to be replaced by the thread pointer and
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/// identifies to the linker that the instruction is part of a
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/// TLS sequence.
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ADD_TLS,
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This patch implements the general dynamic TLS model for 64-bit PowerPC.
Given a thread-local symbol x with global-dynamic access, the generated
code to obtain x's address is:
Instruction Relocation Symbol
addis ra,r2,x@got@tlsgd@ha R_PPC64_GOT_TLSGD16_HA x
addi r3,ra,x@got@tlsgd@l R_PPC64_GOT_TLSGD16_L x
bl __tls_get_addr(x@tlsgd) R_PPC64_TLSGD x
R_PPC64_REL24 __tls_get_addr
nop
<use address in r3>
The implementation borrows from the medium code model work for introducing
special forms of ADDIS and ADDI into the DAG representation. This is made
slightly more complicated by having to introduce a call to the external
function __tls_get_addr. Using the full call machinery is overkill and,
more importantly, makes it difficult to add a special relocation. So I've
introduced another opcode GET_TLS_ADDR to represent the function call, and
surrounded it with register copies to set up the parameter and return value.
Most of the code is pretty straightforward. I ran into one peculiarity
when I introduced a new PPC opcode BL8_NOP_ELF_TLSGD, which is just like
BL8_NOP_ELF except that it takes another parameter to represent the symbol
("x" above) that requires a relocation on the call. Something in the
TblGen machinery causes BL8_NOP_ELF and BL8_NOP_ELF_TLSGD to be treated
identically during the emit phase, so this second operand was never
visited to generate relocations. This is the reason for the slightly
messy workaround in PPCMCCodeEmitter.cpp:getDirectBrEncoding().
Two new tests are included to demonstrate correct external assembly and
correct generation of relocations using the integrated assembler.
Comments welcome!
Thanks,
Bill
llvm-svn: 169910
2012-12-12 04:30:11 +08:00
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/// G8RC = ADDIS_TLSGD_HA %X2, Symbol - For the general-dynamic TLS
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/// model, produces an ADDIS8 instruction that adds the GOT base
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/// register to sym@got@tlsgd@ha.
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ADDIS_TLSGD_HA,
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|
|
|
|
|
|
|
/// G8RC = ADDI_TLSGD_L G8RReg, Symbol - For the general-dynamic TLS
|
|
|
|
/// model, produces an ADDI8 instruction that adds G8RReg to
|
|
|
|
/// sym@got@tlsgd@l.
|
|
|
|
ADDI_TLSGD_L,
|
|
|
|
|
|
|
|
/// G8RC = GET_TLS_ADDR %X3, Symbol - For the general-dynamic TLS
|
|
|
|
/// model, produces a call to __tls_get_addr(sym@tlsgd).
|
|
|
|
GET_TLS_ADDR,
|
|
|
|
|
2012-12-13 03:29:35 +08:00
|
|
|
/// G8RC = ADDIS_TLSLD_HA %X2, Symbol - For the local-dynamic TLS
|
|
|
|
/// model, produces an ADDIS8 instruction that adds the GOT base
|
|
|
|
/// register to sym@got@tlsld@ha.
|
|
|
|
ADDIS_TLSLD_HA,
|
|
|
|
|
|
|
|
/// G8RC = ADDI_TLSLD_L G8RReg, Symbol - For the local-dynamic TLS
|
|
|
|
/// model, produces an ADDI8 instruction that adds G8RReg to
|
|
|
|
/// sym@got@tlsld@l.
|
|
|
|
ADDI_TLSLD_L,
|
|
|
|
|
|
|
|
/// G8RC = GET_TLSLD_ADDR %X3, Symbol - For the local-dynamic TLS
|
|
|
|
/// model, produces a call to __tls_get_addr(sym@tlsld).
|
|
|
|
GET_TLSLD_ADDR,
|
|
|
|
|
|
|
|
/// G8RC = ADDIS_DTPREL_HA %X3, Symbol, Chain - For the
|
|
|
|
/// local-dynamic TLS model, produces an ADDIS8 instruction
|
|
|
|
/// that adds X3 to sym@dtprel@ha. The Chain operand is needed
|
|
|
|
/// to tie this in place following a copy to %X3 from the result
|
|
|
|
/// of a GET_TLSLD_ADDR.
|
|
|
|
ADDIS_DTPREL_HA,
|
|
|
|
|
|
|
|
/// G8RC = ADDI_DTPREL_L G8RReg, Symbol - For the local-dynamic TLS
|
|
|
|
/// model, produces an ADDI8 instruction that adds G8RReg to
|
|
|
|
/// sym@got@dtprel@l.
|
|
|
|
ADDI_DTPREL_L,
|
|
|
|
|
2013-02-20 23:50:31 +08:00
|
|
|
/// VRRC = VADD_SPLAT Elt, EltSize - Temporary node to be expanded
|
|
|
|
/// into an ADD of a VSPLTI with itself during instruction selection.
|
|
|
|
/// Necessary to avoid losing this optimization due to constant folds.
|
|
|
|
VADD_SPLAT,
|
|
|
|
|
2009-09-26 04:36:54 +08:00
|
|
|
/// STD_32 - This is the STD instruction for use with "32-bit" registers.
|
|
|
|
STD_32 = ISD::FIRST_TARGET_MEMORY_OPCODE,
|
2011-02-26 05:41:48 +08:00
|
|
|
|
|
|
|
/// CHAIN = STBRX CHAIN, GPRC, Ptr, Type - This is a
|
2009-09-26 04:36:54 +08:00
|
|
|
/// byte-swapping store instruction. It byte-swaps the low "Type" bits of
|
|
|
|
/// the GPRC input, then stores it through Ptr. Type can be either i16 or
|
|
|
|
/// i32.
|
2011-02-26 05:41:48 +08:00
|
|
|
STBRX,
|
|
|
|
|
|
|
|
/// GPRC, CHAIN = LBRX CHAIN, Ptr, Type - This is a
|
2009-09-26 04:36:54 +08:00
|
|
|
/// byte-swapping load instruction. It loads "Type" bits, byte swaps it,
|
|
|
|
/// then puts it in the bottom bits of the GPRC. TYPE can be either i16
|
|
|
|
/// or i32.
|
This patch implements medium code model support for 64-bit PowerPC.
The default for 64-bit PowerPC is small code model, in which TOC entries
must be addressable using a 16-bit offset from the TOC pointer. Additionally,
only TOC entries are addressed via the TOC pointer.
With medium code model, TOC entries and data sections can all be addressed
via the TOC pointer using a 32-bit offset. Cooperation with the linker
allows 16-bit offsets to be used when these are sufficient, reducing the
number of extra instructions that need to be executed. Medium code model
also does not generate explicit TOC entries in ".section toc" for variables
that are wholly internal to the compilation unit.
Consider a load of an external 4-byte integer. With small code model, the
compiler generates:
ld 3, .LC1@toc(2)
lwz 4, 0(3)
.section .toc,"aw",@progbits
.LC1:
.tc ei[TC],ei
With medium model, it instead generates:
addis 3, 2, .LC1@toc@ha
ld 3, .LC1@toc@l(3)
lwz 4, 0(3)
.section .toc,"aw",@progbits
.LC1:
.tc ei[TC],ei
Here .LC1@toc@ha is a relocation requesting the upper 16 bits of the
32-bit offset of ei's TOC entry from the TOC base pointer. Similarly,
.LC1@toc@l is a relocation requesting the lower 16 bits. Note that if
the linker determines that ei's TOC entry is within a 16-bit offset of
the TOC base pointer, it will replace the "addis" with a "nop", and
replace the "ld" with the identical "ld" instruction from the small
code model example.
Consider next a load of a function-scope static integer. For small code
model, the compiler generates:
ld 3, .LC1@toc(2)
lwz 4, 0(3)
.section .toc,"aw",@progbits
.LC1:
.tc test_fn_static.si[TC],test_fn_static.si
.type test_fn_static.si,@object
.local test_fn_static.si
.comm test_fn_static.si,4,4
For medium code model, the compiler generates:
addis 3, 2, test_fn_static.si@toc@ha
addi 3, 3, test_fn_static.si@toc@l
lwz 4, 0(3)
.type test_fn_static.si,@object
.local test_fn_static.si
.comm test_fn_static.si,4,4
Again, the linker may replace the "addis" with a "nop", calculating only
a 16-bit offset when this is sufficient.
Note that it would be more efficient for the compiler to generate:
addis 3, 2, test_fn_static.si@toc@ha
lwz 4, test_fn_static.si@toc@l(3)
The current patch does not perform this optimization yet. This will be
addressed as a peephole optimization in a later patch.
For the moment, the default code model for 64-bit PowerPC will remain the
small code model. We plan to eventually change the default to medium code
model, which matches current upstream GCC behavior. Note that the different
code models are ABI-compatible, so code compiled with different models will
be linked and execute correctly.
I've tested the regression suite and the application/benchmark test suite in
two ways: Once with the patch as submitted here, and once with additional
logic to force medium code model as the default. The tests all compile
cleanly, with one exception. The mandel-2 application test fails due to an
unrelated ABI compatibility with passing complex numbers. It just so happens
that small code model was incredibly lucky, in that temporary values in
floating-point registers held the expected values needed by the external
library routine that was called incorrectly. My current thought is to correct
the ABI problems with _Complex before making medium code model the default,
to avoid introducing this "regression."
Here are a few comments on how the patch works, since the selection code
can be difficult to follow:
The existing logic for small code model defines three pseudo-instructions:
LDtoc for most uses, LDtocJTI for jump table addresses, and LDtocCPT for
constant pool addresses. These are expanded by SelectCodeCommon(). The
pseudo-instruction approach doesn't work for medium code model, because
we need to generate two instructions when we match the same pattern.
Instead, new logic in PPCDAGToDAGISel::Select() intercepts the TOC_ENTRY
node for medium code model, and generates an ADDIStocHA followed by either
a LDtocL or an ADDItocL. These new node types correspond naturally to
the sequences described above.
The addis/ld sequence is generated for the following cases:
* Jump table addresses
* Function addresses
* External global variables
* Tentative definitions of global variables (common linkage)
The addis/addi sequence is generated for the following cases:
* Constant pool entries
* File-scope static global variables
* Function-scope static variables
Expanding to the two-instruction sequences at select time exposes the
instructions to subsequent optimization, particularly scheduling.
The rest of the processing occurs at assembly time, in
PPCAsmPrinter::EmitInstruction. Each of the instructions is converted to
a "real" PowerPC instruction. When a TOC entry needs to be created, this
is done here in the same manner as for the existing LDtoc, LDtocJTI, and
LDtocCPT pseudo-instructions (I factored out a new routine to handle this).
I had originally thought that if a TOC entry was needed for LDtocL or
ADDItocL, it would already have been generated for the previous ADDIStocHA.
However, at higher optimization levels, the ADDIStocHA may appear in a
different block, which may be assembled textually following the block
containing the LDtocL or ADDItocL. So it is necessary to include the
possibility of creating a new TOC entry for those two instructions.
Note that for LDtocL, we generate a new form of LD called LDrs. This
allows specifying the @toc@l relocation for the offset field of the LD
instruction (i.e., the offset is replaced by a SymbolLo relocation).
When the peephole optimization described above is added, we will need
to do similar things for all immediate-form load and store operations.
The seven "mcm-n.ll" test cases are kept separate because otherwise the
intermingling of various TOC entries and so forth makes the tests fragile
and hard to understand.
The above assumes use of an external assembler. For use of the
integrated assembler, new relocations are added and used by
PPCELFObjectWriter. Testing is done with "mcm-obj.ll", which tests for
proper generation of the various relocations for the same sequences
tested with the external assembler.
llvm-svn: 168708
2012-11-28 01:35:46 +08:00
|
|
|
LBRX,
|
|
|
|
|
|
|
|
/// G8RC = ADDIS_TOC_HA %X2, Symbol - For medium code model, produces
|
|
|
|
/// an ADDIS8 instruction that adds the TOC base register to sym@toc@ha.
|
|
|
|
ADDIS_TOC_HA,
|
|
|
|
|
|
|
|
/// G8RC = LD_TOC_L Symbol, G8RReg - For medium code model, produces a
|
|
|
|
/// LD instruction with base register G8RReg and offset sym@toc@l.
|
|
|
|
/// Preceded by an ADDIS_TOC_HA to form a full 32-bit offset.
|
|
|
|
LD_TOC_L,
|
|
|
|
|
|
|
|
/// G8RC = ADDI_TOC_L G8RReg, Symbol - For medium code model, produces
|
|
|
|
/// an ADDI8 instruction that adds G8RReg to sym@toc@l.
|
|
|
|
/// Preceded by an ADDIS_TOC_HA to form a full 32-bit offset.
|
|
|
|
ADDI_TOC_L
|
2006-01-28 07:34:02 +08:00
|
|
|
};
|
2006-03-20 14:15:45 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
/// Define some predicates that are used for node matching.
|
|
|
|
namespace PPC {
|
2006-04-07 01:23:16 +08:00
|
|
|
/// isVPKUHUMShuffleMask - Return true if this is the shuffle mask for a
|
|
|
|
/// VPKUHUM instruction.
|
2009-04-28 02:41:29 +08:00
|
|
|
bool isVPKUHUMShuffleMask(ShuffleVectorSDNode *N, bool isUnary);
|
2011-02-26 05:41:48 +08:00
|
|
|
|
2006-04-07 01:23:16 +08:00
|
|
|
/// isVPKUWUMShuffleMask - Return true if this is the shuffle mask for a
|
|
|
|
/// VPKUWUM instruction.
|
2009-04-28 02:41:29 +08:00
|
|
|
bool isVPKUWUMShuffleMask(ShuffleVectorSDNode *N, bool isUnary);
|
2006-04-07 05:11:54 +08:00
|
|
|
|
|
|
|
/// isVMRGLShuffleMask - Return true if this is a shuffle mask suitable for
|
|
|
|
/// a VRGL* instruction with the specified unit size (1,2 or 4 bytes).
|
2009-04-28 02:41:29 +08:00
|
|
|
bool isVMRGLShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize,
|
|
|
|
bool isUnary);
|
2006-04-07 05:11:54 +08:00
|
|
|
|
|
|
|
/// isVMRGHShuffleMask - Return true if this is a shuffle mask suitable for
|
|
|
|
/// a VRGH* instruction with the specified unit size (1,2 or 4 bytes).
|
2009-04-28 02:41:29 +08:00
|
|
|
bool isVMRGHShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize,
|
|
|
|
bool isUnary);
|
2011-02-26 05:41:48 +08:00
|
|
|
|
2006-04-07 02:26:28 +08:00
|
|
|
/// isVSLDOIShuffleMask - If this is a vsldoi shuffle mask, return the shift
|
|
|
|
/// amount, otherwise return -1.
|
2006-04-07 06:28:36 +08:00
|
|
|
int isVSLDOIShuffleMask(SDNode *N, bool isUnary);
|
2011-02-26 05:41:48 +08:00
|
|
|
|
2006-03-20 14:15:45 +08:00
|
|
|
/// isSplatShuffleMask - Return true if the specified VECTOR_SHUFFLE operand
|
|
|
|
/// specifies a splat of a single element that is suitable for input to
|
|
|
|
/// VSPLTB/VSPLTH/VSPLTW.
|
2009-04-28 02:41:29 +08:00
|
|
|
bool isSplatShuffleMask(ShuffleVectorSDNode *N, unsigned EltSize);
|
2011-02-26 05:41:48 +08:00
|
|
|
|
2007-07-30 15:51:22 +08:00
|
|
|
/// isAllNegativeZeroVector - Returns true if all elements of build_vector
|
|
|
|
/// are -0.0.
|
|
|
|
bool isAllNegativeZeroVector(SDNode *N);
|
|
|
|
|
2006-03-20 14:15:45 +08:00
|
|
|
/// getVSPLTImmediate - Return the appropriate VSPLT* immediate to splat the
|
|
|
|
/// specified isSplatShuffleMask VECTOR_SHUFFLE mask.
|
2006-04-05 01:25:31 +08:00
|
|
|
unsigned getVSPLTImmediate(SDNode *N, unsigned EltSize);
|
2011-02-26 05:41:48 +08:00
|
|
|
|
2006-04-13 01:37:20 +08:00
|
|
|
/// get_VSPLTI_elt - If this is a build_vector of constants which can be
|
2006-04-08 14:46:53 +08:00
|
|
|
/// formed by using a vspltis[bhw] instruction of the specified element
|
|
|
|
/// size, return the constant being splatted. The ByteSize field indicates
|
|
|
|
/// the number of bytes of each element [124] -> [bhw].
|
2008-07-28 05:46:04 +08:00
|
|
|
SDValue get_VSPLTI_elt(SDNode *N, unsigned ByteSize, SelectionDAG &DAG);
|
2006-03-20 14:15:45 +08:00
|
|
|
}
|
2011-02-26 05:41:48 +08:00
|
|
|
|
2005-10-16 13:39:50 +08:00
|
|
|
class PPCTargetLowering : public TargetLowering {
|
2006-11-02 09:44:04 +08:00
|
|
|
const PPCSubtarget &PPCSubTarget;
|
2010-04-17 22:41:14 +08:00
|
|
|
|
2005-08-17 01:14:42 +08:00
|
|
|
public:
|
2007-08-03 05:21:54 +08:00
|
|
|
explicit PPCTargetLowering(PPCTargetMachine &TM);
|
2011-02-26 05:41:48 +08:00
|
|
|
|
2006-01-10 07:52:17 +08:00
|
|
|
/// getTargetNodeName() - This method returns the name of a target specific
|
|
|
|
/// DAG node.
|
|
|
|
virtual const char *getTargetNodeName(unsigned Opcode) const;
|
2006-11-08 10:15:41 +08:00
|
|
|
|
2011-02-26 05:41:48 +08:00
|
|
|
virtual MVT getShiftAmountTy(EVT LHSTy) const { return MVT::i32; }
|
|
|
|
|
2008-03-10 23:42:14 +08:00
|
|
|
/// getSetCCResultType - Return the ISD::SETCC ValueType
|
2011-09-07 03:07:46 +08:00
|
|
|
virtual EVT getSetCCResultType(EVT VT) const;
|
2008-03-10 23:42:14 +08:00
|
|
|
|
2006-11-08 10:15:41 +08:00
|
|
|
/// getPreIndexedAddressParts - returns true by value, base pointer and
|
|
|
|
/// offset pointer and addressing mode by reference if the node's address
|
|
|
|
/// can be legally represented as pre-indexed load / store address.
|
2008-07-28 05:46:04 +08:00
|
|
|
virtual bool getPreIndexedAddressParts(SDNode *N, SDValue &Base,
|
|
|
|
SDValue &Offset,
|
2006-11-10 01:55:04 +08:00
|
|
|
ISD::MemIndexedMode &AM,
|
2009-01-16 00:29:45 +08:00
|
|
|
SelectionDAG &DAG) const;
|
2011-02-26 05:41:48 +08:00
|
|
|
|
2006-11-08 10:15:41 +08:00
|
|
|
/// SelectAddressRegReg - Given the specified addressed, check to see if it
|
|
|
|
/// can be represented as an indexed [r+r] operation. Returns false if it
|
|
|
|
/// can be more efficiently represented with [r+imm].
|
2008-07-28 05:46:04 +08:00
|
|
|
bool SelectAddressRegReg(SDValue N, SDValue &Base, SDValue &Index,
|
2009-01-16 00:29:45 +08:00
|
|
|
SelectionDAG &DAG) const;
|
2011-02-26 05:41:48 +08:00
|
|
|
|
2006-11-08 10:15:41 +08:00
|
|
|
/// SelectAddressRegImm - Returns true if the address N can be represented
|
|
|
|
/// by a base register plus a signed 16-bit displacement [r+imm], and if it
|
|
|
|
/// is not better represented as reg+reg.
|
2008-07-28 05:46:04 +08:00
|
|
|
bool SelectAddressRegImm(SDValue N, SDValue &Disp, SDValue &Base,
|
2009-01-16 00:29:45 +08:00
|
|
|
SelectionDAG &DAG) const;
|
2011-02-26 05:41:48 +08:00
|
|
|
|
2006-11-08 10:15:41 +08:00
|
|
|
/// SelectAddressRegRegOnly - Given the specified addressed, force it to be
|
|
|
|
/// represented as an indexed [r+r] operation.
|
2008-07-28 05:46:04 +08:00
|
|
|
bool SelectAddressRegRegOnly(SDValue N, SDValue &Base, SDValue &Index,
|
2009-01-16 00:29:45 +08:00
|
|
|
SelectionDAG &DAG) const;
|
2006-11-08 10:15:41 +08:00
|
|
|
|
|
|
|
/// SelectAddressRegImmShift - Returns true if the address N can be
|
|
|
|
/// represented by a base register plus a signed 14-bit displacement
|
|
|
|
/// [r+imm*4]. Suitable for use by STD and friends.
|
2008-07-28 05:46:04 +08:00
|
|
|
bool SelectAddressRegImmShift(SDValue N, SDValue &Disp, SDValue &Base,
|
2009-01-16 00:29:45 +08:00
|
|
|
SelectionDAG &DAG) const;
|
2006-11-08 10:15:41 +08:00
|
|
|
|
2012-04-02 03:23:08 +08:00
|
|
|
Sched::Preference getSchedulingPreference(SDNode *N) const;
|
2011-02-26 05:41:48 +08:00
|
|
|
|
2005-08-26 08:52:45 +08:00
|
|
|
/// LowerOperation - Provide custom lowering hooks for some operations.
|
|
|
|
///
|
2010-04-17 23:26:15 +08:00
|
|
|
virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
|
2007-11-29 02:44:47 +08:00
|
|
|
|
2008-12-01 19:39:25 +08:00
|
|
|
/// ReplaceNodeResults - Replace the results of node with an illegal result
|
|
|
|
/// type with new values built out of custom code.
|
|
|
|
///
|
|
|
|
virtual void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results,
|
2010-04-17 23:26:15 +08:00
|
|
|
SelectionDAG &DAG) const;
|
2008-12-01 19:39:25 +08:00
|
|
|
|
2008-07-28 05:46:04 +08:00
|
|
|
virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
|
2011-02-26 05:41:48 +08:00
|
|
|
|
2008-07-28 05:46:04 +08:00
|
|
|
virtual void computeMaskedBitsForTargetNode(const SDValue Op,
|
2011-02-26 05:41:48 +08:00
|
|
|
APInt &KnownZero,
|
2008-02-13 08:35:47 +08:00
|
|
|
APInt &KnownOne,
|
2007-06-22 22:59:07 +08:00
|
|
|
const SelectionDAG &DAG,
|
2006-04-02 14:26:07 +08:00
|
|
|
unsigned Depth = 0) const;
|
2005-10-19 07:23:37 +08:00
|
|
|
|
2010-05-01 08:01:06 +08:00
|
|
|
virtual MachineBasicBlock *
|
|
|
|
EmitInstrWithCustomInserter(MachineInstr *MI,
|
|
|
|
MachineBasicBlock *MBB) const;
|
2011-02-26 05:41:48 +08:00
|
|
|
MachineBasicBlock *EmitAtomicBinary(MachineInstr *MI,
|
2008-08-26 06:34:37 +08:00
|
|
|
MachineBasicBlock *MBB, bool is64Bit,
|
2009-02-08 00:15:20 +08:00
|
|
|
unsigned BinOpcode) const;
|
2011-02-26 05:41:48 +08:00
|
|
|
MachineBasicBlock *EmitPartwordAtomicBinary(MachineInstr *MI,
|
|
|
|
MachineBasicBlock *MBB,
|
2009-02-08 00:15:20 +08:00
|
|
|
bool is8bit, unsigned Opcode) const;
|
2011-02-26 05:41:48 +08:00
|
|
|
|
2007-03-25 10:14:49 +08:00
|
|
|
ConstraintType getConstraintType(const std::string &Constraint) const;
|
2010-10-30 01:29:13 +08:00
|
|
|
|
|
|
|
/// Examine constraint string and operand type and determine a weight value.
|
|
|
|
/// The operand object must already have been set up with the operand type.
|
|
|
|
ConstraintWeight getSingleConstraintMatchWeight(
|
|
|
|
AsmOperandInfo &info, const char *constraint) const;
|
|
|
|
|
2011-02-26 05:41:48 +08:00
|
|
|
std::pair<unsigned, const TargetRegisterClass*>
|
2006-11-02 09:44:04 +08:00
|
|
|
getRegForInlineAsmConstraint(const std::string &Constraint,
|
2009-08-11 06:56:29 +08:00
|
|
|
EVT VT) const;
|
2006-03-14 07:20:37 +08:00
|
|
|
|
2008-02-29 06:31:51 +08:00
|
|
|
/// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
|
|
|
|
/// function arguments in the caller parameter area. This is the actual
|
|
|
|
/// alignment, not its logarithm.
|
2011-07-18 12:54:35 +08:00
|
|
|
unsigned getByValTypeAlignment(Type *Ty) const;
|
2008-02-29 06:31:51 +08:00
|
|
|
|
2007-08-25 08:47:38 +08:00
|
|
|
/// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
|
2010-06-26 05:55:36 +08:00
|
|
|
/// vector. If it is invalid, don't add anything to Ops.
|
2008-07-28 05:46:04 +08:00
|
|
|
virtual void LowerAsmOperandForConstraint(SDValue Op,
|
2011-06-03 07:16:42 +08:00
|
|
|
std::string &Constraint,
|
2008-07-28 05:46:04 +08:00
|
|
|
std::vector<SDValue> &Ops,
|
2008-04-27 07:02:14 +08:00
|
|
|
SelectionDAG &DAG) const;
|
2011-02-26 05:41:48 +08:00
|
|
|
|
2007-03-31 07:15:24 +08:00
|
|
|
/// isLegalAddressingMode - Return true if the addressing mode represented
|
|
|
|
/// by AM is legal for this target, for a load/store of the specified type.
|
2011-07-18 12:54:35 +08:00
|
|
|
virtual bool isLegalAddressingMode(const AddrMode &AM, Type *Ty)const;
|
2011-02-26 05:41:48 +08:00
|
|
|
|
2006-03-14 07:20:37 +08:00
|
|
|
/// isLegalAddressImmediate - Return true if the integer value can be used
|
2007-03-13 07:29:01 +08:00
|
|
|
/// as the offset of the target addressing mode for load / store of the
|
|
|
|
/// given type.
|
2011-07-18 12:54:35 +08:00
|
|
|
virtual bool isLegalAddressImmediate(int64_t V, Type *Ty) const;
|
2007-03-13 07:29:01 +08:00
|
|
|
|
|
|
|
/// isLegalAddressImmediate - Return true if the GlobalValue can be used as
|
|
|
|
/// the offset of the target addressing mode.
|
|
|
|
virtual bool isLegalAddressImmediate(GlobalValue *GV) const;
|
2007-03-01 21:11:38 +08:00
|
|
|
|
2008-10-21 11:41:46 +08:00
|
|
|
virtual bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const;
|
2011-02-26 05:41:48 +08:00
|
|
|
|
2010-04-02 04:10:42 +08:00
|
|
|
/// getOptimalMemOpType - Returns the target specific optimal type for load
|
2010-04-03 03:36:14 +08:00
|
|
|
/// and store operations as a result of memset, memcpy, and memmove
|
|
|
|
/// lowering. If DstAlign is zero that means it's safe to destination
|
|
|
|
/// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
|
|
|
|
/// means there isn't a need to check it against alignment requirement,
|
2012-12-12 10:34:41 +08:00
|
|
|
/// probably because the source does not need to be loaded. If 'IsMemset' is
|
|
|
|
/// true, that means it's expanding a memset. If 'ZeroMemset' is true, that
|
|
|
|
/// means it's a memset of zero. 'MemcpyStrSrc' indicates whether the memcpy
|
|
|
|
/// source is constant so it does not need to be loaded.
|
2010-04-17 04:11:05 +08:00
|
|
|
/// It returns EVT::Other if the type should be determined using generic
|
|
|
|
/// target-independent logic.
|
2010-04-03 03:36:14 +08:00
|
|
|
virtual EVT
|
2012-12-12 10:34:41 +08:00
|
|
|
getOptimalMemOpType(uint64_t Size, unsigned DstAlign, unsigned SrcAlign,
|
|
|
|
bool IsMemset, bool ZeroMemset, bool MemcpyStrSrc,
|
2010-04-17 04:11:05 +08:00
|
|
|
MachineFunction &MF) const;
|
2008-10-21 11:41:46 +08:00
|
|
|
|
2012-06-22 08:49:52 +08:00
|
|
|
/// isFMAFasterThanMulAndAdd - Return true if an FMA operation is faster than
|
|
|
|
/// a pair of mul and add instructions. fmuladd intrinsics will be expanded to
|
|
|
|
/// FMAs when this method returns true (and FMAs are legal), otherwise fmuladd
|
|
|
|
/// is expanded to mul + add.
|
|
|
|
virtual bool isFMAFasterThanMulAndAdd(EVT VT) const;
|
|
|
|
|
2008-04-19 09:30:48 +08:00
|
|
|
private:
|
2008-07-28 05:46:04 +08:00
|
|
|
SDValue getFramePointerFrameIndex(SelectionDAG & DAG) const;
|
|
|
|
SDValue getReturnAddrFrameIndex(SelectionDAG & DAG) const;
|
2008-04-30 17:16:33 +08:00
|
|
|
|
2010-01-27 08:07:07 +08:00
|
|
|
bool
|
|
|
|
IsEligibleForTailCallOptimization(SDValue Callee,
|
|
|
|
CallingConv::ID CalleeCC,
|
|
|
|
bool isVarArg,
|
|
|
|
const SmallVectorImpl<ISD::InputArg> &Ins,
|
|
|
|
SelectionDAG& DAG) const;
|
|
|
|
|
2008-07-28 05:46:04 +08:00
|
|
|
SDValue EmitTailCallLoadFPAndRetAddr(SelectionDAG & DAG,
|
2009-02-05 04:06:27 +08:00
|
|
|
int SPDiff,
|
|
|
|
SDValue Chain,
|
|
|
|
SDValue &LROpOut,
|
|
|
|
SDValue &FPOpOut,
|
2009-07-03 14:47:08 +08:00
|
|
|
bool isDarwinABI,
|
2010-04-17 23:26:15 +08:00
|
|
|
DebugLoc dl) const;
|
|
|
|
|
|
|
|
SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
|
|
|
|
SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
|
|
|
|
SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
|
|
|
|
SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
|
2012-06-05 01:36:38 +08:00
|
|
|
SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
|
2010-04-17 23:26:15 +08:00
|
|
|
SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
|
|
|
|
SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG) const;
|
|
|
|
SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG) const;
|
2011-09-06 21:37:06 +08:00
|
|
|
SDValue LowerINIT_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) const;
|
|
|
|
SDValue LowerADJUST_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) const;
|
2008-07-28 05:46:04 +08:00
|
|
|
SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG,
|
2010-04-17 23:26:15 +08:00
|
|
|
const PPCSubtarget &Subtarget) const;
|
2010-04-17 22:41:14 +08:00
|
|
|
SDValue LowerVAARG(SDValue Op, SelectionDAG &DAG,
|
2010-04-17 23:26:15 +08:00
|
|
|
const PPCSubtarget &Subtarget) const;
|
2008-07-28 05:46:04 +08:00
|
|
|
SDValue LowerSTACKRESTORE(SDValue Op, SelectionDAG &DAG,
|
2010-04-17 23:26:15 +08:00
|
|
|
const PPCSubtarget &Subtarget) const;
|
2008-07-28 05:46:04 +08:00
|
|
|
SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG,
|
2010-04-17 23:26:15 +08:00
|
|
|
const PPCSubtarget &Subtarget) const;
|
|
|
|
SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const;
|
|
|
|
SDValue LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG, DebugLoc dl) const;
|
|
|
|
SDValue LowerSINT_TO_FP(SDValue Op, SelectionDAG &DAG) const;
|
|
|
|
SDValue LowerFLT_ROUNDS_(SDValue Op, SelectionDAG &DAG) const;
|
|
|
|
SDValue LowerSHL_PARTS(SDValue Op, SelectionDAG &DAG) const;
|
|
|
|
SDValue LowerSRL_PARTS(SDValue Op, SelectionDAG &DAG) const;
|
|
|
|
SDValue LowerSRA_PARTS(SDValue Op, SelectionDAG &DAG) const;
|
|
|
|
SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const;
|
|
|
|
SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const;
|
|
|
|
SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const;
|
|
|
|
SDValue LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) const;
|
|
|
|
SDValue LowerMUL(SDValue Op, SelectionDAG &DAG) const;
|
Major calling convention code refactoring.
Instead of awkwardly encoding calling-convention information with ISD::CALL,
ISD::FORMAL_ARGUMENTS, ISD::RET, and ISD::ARG_FLAGS nodes, TargetLowering
provides three virtual functions for targets to override:
LowerFormalArguments, LowerCall, and LowerRet, which replace the custom
lowering done on the special nodes. They provide the same information, but
in a more immediately usable format.
This also reworks much of the target-independent tail call logic. The
decision of whether or not to perform a tail call is now cleanly split
between target-independent portions, and the target dependent portion
in IsEligibleForTailCallOptimization.
This also synchronizes all in-tree targets, to help enable future
refactoring and feature work.
llvm-svn: 78142
2009-08-05 09:29:28 +08:00
|
|
|
|
|
|
|
SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
|
2009-09-02 16:44:58 +08:00
|
|
|
CallingConv::ID CallConv, bool isVarArg,
|
Major calling convention code refactoring.
Instead of awkwardly encoding calling-convention information with ISD::CALL,
ISD::FORMAL_ARGUMENTS, ISD::RET, and ISD::ARG_FLAGS nodes, TargetLowering
provides three virtual functions for targets to override:
LowerFormalArguments, LowerCall, and LowerRet, which replace the custom
lowering done on the special nodes. They provide the same information, but
in a more immediately usable format.
This also reworks much of the target-independent tail call logic. The
decision of whether or not to perform a tail call is now cleanly split
between target-independent portions, and the target dependent portion
in IsEligibleForTailCallOptimization.
This also synchronizes all in-tree targets, to help enable future
refactoring and feature work.
llvm-svn: 78142
2009-08-05 09:29:28 +08:00
|
|
|
const SmallVectorImpl<ISD::InputArg> &Ins,
|
|
|
|
DebugLoc dl, SelectionDAG &DAG,
|
2010-04-17 23:26:15 +08:00
|
|
|
SmallVectorImpl<SDValue> &InVals) const;
|
2009-09-02 16:44:58 +08:00
|
|
|
SDValue FinishCall(CallingConv::ID CallConv, DebugLoc dl, bool isTailCall,
|
Major calling convention code refactoring.
Instead of awkwardly encoding calling-convention information with ISD::CALL,
ISD::FORMAL_ARGUMENTS, ISD::RET, and ISD::ARG_FLAGS nodes, TargetLowering
provides three virtual functions for targets to override:
LowerFormalArguments, LowerCall, and LowerRet, which replace the custom
lowering done on the special nodes. They provide the same information, but
in a more immediately usable format.
This also reworks much of the target-independent tail call logic. The
decision of whether or not to perform a tail call is now cleanly split
between target-independent portions, and the target dependent portion
in IsEligibleForTailCallOptimization.
This also synchronizes all in-tree targets, to help enable future
refactoring and feature work.
llvm-svn: 78142
2009-08-05 09:29:28 +08:00
|
|
|
bool isVarArg,
|
|
|
|
SelectionDAG &DAG,
|
|
|
|
SmallVector<std::pair<unsigned, SDValue>, 8>
|
|
|
|
&RegsToPass,
|
|
|
|
SDValue InFlag, SDValue Chain,
|
|
|
|
SDValue &Callee,
|
|
|
|
int SPDiff, unsigned NumBytes,
|
|
|
|
const SmallVectorImpl<ISD::InputArg> &Ins,
|
2010-04-17 23:26:15 +08:00
|
|
|
SmallVectorImpl<SDValue> &InVals) const;
|
Major calling convention code refactoring.
Instead of awkwardly encoding calling-convention information with ISD::CALL,
ISD::FORMAL_ARGUMENTS, ISD::RET, and ISD::ARG_FLAGS nodes, TargetLowering
provides three virtual functions for targets to override:
LowerFormalArguments, LowerCall, and LowerRet, which replace the custom
lowering done on the special nodes. They provide the same information, but
in a more immediately usable format.
This also reworks much of the target-independent tail call logic. The
decision of whether or not to perform a tail call is now cleanly split
between target-independent portions, and the target dependent portion
in IsEligibleForTailCallOptimization.
This also synchronizes all in-tree targets, to help enable future
refactoring and feature work.
llvm-svn: 78142
2009-08-05 09:29:28 +08:00
|
|
|
|
|
|
|
virtual SDValue
|
|
|
|
LowerFormalArguments(SDValue Chain,
|
2009-09-02 16:44:58 +08:00
|
|
|
CallingConv::ID CallConv, bool isVarArg,
|
Major calling convention code refactoring.
Instead of awkwardly encoding calling-convention information with ISD::CALL,
ISD::FORMAL_ARGUMENTS, ISD::RET, and ISD::ARG_FLAGS nodes, TargetLowering
provides three virtual functions for targets to override:
LowerFormalArguments, LowerCall, and LowerRet, which replace the custom
lowering done on the special nodes. They provide the same information, but
in a more immediately usable format.
This also reworks much of the target-independent tail call logic. The
decision of whether or not to perform a tail call is now cleanly split
between target-independent portions, and the target dependent portion
in IsEligibleForTailCallOptimization.
This also synchronizes all in-tree targets, to help enable future
refactoring and feature work.
llvm-svn: 78142
2009-08-05 09:29:28 +08:00
|
|
|
const SmallVectorImpl<ISD::InputArg> &Ins,
|
|
|
|
DebugLoc dl, SelectionDAG &DAG,
|
2010-04-17 23:26:15 +08:00
|
|
|
SmallVectorImpl<SDValue> &InVals) const;
|
Major calling convention code refactoring.
Instead of awkwardly encoding calling-convention information with ISD::CALL,
ISD::FORMAL_ARGUMENTS, ISD::RET, and ISD::ARG_FLAGS nodes, TargetLowering
provides three virtual functions for targets to override:
LowerFormalArguments, LowerCall, and LowerRet, which replace the custom
lowering done on the special nodes. They provide the same information, but
in a more immediately usable format.
This also reworks much of the target-independent tail call logic. The
decision of whether or not to perform a tail call is now cleanly split
between target-independent portions, and the target dependent portion
in IsEligibleForTailCallOptimization.
This also synchronizes all in-tree targets, to help enable future
refactoring and feature work.
llvm-svn: 78142
2009-08-05 09:29:28 +08:00
|
|
|
|
|
|
|
virtual SDValue
|
2012-05-26 00:35:28 +08:00
|
|
|
LowerCall(TargetLowering::CallLoweringInfo &CLI,
|
2010-04-17 23:26:15 +08:00
|
|
|
SmallVectorImpl<SDValue> &InVals) const;
|
Major calling convention code refactoring.
Instead of awkwardly encoding calling-convention information with ISD::CALL,
ISD::FORMAL_ARGUMENTS, ISD::RET, and ISD::ARG_FLAGS nodes, TargetLowering
provides three virtual functions for targets to override:
LowerFormalArguments, LowerCall, and LowerRet, which replace the custom
lowering done on the special nodes. They provide the same information, but
in a more immediately usable format.
This also reworks much of the target-independent tail call logic. The
decision of whether or not to perform a tail call is now cleanly split
between target-independent portions, and the target dependent portion
in IsEligibleForTailCallOptimization.
This also synchronizes all in-tree targets, to help enable future
refactoring and feature work.
llvm-svn: 78142
2009-08-05 09:29:28 +08:00
|
|
|
|
2011-10-15 03:51:36 +08:00
|
|
|
virtual bool
|
|
|
|
CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF,
|
|
|
|
bool isVarArg,
|
|
|
|
const SmallVectorImpl<ISD::OutputArg> &Outs,
|
|
|
|
LLVMContext &Context) const;
|
|
|
|
|
Major calling convention code refactoring.
Instead of awkwardly encoding calling-convention information with ISD::CALL,
ISD::FORMAL_ARGUMENTS, ISD::RET, and ISD::ARG_FLAGS nodes, TargetLowering
provides three virtual functions for targets to override:
LowerFormalArguments, LowerCall, and LowerRet, which replace the custom
lowering done on the special nodes. They provide the same information, but
in a more immediately usable format.
This also reworks much of the target-independent tail call logic. The
decision of whether or not to perform a tail call is now cleanly split
between target-independent portions, and the target dependent portion
in IsEligibleForTailCallOptimization.
This also synchronizes all in-tree targets, to help enable future
refactoring and feature work.
llvm-svn: 78142
2009-08-05 09:29:28 +08:00
|
|
|
virtual SDValue
|
|
|
|
LowerReturn(SDValue Chain,
|
2009-09-02 16:44:58 +08:00
|
|
|
CallingConv::ID CallConv, bool isVarArg,
|
Major calling convention code refactoring.
Instead of awkwardly encoding calling-convention information with ISD::CALL,
ISD::FORMAL_ARGUMENTS, ISD::RET, and ISD::ARG_FLAGS nodes, TargetLowering
provides three virtual functions for targets to override:
LowerFormalArguments, LowerCall, and LowerRet, which replace the custom
lowering done on the special nodes. They provide the same information, but
in a more immediately usable format.
This also reworks much of the target-independent tail call logic. The
decision of whether or not to perform a tail call is now cleanly split
between target-independent portions, and the target dependent portion
in IsEligibleForTailCallOptimization.
This also synchronizes all in-tree targets, to help enable future
refactoring and feature work.
llvm-svn: 78142
2009-08-05 09:29:28 +08:00
|
|
|
const SmallVectorImpl<ISD::OutputArg> &Outs,
|
2010-07-07 23:54:55 +08:00
|
|
|
const SmallVectorImpl<SDValue> &OutVals,
|
2010-04-17 23:26:15 +08:00
|
|
|
DebugLoc dl, SelectionDAG &DAG) const;
|
Major calling convention code refactoring.
Instead of awkwardly encoding calling-convention information with ISD::CALL,
ISD::FORMAL_ARGUMENTS, ISD::RET, and ISD::ARG_FLAGS nodes, TargetLowering
provides three virtual functions for targets to override:
LowerFormalArguments, LowerCall, and LowerRet, which replace the custom
lowering done on the special nodes. They provide the same information, but
in a more immediately usable format.
This also reworks much of the target-independent tail call logic. The
decision of whether or not to perform a tail call is now cleanly split
between target-independent portions, and the target dependent portion
in IsEligibleForTailCallOptimization.
This also synchronizes all in-tree targets, to help enable future
refactoring and feature work.
llvm-svn: 78142
2009-08-05 09:29:28 +08:00
|
|
|
|
2012-10-23 23:51:16 +08:00
|
|
|
SDValue
|
|
|
|
extendArgForPPC64(ISD::ArgFlagsTy Flags, EVT ObjectVT, SelectionDAG &DAG,
|
|
|
|
SDValue ArgVal, DebugLoc dl) const;
|
|
|
|
|
|
|
|
void
|
|
|
|
setMinReservedArea(MachineFunction &MF, SelectionDAG &DAG,
|
|
|
|
unsigned nAltivecParamsAtEnd,
|
|
|
|
unsigned MinReservedArea, bool isPPC64) const;
|
|
|
|
|
Major calling convention code refactoring.
Instead of awkwardly encoding calling-convention information with ISD::CALL,
ISD::FORMAL_ARGUMENTS, ISD::RET, and ISD::ARG_FLAGS nodes, TargetLowering
provides three virtual functions for targets to override:
LowerFormalArguments, LowerCall, and LowerRet, which replace the custom
lowering done on the special nodes. They provide the same information, but
in a more immediately usable format.
This also reworks much of the target-independent tail call logic. The
decision of whether or not to perform a tail call is now cleanly split
between target-independent portions, and the target dependent portion
in IsEligibleForTailCallOptimization.
This also synchronizes all in-tree targets, to help enable future
refactoring and feature work.
llvm-svn: 78142
2009-08-05 09:29:28 +08:00
|
|
|
SDValue
|
2012-10-06 05:27:08 +08:00
|
|
|
LowerFormalArguments_Darwin(SDValue Chain,
|
|
|
|
CallingConv::ID CallConv, bool isVarArg,
|
|
|
|
const SmallVectorImpl<ISD::InputArg> &Ins,
|
|
|
|
DebugLoc dl, SelectionDAG &DAG,
|
|
|
|
SmallVectorImpl<SDValue> &InVals) const;
|
|
|
|
SDValue
|
|
|
|
LowerFormalArguments_64SVR4(SDValue Chain,
|
2009-09-02 16:44:58 +08:00
|
|
|
CallingConv::ID CallConv, bool isVarArg,
|
Major calling convention code refactoring.
Instead of awkwardly encoding calling-convention information with ISD::CALL,
ISD::FORMAL_ARGUMENTS, ISD::RET, and ISD::ARG_FLAGS nodes, TargetLowering
provides three virtual functions for targets to override:
LowerFormalArguments, LowerCall, and LowerRet, which replace the custom
lowering done on the special nodes. They provide the same information, but
in a more immediately usable format.
This also reworks much of the target-independent tail call logic. The
decision of whether or not to perform a tail call is now cleanly split
between target-independent portions, and the target dependent portion
in IsEligibleForTailCallOptimization.
This also synchronizes all in-tree targets, to help enable future
refactoring and feature work.
llvm-svn: 78142
2009-08-05 09:29:28 +08:00
|
|
|
const SmallVectorImpl<ISD::InputArg> &Ins,
|
|
|
|
DebugLoc dl, SelectionDAG &DAG,
|
2010-04-17 23:26:15 +08:00
|
|
|
SmallVectorImpl<SDValue> &InVals) const;
|
Major calling convention code refactoring.
Instead of awkwardly encoding calling-convention information with ISD::CALL,
ISD::FORMAL_ARGUMENTS, ISD::RET, and ISD::ARG_FLAGS nodes, TargetLowering
provides three virtual functions for targets to override:
LowerFormalArguments, LowerCall, and LowerRet, which replace the custom
lowering done on the special nodes. They provide the same information, but
in a more immediately usable format.
This also reworks much of the target-independent tail call logic. The
decision of whether or not to perform a tail call is now cleanly split
between target-independent portions, and the target dependent portion
in IsEligibleForTailCallOptimization.
This also synchronizes all in-tree targets, to help enable future
refactoring and feature work.
llvm-svn: 78142
2009-08-05 09:29:28 +08:00
|
|
|
SDValue
|
2012-09-19 23:42:13 +08:00
|
|
|
LowerFormalArguments_32SVR4(SDValue Chain,
|
|
|
|
CallingConv::ID CallConv, bool isVarArg,
|
|
|
|
const SmallVectorImpl<ISD::InputArg> &Ins,
|
|
|
|
DebugLoc dl, SelectionDAG &DAG,
|
|
|
|
SmallVectorImpl<SDValue> &InVals) const;
|
Major calling convention code refactoring.
Instead of awkwardly encoding calling-convention information with ISD::CALL,
ISD::FORMAL_ARGUMENTS, ISD::RET, and ISD::ARG_FLAGS nodes, TargetLowering
provides three virtual functions for targets to override:
LowerFormalArguments, LowerCall, and LowerRet, which replace the custom
lowering done on the special nodes. They provide the same information, but
in a more immediately usable format.
This also reworks much of the target-independent tail call logic. The
decision of whether or not to perform a tail call is now cleanly split
between target-independent portions, and the target dependent portion
in IsEligibleForTailCallOptimization.
This also synchronizes all in-tree targets, to help enable future
refactoring and feature work.
llvm-svn: 78142
2009-08-05 09:29:28 +08:00
|
|
|
|
|
|
|
SDValue
|
2012-10-23 23:51:16 +08:00
|
|
|
createMemcpyOutsideCallSeq(SDValue Arg, SDValue PtrOff,
|
|
|
|
SDValue CallSeqStart, ISD::ArgFlagsTy Flags,
|
|
|
|
SelectionDAG &DAG, DebugLoc dl) const;
|
|
|
|
|
|
|
|
SDValue
|
|
|
|
LowerCall_Darwin(SDValue Chain, SDValue Callee,
|
|
|
|
CallingConv::ID CallConv,
|
|
|
|
bool isVarArg, bool isTailCall,
|
|
|
|
const SmallVectorImpl<ISD::OutputArg> &Outs,
|
|
|
|
const SmallVectorImpl<SDValue> &OutVals,
|
|
|
|
const SmallVectorImpl<ISD::InputArg> &Ins,
|
|
|
|
DebugLoc dl, SelectionDAG &DAG,
|
|
|
|
SmallVectorImpl<SDValue> &InVals) const;
|
|
|
|
SDValue
|
|
|
|
LowerCall_64SVR4(SDValue Chain, SDValue Callee,
|
2012-09-19 23:42:13 +08:00
|
|
|
CallingConv::ID CallConv,
|
2012-02-29 02:51:51 +08:00
|
|
|
bool isVarArg, bool isTailCall,
|
Major calling convention code refactoring.
Instead of awkwardly encoding calling-convention information with ISD::CALL,
ISD::FORMAL_ARGUMENTS, ISD::RET, and ISD::ARG_FLAGS nodes, TargetLowering
provides three virtual functions for targets to override:
LowerFormalArguments, LowerCall, and LowerRet, which replace the custom
lowering done on the special nodes. They provide the same information, but
in a more immediately usable format.
This also reworks much of the target-independent tail call logic. The
decision of whether or not to perform a tail call is now cleanly split
between target-independent portions, and the target dependent portion
in IsEligibleForTailCallOptimization.
This also synchronizes all in-tree targets, to help enable future
refactoring and feature work.
llvm-svn: 78142
2009-08-05 09:29:28 +08:00
|
|
|
const SmallVectorImpl<ISD::OutputArg> &Outs,
|
2010-07-07 23:54:55 +08:00
|
|
|
const SmallVectorImpl<SDValue> &OutVals,
|
Major calling convention code refactoring.
Instead of awkwardly encoding calling-convention information with ISD::CALL,
ISD::FORMAL_ARGUMENTS, ISD::RET, and ISD::ARG_FLAGS nodes, TargetLowering
provides three virtual functions for targets to override:
LowerFormalArguments, LowerCall, and LowerRet, which replace the custom
lowering done on the special nodes. They provide the same information, but
in a more immediately usable format.
This also reworks much of the target-independent tail call logic. The
decision of whether or not to perform a tail call is now cleanly split
between target-independent portions, and the target dependent portion
in IsEligibleForTailCallOptimization.
This also synchronizes all in-tree targets, to help enable future
refactoring and feature work.
llvm-svn: 78142
2009-08-05 09:29:28 +08:00
|
|
|
const SmallVectorImpl<ISD::InputArg> &Ins,
|
|
|
|
DebugLoc dl, SelectionDAG &DAG,
|
2010-04-17 23:26:15 +08:00
|
|
|
SmallVectorImpl<SDValue> &InVals) const;
|
Major calling convention code refactoring.
Instead of awkwardly encoding calling-convention information with ISD::CALL,
ISD::FORMAL_ARGUMENTS, ISD::RET, and ISD::ARG_FLAGS nodes, TargetLowering
provides three virtual functions for targets to override:
LowerFormalArguments, LowerCall, and LowerRet, which replace the custom
lowering done on the special nodes. They provide the same information, but
in a more immediately usable format.
This also reworks much of the target-independent tail call logic. The
decision of whether or not to perform a tail call is now cleanly split
between target-independent portions, and the target dependent portion
in IsEligibleForTailCallOptimization.
This also synchronizes all in-tree targets, to help enable future
refactoring and feature work.
llvm-svn: 78142
2009-08-05 09:29:28 +08:00
|
|
|
SDValue
|
2012-09-19 23:42:13 +08:00
|
|
|
LowerCall_32SVR4(SDValue Chain, SDValue Callee, CallingConv::ID CallConv,
|
|
|
|
bool isVarArg, bool isTailCall,
|
|
|
|
const SmallVectorImpl<ISD::OutputArg> &Outs,
|
|
|
|
const SmallVectorImpl<SDValue> &OutVals,
|
|
|
|
const SmallVectorImpl<ISD::InputArg> &Ins,
|
|
|
|
DebugLoc dl, SelectionDAG &DAG,
|
|
|
|
SmallVectorImpl<SDValue> &InVals) const;
|
2005-08-17 01:14:42 +08:00
|
|
|
};
|
|
|
|
}
|
|
|
|
|
|
|
|
#endif // LLVM_TARGET_POWERPC_PPC32ISELLOWERING_H
|